SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product PRODUCT FEATURES FREQUENCY TABLE Supports Pentium . Pentium II & Pro CPUs. Designed to meet Intel chipset specification 4 CPU and 8 PCI clocks Two 48 MHz fixed clocks for USB and Super IO. Separate supply pins for mixed CPU, IOAPIC, and Fixed/PCI clocks < 175 ps Max. skew among CPU clocks. < 250 ps Max. skew among PCI clocks. Controlled current output buffers Power management feature 2 IOAPIC clocks for multiprocessor support. 48-pin SSOP package Spread Spectrum EMI reduction mode BLOCK DIAGRAM VDDR Xin Xout REF OSC REF[1:3] VDDI IOAPIC[1:2} VDDC CPU[1:4] VDDP FS[0:2] CSTOP PCIF PLL1 VDDP PSTOP PCI[1:7] #SSM VDDF PLL2 48M[1:2] INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 FS2 FS1 FS0 CPU PCI 0 0 0 Tri-State Tri-State 0 1 1 66 (66.58)* 33.3* 1 0 0 Ref/2 Ref/4 1 1 1 100 (99.7)** 33.2** NOTE: *Down Spread 1.25% (total) **Down Spread .5% (total) CONNECTION DIAGRAM ,0,6* 5() 9''5 5() 5() 966 9'', ;,1 ,2$3,& ;287 ,2$3,& 966 966 3&,B) 1& 3&, 9''& 9''3 &38 3&, &38 3&, 966 966 9''& 3&, &38 3&, &38 9''3 966 3&, 9'' 3&, 966 966 36723 9'' &6723 966 3' 9'') 660 0 )6 0 )6 966 )6 Rev 1.8 2/19/98 Page 1 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product PIN DESCRIPTION PIN No. 4 Pin Name Xin PWR I/O TYPE Description VDD I OSC1 5 Xout VDD O OSC1 25, 26, 27 40, 39, 36, 35 45, 44 FS(0:2) - I CPU(1:4) VDDC O PAD PU BUF1 On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal O-chip reference oscillator output pin. Drives an external parallel resonant crystal when an externally generated reference signal is used, is left unconnected Frequency select input pins. See frequency select table on page 1. These pin has an internal pull-up Clock outputs. CPU frequency table specified on page 1. IOAPIC(1:2) VDDI O BUF2 8, 10, 11, 13, 14, 16, 17 7 PCI(1:7) VDDP O BUF4 PCI_F VDDP O BUF4 3, 6, 12, 18, 20, 24, 32, 34, 38, 43 46 VSS - P - VDDI - P - 9, 15 VDDP - P - 21 48 37, 41 19, 33 1, 2, 47 22, 23 31 VDDF VDDR VDDC VDD REF(1:3) 48M(1:2) PSTOP - P P P - VDDR VDDF - O O I 30 CSTOP - I 28 #SSM - I 29 PD - I BUF3 BUF3 PAD PU PAD PU PAD PU PAD PU - IOAPIC clock for multi processor support. Fixed frequency at 14.31818 MHz. (2.5 or 3.3 supply = VDDI) PCI bus clocks. See frequency select table on page 1. PCI clock that ceases only when PD (pin 29) is ascerted. See frequency select table on page 1. Ground pins for the device. 3.3 or 2.5 Volt power supply pins for IOAPIC clock output buffers. 3.3 Volt power supply pins for PCI and PCI_F clock output buffers. 3.3 Volt power supply pins for 48 MHz clock output buffers. 3.3 Volt power supply pins for reference clock output buffers. 3.3 or 2.5 Volt power supply pins for CPU clock output buffers. Power supply pins for analog circuits and core logic Buffered outputs of on-chip reference oscillator. Fixed 48 MHz frequency clock outputs. When driven to a logic low level, this pin will synchronously stop all PCI clocks (except PCI_F) at a logic low level. When driven to a logic low level, this pin will synchronously stop all CPU clocks at a logic low level. When driven to a logic low level this pin enables EMI reducing Spread Spectrum mode (affects only CPU and PCI clocks). When this pin is driven to a logic low the IC will enter shutdown mode and ALL internal circuitry is turned off. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 2 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product Outputs Descriptions CPU PCI, PCIF 48 MHz REF1:3 Tri-State Hi-Z Hi-Z Hi-Z Hi-Z Test Mode TCLK/2 TCLK/4 TCLK/2 TCLK NOTE: TCLK is a test clock that is driven into the XTAL_IN input during test mode. IOAPIC Hi-Z TCLK POWER MANAGEMENT FUNCTIONS All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PSTOP and CSTOP input pins. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, (after bring PD from a low to high state) the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. CSTOP PSTOP PD CPUCLK PCICLK OTHER CLKs XTAL & VCOs X X 0 LOW LOW LOW OFF 0 0 0 1 1 1 LOW LOW LOW RUNNING RUNNING RUNNING RUNNING RUNNING 1 1 0 1 1 1 RUNNING RUNNING LOW RUNNING RUNNING RUNNING RUNNING RUNNING POWER MANAGEMENT TIMING PCICLK_F PSTOP PCICLK(0:5) CSTOP CPUCLK(0:3) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 3 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product Power Management Timing Latency Signal Signal State CSTOP 0 (disabled) 1 (enabled) PSTOP 0 (disabled) 1 (enabled) 1 (normal operation) PD No. of rising edges of free running PCICLK (PCIF) 1 1 1 1 3 mS 0 (power down) 2 mS max. NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high) to when the first valid clocks are driven from the device. SPECTRUM SPREAD CLOCKING Down Spread Amplitude (dB) Without Spectrum Spread With Spectrum Spread Center Frequency(MHz) Spectrum Analysis INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 4 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product SPECTRUM SPREADING SELECTION TABLE Min (MHz) Center (MHz) Max (MHz) CPU Frequency % OF FREQUENCY SPREADING MODE 99.50 65.4 99.75 66.4 99.7 67.39 100 66 .5% (-.5% + 0%) 1.25% (-1.25% + 0%) Down Spread Down Spread MAXIMUM RATINGS Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). -0.3V 0.3V 0ºC to + 125ºC 0ºC to +70ºC 7V ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Input Low Voltage VIL - - 0.8 Vdc - Input High Voltage Input Low Current VIH IIL 2.0 -66 - - Vdc µA - Input High Current Output Low Voltage IOL = 4mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current Static Supply Current IIH VOL - - 5 0.4 µA Vdc VOH 2.4 - - Vdc Ioz Idd Isdd - - 10 175 75 µA mA mA Cx - 18 - pF ISC 25 - - mA Crystal Oscillator Capacitance Short Circuit Current Typ Max Units Conditions All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) CPU = 66.6 MHz, PCI = 33.3 MHz Xin and Xout crystal load capacitance values (each) 1 output at a time - 30 seconds VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 5 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product SWITCHING CHARACTERISTICS Characteristic Symbol Min Typ Max Units tOFF 45 1.5 50 - 55 4 % ns tSKEW1 - - 175 ps Measured at 1.5V CPU load = 20 pF, PCI load = 30 pF measured at 1.5V PCI and 1.25V CPU 20 pF Load Measured at 1.5V tSKEW2 - - 250 ps 30 pF Load Measured at 1.5V ∆Period Adjacent Cycles ∆P - - +250 ps - Jitter Spectrum 20 dB Bandwidth from Center BWJ 500 KHz Output Duty Cycle CPU to PCI Offset Buffer out Skew All CPU Buffer Outputs Buffer out Skew All PCI Buffer Outputs Conditions VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI = 2.5V ±5%, TA = 0ºC to +70ºC BUFFER 1 CHARACTERISTICS FOR CPUCLK(1:4) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min/Max Between 0.4 V and 2.0 V Symbol Min IOHmin IOHmax IOLmin IOLmax TRF -27 27 0.4 Typ - Max -27 30 1.6 Units Conditions mA mA mA mA ns Vout = 1.0 V Vout = 2.375 V Vout = 1.2 V Vout = 0.3 V 20 pF Load VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 6 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product BUFFER 2 CHARACTERISTICS FOR IOAPIC (1:2) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min/Max Between 0.4 V and 2.0 V Symbol Min IOHmin IOHmax IOLmin IOLmax TRFmax -36 36 0.4 Typ - Max -21 31 1.6 Units Conditions mA mA mA mA nS Vout = 1.4 V Vout = 2.5 V Vout = 1.0 V Vout = 0.2 V 20 pF Load VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC BUFFER 3 CHARACTERISTICS FOR REF(1:3) and 48(1:2) MHz Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min Pull-Up Current Max IOHmin IOHmax -29 - - -23 mA mA Vout = 1.0 V Vout = 3.135 V Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min/Max Between 0.4 V and 2.4 V IOLmin IOLmax TRF 29 0.5 - 27 2.0 mA mA ns Vout = 1.95 V Vout = 0.4 V 20 pF Load VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC BUFFER 4 CHARACTERISTICS FOR PCICLK(1:8,F) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise/Fall Time Min/Max Between 0.4 V and 2.4 V Symbol Min IOHmin IOHmax IOLmin IOLmax TRF -33 30 0.5 Typ - Max -33 38 2.0 Units Conditions mA mA mA mA ns Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 30 pF Load VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 7 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product CRYSTAL AND REFERENCE OSCILLATOR PARAMETERS Characteristic Symbol Min Typ Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerence TC - - +/-100 PPM Calibration note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1 TA - - 5 PPM Aging (first year @ 25C) note 1 Mode OM - - - Pin Capacitance CP DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resonant resistance R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW Shunt Capacitance CO - -- 7 pF X1 and X2 Load CL 5 17 Conditions Parallell Resonant pF pF Capacitance of XIN and Xout pins note 1 note 1 internal crystal loading gapacitors on each pin (to ground) For maximum accuracy,the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore the total parasitic capacitance would therefore be 2.0 pF 18.0 pF = 20.0 pF.(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 8 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product PCB LAYOUT SUGGESTION Via to VDD Plane Via to GND Plane Void (cut) in power plane C10 FB1 VCC C1 22uF C2 C3 C4 C5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 C9 FB2 C8 VCC (CPU) C11 22uF C7 C6 This is only a layout recommendation for best performance and lower EMI. the designer may choose a different approach but C2, C3, C4, C5, C6, C7, C8, C9, and C10 (all are 0.1 uf) should always be used and placed as close to their VDD pins as is physically possible. The topological hookup of C4 with respect to its power and ground vias is especially important. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 9 of 10 SG577C Low EMI Clock Generator for Pentium II Systems with Power Management Approved Product PACKAGE DRAWING AND DIMENSIONS 48 PIN SSOP OUTLINE DIMENSIONS INCHES SYMBOL C L H E D a A2 A A1 B e MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.088 0.090 0.092 2.24 2.29 2.34 B 0.008 0.010 0.0135 0.203 0.254 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.620 0.625 0.630 15.75 15.88 16.00 E 0.292 0.296 0.299 7.42 7.52 7.59 e 0.025 BSC 0.635 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0º 5º 8º 0º 5º 8º X 0.085 0.093 0.100 2.16 2.36 2.54 ORDERING INFORMATION Part Number Package Type Production Flow IMISG577CYB 48 PIN SSOP Commercial, 0ºC to +70ºC Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI SG577CYB Date Code, Lot # IMISG577CYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev 1.8 2/19/98 Page 10 of 10