SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product FREQUENCY TABLE PRODUCT FEATURES ® Supports clock requirements for Mobile Pentium Processor 2 Host and 5 PCI clocks Separate supply pins for mixed (3.3/2.5V) voltage application. <175ps skew among CPU clocks. < 250ps skew among PCI clocks. 48mhz for USB. 28-pin SSOP package for minimum board space. Power management capabilities SEL100/66# CPU PCI 0 66.4 Mhz* 33.3 Mhz 1 99.8 Mhz** 33.2 MHz *Down Spread 1.25% (total); **Down Spread .5% (total) BLOCK DIAGRAM VDDR XIN REF OSC XOUT CPU_STOP# PLL VDDC CPUCLK (0:1) PCI_STOP# VDDP SEL1066# PCI (1:5) PWR_DWN# PCI_F PLL 48 MHz INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 CONNECTION DIAGRAM XIN XOUT VSS PCI_F PCI1 VDDP PCI2 PCI3 VDDP PCI4 PCI5 VSS VDD VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 Rev. 1.0 VSS VDDR REF VDDC CPU0 CPU1 VSS VDD VSS PCI_STOP# CPU_STOP# PWR_DWN# 48M SEL100/66# 4/12/1999 Page 1 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product PIN DESCRIPTION PIN No. 1 Pin Name XIN PWR VDD I/O I TYPE OSC1 2 XOUT VDD O OSC1 15 SEL100/66# - I 23, 24 CPUCLK (0:1) PCI_F VDDC O PADI4 PU BUF1 VDDP O BUF4 4 Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On-chip reference oscillator output pin. Drives an external parallel resonant crystal. When an externally generated reference signal is used at Xin, this pin is left unconnected Frequency select input pins. See frequency select table on page 1.This pin has internal pull-up. Clock outputs. CPU frequency table specified on page 1. 16 5, 7, 8, 10, 11 26 19 48M PCI(1:5) VDD48 VDDP O O BUF3 BUF4 Free running PCI clock. When PCI_STP# = 0, this clock does NOT stop. 48 MHz fixed clock. PCI bus clocks. See frequency select table on page 1. REF PCI_STOP# VDDR - O I 18 CPU_STOP# - I 17 PWR_DWN# - I 13, 21 3, 12, 14, 20, 22, 28 9, 6 VDD VSS - P P BUF3 PAD PU PAD PU PAD PU - Buffered outputs of on-chip reference oscillator. When driven to a logic low level, this pin will synchronously stop all PCI clocks (except PCI_F) at a logic low level. When driven to a logic low level, this pin will synchronously stop all CPU clocks at a logic low level. This pin is active low. When asserted low, the device is in shutdown mode. VCO’s, Crystal, and outputs are turned off. 3.3 volt power supply for core logic. Ground pins for the device. VDDP - P - 25 27 VDDC VDDR - P P - 3.3 Volt power supply pins for PCI (1:5) and PCI_F clock output buffers. 3.3 or 2.5 Volt power supply for CPUCLK (0:1) outputs. 3.3 Volt power supply pins for reference clock output buffers and crystal circuit. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 2 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product POWER MANAGEMENT FUNCTIONS All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PCI_STOP# and CPU_STOP# input pins. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within 0.2 mS. The CPU and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. PWR_DWN# 1 1 1 1 0 CPU_STOP# 0 0 1 1 x (don’t care) PCI_STOP# 0 1 0 1 x (don’tcare) CPUCLK LOW LOW RUNNING RUNNING LOW PCICLK LOW RUNNING LOW RUNNING LOW OTHER CLKs RUNNING RUNNING RUNNING RUNNING LOW XTAL & VCOs RUNNING RUNNING RUNNING RUNNING OFF POWER MANAGEMENT TIMING PCI_F PCI_STOP# PCICLK(1:5) CPU_STOP# CPUCLK(0:1) POWER MANAGEMENT TIMING Signal Signal State Latency No. of rising edges of free running PCICLK (PCIF) CPU_ST0P# 0 (disabled) 1 1 (enabled) 1 PCI_ST0P# 0 (disabled) 1 1 (enabled) 1 NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the first valid clock comes out of the device. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 3 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product SPECTRUM SPREAD CLOCKING Down Spread Amplitude (dB) Without Spectrum Spread With Spectrum Spread Frequency (MHz) Center Spectrum Analysis MAXIMUM RATINGS Voltage Relative to VSS: -0.3V Voltage Relative to VDD: 0.3V Storage Temperature: Operating Temperature: Maximum Power Supply: -65ºC to + 150ºC -40ºC to +85ºC 7V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 4 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product ELECTRICAL CHARACTERISTICS Characteristic Symbol Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage IOL = 4mA Output High Voltage IOH = 4mA Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Min Typ VIL VIH IIL IIH VOL 2.0 - - VOH Max Units - 0.8 -66 5 0.4 Vdc Vdc µA µA Vdc 2.4 - - Vdc Ioz Idd Isdd - - 10 140 70 µA mA ISC 25 - - Conditions µA mA - All Outputs (see buffer spec) All Outputs Using 3.3V Power (see buffer spec) CPU = 66.6 MHz, PCI = 33.3 MHz pwr_dwn# (PIN17) = 0 1 output at a time - 30 seconds VDD = VDDP=VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC SWITCHING CHARACTERISTICS Characteristic Symbol Min Typ Max Units Conditions Output Duty Cycle - 45 50 55 % Measured at 1.5V CPU to PCI Offset tOFF 1 3 4 ns 15 pf Load Measured at 1.5V tSKEW - - 250 ps 15 pf Load Measured at 1.5V ∆Period Adjacent Cycles ∆P - - +250 ps - Jitter Spectrum 20 dB Bandwidth from Center BW J 500 KHz Buffer out Skew All CPU and PCI Buffer Outputs VDD = VDDP =VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 5 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product BUFFER 1 CHARACTERISTICS FOR CPUCLK(0:1) Characteristic Symbol Min Typ Max Units Pull-Up Current Min IOHmin -27 Pull-Up Current Max IOHmax - Pull-Down Current Min IOLmin Pull-Down Current Max Conditions - - mA Vout = 1.0 V - -27 mA Vout = 2.6 V 27 - - mA Vout = 1.2 V IOLmax - - 27 mA Vout = 0.3 V Dynamic Output Impedance Zo 10 - 15 Ohms 66 and 100 MHz Rise Time Between 0.4 V and 2.0 V TR 0.4 - 1.6 nS 20 pF Load Fall Time Between 0.4 V and 2.0 V TF 0.5 - 1.6 nS 20 pF Load VDD = VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC BUFFER 3 CHARACTERISTICS FOR REF, 48M Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -29 - - mA Vout = 1.0 V Pull-Up Current Max IOHmax - - -23 mA Vout = 3.135 V Pull-Down Current Min IOLmin 29 - - mA Vout = 1.95 V Pull-Down Current Max IOLmax - - 27 mA Vout = 0.4 V Dynamic Output Impedance Zo 18 - 25 Ohms 66 and 100 MHz Rise Time Between 0.4 V and 2.4 V TR 0.5 - 2.0 nS 20 pF Load Fall Time Between 0.4 V and 2.4 V TF 0.5 - 2.0 nS 20 pF Load VDD = VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 6 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product BUFFER 4 CHARACTERISTICS FOR PCI_F, PCI(1:5) Characteristic Symbol Min Typ Max Units Pull-Up Current Min IOHmin -33 Pull-Up Current Max IOHmax - Pull-Down Current Min IOLmin Pull-Down Current Max Dynamic Output Impedance Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Conditions - - mA Vout = 1.0 V - -33 mA Vout = 3.135 V 30 - - mA Vout = 1.95 V IOLmax Zo TR 14 0.5 - 38 20 2.0 mA Ohms nS Vout = 0.4 V 66 and 100 MHz 30 pF Load TF 0.5 - 2.0 nS 30 pF Load VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC CRYSTAL AND REFERENCE OSCILLATOR PARAMETERS Characteristic Symbol Min Typ Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1 TA - - 5 PPM Aging (first year @ 25C) note 1 Mode OM - - - Pin Capacitance CP DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resonant resistance R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW Shunt Capacitance CO - -- 7 pF X1 and X2 Load CL 5 Calibration note 1 Parallel Resonant pF 17 Conditions Capacitance of XIN and Xout pins note 1 note 1 internal crystal loading capacitors on each pin (to ground) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 pF Rev. 1.0 4/12/1999 Page 7 of 8 SG559 Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power Management Support Approved Product PACKAGE DRAWING AND DIMENSIONS 28 PIN SSOP OUTLINE DIMENSIONS C L SYMBOL H E INCHES D a A2 A MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.068 0.073 0.078 1.73 1.86 1.99 A1 0.002 0.005 0.008 0.05 0.13 0.21 A2 0.066 0.068 0.070 1.68 1.73 1.78 B 0.010 0.012 0.015 0.25 0.30 0.38 C 0.005 0.006 0.009 0.13 0.15 0.22 D 0.397 0.402 0.407 10.07 10.20 10.33 E 0.205 0.209 0.212 5.20 5.30 5.38 A1 B e e 0.0256 BSC 0.65 BSC H 0.301` 0.307 0.311 7.65 7.80 7.90 a 0° 4° 8° 0° 4° 8° L 0.022 0.030 0.037 0.55 0.75 0.95 ORDERING INFORMATION Part Number Package Type IMISG559AYB 28 PIN SSOP Note: Production Flow Commercial, -40ºC to +85ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI SG559AYB Date Code, Lot # IMISG559AYB Flow B = Commercial, -40ºC to + 85ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/12/1999 Page 8 of 8