C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Frequency Table Product Features • • • • • • • • • • • • • • • Supports Intel Pentium II CPU designs. 133 and 100 Mhz CPU clock support Designed to meet Intel chipset specification 3 CPU clocks with isolated power supply 1 CPU/2 clock with isolated power supply 10 PCI clocks with isolated power supply 1 IOAPIC clocks with isolated power supply One 48 Mhz fixed clock for USB/Super IO with isolated power supply 3 3V66 clocks with isolated power supply 2 reference clocks with isolated power supply <175 pS Max. skew among CPU clocks <500 pS Max. skew among PCI clocks Power management control of CPU and PCI clocks 48-pin SSOP package Spread Spectrum EMI reduction mode XOUT 33.3* 1 133* *See complete table on page 3. 33.3* Pin Configuration C9805 48 VSS 47 VDDI VDDR 3 46 IOAPIC XIN 4 45 VSS XOUT 5 44 VDDC/2 VSSP 6 43 CPU/2 PCI0 7 42 VSS PCI1 8 41 VDDC VDDP 9 40 CPU2 PCI2 10 39 VSS PCI3 11 38 VDDC PCI4 12 37 CPU1 PCI5 13 36 CPU0 CPU[0:2] VDDC/2 VSS 14 35 VSS PCI6 15 34 VDD3 CPU/2 PCI7 16 33 VSS VDDP 17 32 PD# PCI8 18 31 SS# PCI9 19 30 SEL1 VSS 20 29 SEL0 3V66_0 21 28 VDD48 3V66_1 22 27 48M 3V66_2 23 26 VSS VDD66 24 25 SEL133/100# REF[0:1] VDDI /2 VDDP PD# PCI [0:9] VDDA 3V66 [0:2] VDDF PLL2 100* 2 VDDC PLL1 0 1 IOAPIC SEL[0:1] SEL133/100# PCI REF1 VDDF REF OSC CPU REF0 Block Diagram XIN SEL133/100# 48M INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 1 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Pin Description PIN No. 4 Pin Name Xin PWR I/O TYPE Description VDD I OSC1 5 Xout VDD O OSC1 36, 37, 40 43 7, 8, 10, 11, 12, 13, 15, 1618, 19 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 9, 17 CPU(0:2) VDDC 0 BUF1 On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On-chip reference oscillator output pin. Drives an external parallel resonant crystal when an externally generated reference signal is used, is left unconnected Clock outputs. CPU frequency table specified on page 1. CPU/2 PCI (0:9) VDDC VDDP O O BUF4 BUF4 CPU Synchronous clock. Its frequency is half CPU clocks. PCI bus clocks. See frequency select table on page 1. VSS - P - Ground pins for the device. VDDP - P - 28 47 38, 41 34 24 21, 22, 23 1, 2 27 25 VDD48 VDDI VDDC VDD VDD66 3V66 (0:2) - P P P - VDDA P O BUF VDDR VDDF - O O I BUF# BUF3 PAD 3.3 Volt power supply pins for PCI and PCI_F clock output buffers. 3.3 Volt power supply pins for 48 MHz clock output buffers. 2.5 Volt power supply pins for IOAPIC clock buffers. 3.3 or 2.5 Volt power supply pins for CPU clock output buffers. Power supply pins for analog circuits and core logic. 3.3 Volt power supply pins for 3V66 clock output buffers. Fixed 66.6 Mhz Advanced Graphics Processor Clock. This clock is rising edgy synchronous with the CPU clock. Buffered outputs of on-chip reference oscillator. Fixed 48 MHz frequency clock output. CPU frequency select pin. By design this input does not contain any internal pullup or pulldown resistor. Device power down signal. Removes power from all internal logic when at a logic low level. See page 4. 3.3 Volt power supply pins for REF clock output buffers. Function selector pins. See description on page 3. 32 3 29, 30 REF (0:1) 48M SEL133/ 100# PD# VDDR SEL (0:1) PU - I 31 SS# - I 46 IOAPIC VDDI 0 PU PAD PU PAD PU PAD When driven to a logic low level, this pin enables EMI reducing Spread Spectrum mode (affects only CPU and PCI clocks). 2.5013.3 volt copy of a 16.67 Mhz clock that is synchronized with the CPU clock. See note on page 3 INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 2 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product SEL 133/100# SEL1 SEL0 CPU CPU/2 3V66 PCI 48M REF 0 0 0 High-Z High-Z High-Z High-Z High-Z High-Z High-Z 0 0 1 105 52.5 66.6 MHz 33.3 MHz 48 MHz 14.5 MHz 16.67 MHz 0 1 0 100 MHz* 50 MHz* 66.6 MHz* 33.3 MHz* OFF 14.3 MHz 16.67MHz* 0 1 1 100 MHz* 50 MHz* 66.6 MHz* 33.3 MHz* 48 MHz 14.3 MH 16.67MHz* 1 0 0 REF/2 REF/4 REF/4 REF/8 REF/2 REF REF/16 1 0 1 139.7 MHz 69.8 MHz 66.6 MHz 33.3 MHz 48 MHz 14.3 MHz 16.67 MHz 1 1 0 133 MHz 66.6 MHz 66.6 MHz 33.3 MHz OFF 14.3 MH 16.67MHz 1 1 1 133 MHz 66.6 Mhz 66.6 MHz 33.3 MHz 48 MHz 14.3 MHz 16.67MHz IOAPIC IOAPIC Clock Synchronization This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU clock and represent a devided by 8 (133 MHz CPU clock mode) or divided by 6 (100 MHz CPU clock mode) clock. the IOAPIC clock lags the CPU clock by the specified 1.5 to 4.0 nSEC. Power Management Functions All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PSTOP and CSTOP input pins. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running when the chip was not powered down. On power up, (after bring PD from a low to high state) the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, and PCI clocks transition between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled or disabled. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 3 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Power Management Functions (Cont.) PD# CPU CPU/2 3V66 PCI PCIF REF XTAL & VCOs 0 LOW LOW LOW LOW LOW LOW OFF ON ON ON ON ON 1 ON ON CPU, 3V66, and CPU/2 Clock Phase Alignment CPU (0:3) 3V66(0:3) CPU/2 (0,1) Power Management Timing PCICLK_F PS# PCICLK(1:7) CS# CPUCLK(0:3) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 4 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Power Management Timing Signal Signal State Latency No. of rising edges of free running PCICLK (PCIF) PD# 1 (normal operation) 3 mS 0 (power down) 2 mS max. NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/high to the first valid clock comes out of the device. 2. Power up latency is when PD# goes inactive (high) to when the first valid clocks are driven from the device. Power Management Timing PD# CPU, PCI, 3V66, PCI_F, CPU/2, Ref, IOAPIC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 5 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Spectrum Spread Clocking Spectrum Analysis Spectrum Spreading Selection Table Min (MHz) Center (MHz) Max (MHz) CPU Frequency % OF FREQUENCY SPREADING MODE 99.5 99.75 100 100 0.5% -0.5%% + 0%) Down Spread 126.4 129.7 133 133.3 0.5% (-0.5% + 0%) Down Spread Maximum Ratings Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD -0.3V 0.3V -65ºC to + 150ºC 0ºC to +70ºC Maximum Power Supply: 5V DC Parameters Characteristic Symbol Input Low Voltage VIL2 Input High Voltage Min Typ Max - - 0.8 Vdc SDATA, SCLK - VIH2 2.0 Input Low Current (@VIL = VSS) IIL -66 Input High Current (@VIL = VDD) IIH Tri-State leakage Current Ioz - Dynamic Supply Current Idd3.3V Isdd Static Supply Current Units Conditions - Vdc SDATA, SCLK -5 µA Pull up 5 µA Pull up - 10 µA - - 175 mA Note 1 - - 2.5 mA PD# Pin at Logic Low VDD = VDDS = 3.3V ±5%, VDDC = 2.5 + 5%, TA = 0ºC to +70ºC Note1: CPU frequency = 133 MHz, all outputs loaded to datasheet maximum capacitive loading values and Vdd = 3.465V. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 6 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product AC Parameters Characteristic Symbol Min Typ Max Units Conditions 50 55 % Measured at 1.5V for 3.3 Volt VDD clocks and 1.25V for 2.5V VDD clocks Output Duty Cycle - 45 CPU to CPU Skew tSKEW cc 0 - 175 pS CPU load = 20 pF, measured at 1.25V CPU/2 to CPU/2 Skew tSKEW cc2 0 - 175 pS CPU/2 load 20 pF,measured at 1.25V IOAPIC to IOAPIC Skew tSKEW II 0 - 250 pS IOAPIC load = 20 pF, measured at 1.25V 3V66 to 3V66 Skew tSKEW AA 0 - 250 pS 3V66 load = 30 pF, measured at 1.5V PCI to PCI Skew tSKEW PP 0 - 500 pS PCI load = 30 pF measured at 1.5V SKEW PERFORMANCE CLOCK OFFSETS CPU to 3V66 Offset tOFFCA 0 - 1.5 nS CPU load = 20 pF, 3V66 load = 30 pF measured at 1.25V, 3V66 = 1.5V (CPU leads) 3V66 to PCI Offset tOFFCP 1.5 - 4.0 nS 3V66 load = 20 pF, PCI load = 30 pF measured at 1.5V tOFFCL 1.5 - 4.0 nS CPU load = 20 pF, IOAPIC load = 20 pF measured at 1.25V (CPU leads) CPU to PCI CPU to IOAPIC Offset 1.5 5.5 JITTER PERFORMANCE ∆Period Adjacent Cycles CPU, CPU/2 and IOAPIC ∆P - - +250 pS ∆Period Adjacent Cycles 48M, 3V66, PCI and REF ∆P - - + 500 pS VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI = 2.5V ±5%, TA = 0ºC to +70ºC Buffer Characteristics for CPU(0:3), IOAPIC (0:2), and CPU/2 (0,1) Characteristic Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -27 - - mA Vout = 1.0 V Pull-Up Current Max IOHmax - - -27 mA Vout = 2.375 V Pull-Down Current Min IOLmin 27 - - mA Vout = 1.2 V Pull-Down Current Max IOLmax - - 27 mA Vout = 0.3 V Rise Time Min Between 0.4 V and 2.0 V TRmin 0.4 - - ns 20 pF Load Fall Time Max Between 0.4 V and 2.0 V TRFmax - 1.6 ns 20 pF Load Dynamic Output Impedance ZO - Ohms VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 7 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Buffer Characteristics for REF(1:3) and 48(1:2) MHz Characteristic Symbol Min Typ Max Units Pull-Up Current Min IOHmin -29 - - mA Vout = 1.0 V Pull-Up Current Max IOHmax - - -23 mA Vout = 3.135 V Pull-Down Current Min IOLmin 29 - - mA Vout = 1.95 V Pull-Down Current Max IOLmax - - 27 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.4 V TRmin 0.5 - 2.0 ns 20 pF Load Fall Time Max Between 0.4 V and 2.4 V TFmax 0.5 - 2.0 ns 20 pF Load Dynamic Output Impedance ZO - Conditions Ohms VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC Buffer Characteristics for PCICLK(0:7), 3V66 (0,7) Characteristic Symbol Min Typ Max Units Pull-Up Current Min IOHmin -33 - - mA Vout = 1.0 V Pull-Up Current Max IOHmax - - -33 mA Vout = 3.135 V Pull-Down Current Min IOLmin 30 - - mA Vout = 1.95 V Pull-Down Current Max IOLmax - - 38 mA Vout = 0.4 V Rise Time Min Between 0.4 V and 2.4 V TRmin 0.5 - - ns 30 pF Load Fall Time Max Between 0.4 V and 2.4 V TFmax 0.5 - 2.0 ns 30 pF Load Dynamic Output Impedance ZO - Conditions Ohms VDD = VDDP=VDDF =VDDR =3.3V ±5%, VDDC, & VDDI =2.5V ±5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 8 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Crystal and Reference Oscillator Parameters Characteristic Symbol Min Typ Max Units Frequency Fo 12.00 14.31818 16.00 MHz Tolerance TC - - +/-100 PPM Calibration Note 1 TS - - +/- 100 PPM Stability (Ta -10 to +60C) note 1 PPM TA - - 5 Mode OM - - - Pin Capacitance CP DC Bias Voltage VBIAS 0.3Vdd Vdd/2 0.7Vdd V Startup time Ts - - 30 µS Load Capacitance CL - 20 - pF Effective Series resonant resistance R1 - - 40 Ohms Power Dissipation DL - - 0.10 mW Shunt Capacitance CO - -- 7 X1 and X2 Load CL 5 17 Conditions Aging (first year @ 25C) note 1 Parallel Resonant pF Capacitance of XIN and Xout pins Note 1 Note 1 pF pF Internal crystal loading capacitors on each pin (to ground) For maximum accuracy,the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore 2.0 pF Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore 18.0 pF the total parasitic capacitance would therefore be = 20.0 pF.(matching CL) Note 1: It is recommended but not mandatory that a crystal meets these specifications. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 9 of 10 C9805 Low EMI Clock Generator for Pentium II CPU Systems with Power Management Approved Product Package Drawing and Dimensions 48 Pin SSOP Outline Dimensions INCHES SYMBOL C L H E MIN NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.088 0.090 0.092 2.24 2.29 2.34 B 0.008 0.010 0.0135 0.203 0.254 0.343 C 0.005 - 0.010 0.127 - 0.254 D .720 .725 .730 18.29 18.42 18.54 E 0.292 0.296 0.299 7.42 7.52 7.59 a D e A2 A A1 B MILLIMETERS e 0.025 BSC 0.406 0.635 BSC H 0.400 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0º 5º 8º 0º 5º 8º X 0.085 0.093 0.100 2.16 2.36 2.54 Ordering Information Part Number Package Type Production Flow C9805CYB 48 PIN SSOP Commercial, 0ºC to +70ºC Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI C9805CYB Date Code, Lot # C9805CYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 http://www.imicorp.com Rev 1.5 9/2/1999 Page 10 of 10