ETC PI6C2404A-1I

PI6C2404A
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Zero-Delay Clock Buffer
Product Features
Functional Description
•
•
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The PI6C2404A is a PLL-based, zero-delay buffer, with the ability
to distribute four outputs of up to 133 MHz at 3.3 V. Two banks of
two outputs exist, OUTA[1–2) and OUTB[1–2].
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•
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Maximum rated frequency: 133 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 200ps
External feedback pin allows outputs to be synchronized
to the clock input
5V tolerant input*
Operates at 3.3V VDD
Test mode allows bypass of the PLL for system testing
purposes (e.g., IBIS measurements)
Space-saving Packages:
8-pin, 150-mil SOIC (W)
An external feedback pin is used to synchronize the outputs to the
input; the relationship between loading of this signal and the other
outputs determines the input-output delay.
The PI6C2404A is characterized for both commercial and industrial
operation.
* FB_IN and CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing
Block Diagram
FB_IN
CLKIN
Pin Configuration
PLL
8
FB_IN
7
VDD
3
6
OUTB2
4
5
OUTB1
OUTA1
CLKIN
1
OUTA2
OUTA1
2
OUTA2
GND
OUTB1
OUTB2
8-Pin
W
Pin Description
Pin
1
Signal
D e s cription
C LK IN
Input clock reference frequency (weak pull- down)
O UTA[1- 2]
C lock output, Bank A
7
VDD
3.3V supply
4
GN D
Ground
O UTB[1- 2]
C lock output, Bank B
FB_IN
PLL feedback input
2, 3
5, 6
8
1
PS8609
04/10/02
PI6C2404A
Zero Delay Clock Buffer
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Zero Delay and Skew Control
CLKIN - Input to OUTA/OUTB Delay (ps)
CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins
800
600
400
200
0
–200
–25
–20
–15
–10
0
–5
5
10
15
20
25
–400
PI6C2404A-1
–600
–800
–900
–1000
Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF)
The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when
all outputs, including feedback, are loaded equally.
Maximum Ratings
Supply Voltage to Ground Potential ............................................................................................................................. –0.5V to +7.0V
DC Input Voltage (Except CLKIN) ........................................................................................................................ –0.5V to VDD +0.5V
DC Input Voltage CLKIN ...................................................................................................................................................... –0.5 to 7V
Storage Temperature ................................................................................................................................................... –65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC
Junction Temperature .................................................................................................................................................................. 150ºC
Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V
Operating Conditions (VCC = 3.3V ±0.3V)
Parame te r
VDD
TA
CL
C IN
De s cription
Supply Voltage
Commerical Operating Temperature
Industrial Operating Temperature
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance
2
M in.
M ax.
Units
3.0
3.6
V
0
70
–40
85
¾
¾
¾
ºC
30
15
pF
7.3
PS8609
04/10/02
PI6C2404A
Zero Delay Clock Buffer
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DC Electrical Characteristics for Industrial Temperature Devices
Parame te r
De s cription
Te s t Conditions
M in.
M ax.
VIL
Input LOW Voltage
0.8
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50
IIH
Input HIGH Current
VIN = VDD
112
VO L
Output LOW Voltage
IO L = 8mA
0.4
VO H
Output HIGH Voltage
IO H = –8mA
IDD
Supply Current
Unloaded outputs 100 MHz, Select inputs at VDD or GND
54
Unloaded outputs 66 MHz, CLKIN
39
Unloaded outputs 33MHz, CLKIN
22
Units
V
2.0
mA
V
2.4
mA
AC Electrical Characteristics for Industrial Temperature Devices
Parame te rs
N ame
FO
O utput Frequency
tDC
Duty Cycle(1)
tR
tF
tS K (O )
Rise Time(1)
Fall Time(1)
O utput to O utput Skew
within same bank(1)
Te s t Conditions
30pF load
M in. Typ. M ax. Units
10 0
10
15pF load
Measured at VDD/2, FO UT <66.67MHz 30pF load
40
Measured at VDD/2, FOUT <50MHz 15pF load
45
13 3
50
60
55
Measured between 0.8V and 2.0V, 30pF load
2. 2
Measured between 0.8V and 2.0V, 15pF load
1. 5
Measured between 0.8V and 2.0V, 30pF load
2. 2
Measured between 0.8V and 2.0V, 15pF load
1. 5
All outputs equally loaded
Delay, CLK IN Rising Edge
to FB_IN Rising Edge(1)
Measured at VDD/2
tS K (D)
Device- to- Device Skew(1)
Measured at VDD/2 on FB_IN pins of devices
Cycle- to- Cycle Jitter(1)
Measured at 66.67 MHz, loaded 30pF load
200
Measured at 133 MHz, loaded 15pF load
110
Stable power supply, valid clocks
presented on CLK IN and FB_IN pins
1. 0
PLL Lock Time(1)
ns
ps
t0
tLO C K
%
200
O UTA to O UTB Skew(1)
tJIT
MHz
0
± 230
0
500
ps
ms
Notes:
1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2.
3
PS8609
04/10/02
PI6C2404A
Zero Delay Clock Buffer
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DC Electrical Characteristics for Commercial Temperature Devices
Parame te r
De s cription
Te s t Conditions
M in.
VIL
Input LOW Voltage
¾
VIH
Input HIGH Voltage
2.0
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
VO L
Output LOW Voltage
IO L = 8mA
VO H
Output HIGH Voltage
IO H = –8mA
IDD
Supply Current
Unloaded outputs 100 MHz Select Inputs @ VDD or GND
IDD
Supply Current
Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND
¾
¾
¾
2.4
¾
¾
M ax.
0.8
¾
50
112
0.4
Units
V
µA
¾
V
39
mA
54
AC Electrial Characteristics for Commercial Temperature Device
Parame te rs
N ame
FO
O utput Frequency
tDC
Duty C ycle(2)
tR
Rise Time(1) @30pF
Rise Time(1) @15pF
tF
Fall Time(1) @30pF
Te s t Conditions
30pF load
M in.
Typ. M ax. Units
10 0
10
15pF load,
13 3
Measured at VDD/2, FO <66.67MHz, 30pF load
40
50
60
Measured at VDD/2, FO <50MHz, 15pF load
45
50
55
tS K (O )
t0
tS K (D)
tJIT
tLO C K
O utput to O utput
within same bank
1. 5
Measured between 0.8V and 2.0V
2. 2
200
O UTA to O UTB Skew(1)
All outputs equally loaded, VDD/2
200
Input to O utput Delay, C LK IN
Rising Edge to FB_IN Rising
Edge(1)
Measured at VDD/2
0
± 200
Device to Device Skew(1)
Measured at VDD/2 on FB_IN pins of devices
0
500
C ycle- to- C ycle Jitter(1)
Measured at 66.67 MHz, loaded 30pF outputs
200
Measured at 133 MHz, loaded 15pF outputs
110
Stable power supply, valid clocks
presented on C LK IN and FB_IN pins
1. 0
PLL Lock
ns
1. 5
All outputs equally loaded, VDD/2
Time(1)
%
2. 2
Fall Time(1) @15pF
Skew(1)
MHz
ps
ms
Notes:
1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2.
2. tDC =
tHIGH
tHIGH + tLOW
4
PS8609
04/10/02
PI6C2404A
Zero Delay Clock Buffer
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Switching Waveforms
tHIGH
Duty Cycle Timing
VDD/2
All Outputs Rise/Fall Time
OUTPUT
tLOW
VDD/2
VDD/2
2.0V
0.8V
tR
2.0V
0.8V
tF
3.3V
0V
Output-Output Skew
OUTPUT
VDD/2
VDD/2
OUTPUT
tSK(O)
Device-Device Skew
FB_IN Device 1
VDD/2
VDD/2
FB_IN Device 2
tSK(D)
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
FB_IN
t0
Test Circuit
0.1µF
VDD
CLK out
OUTPUTS
CLOAD
0.1µF
VDD
GND
GND
Test Circuit for all parameters
5
PS8609
04/10/02
PI6C2404A
Zero Delay Clock Buffer
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8-Pin SOIC (W) Package
8
.149
.157
3.78
3.99
.0099
.0196
1
.189
.196
.016
.026
0.406
0.660
0.25
x 45˚
0.50
.0075
.0098
0-8˚
4.80
5.00
0.19
0.25
0.40 .016
1.27 .050
.053
.068
1.35
1.75
SEATING PLANE
REF
.050
BSC
1.27
.2284
.2440
5.80
6.20
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Ordering Information
Orde ring Code
PI6C2404A- 1W
PI6C2404A- 1WI
Package Name
Package Type
W8
8- pin 150- mil SOIC
Ope rating Range
Commercial
Industrial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
6
PS8609
04/10/02