PI6C9930 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V Zero-Delay Clock Buffer Features Product Description • Near zero input to output delay The PI6C9930 Clock Buffer offers zero-delay, low-skew system clock distribution. These multiple output clock drivers optimize the timing of high-performance computer systems. Each of eight individual drivers can drive series-terminated transmission lines with impedances as low as 50Ω while delivering minimal output skews and full-swing logic levels. • Seven copies of the REF/2 or Six copies of REF plus one REF × 2 • 25 100 MHz output • 50% duty cycle • Low skew • Low jitter (<250ps cycle-to-cycle) • Low noise balanced drive outputs • VCC = 3.3V ±0.3V, TA = 0° to 70° • 24-pin 209 mil wide SSOP (H) • 24-pin 150 mil wide QSOP (Q) • 24-pin 300 mil wide SOIC (S) Applications • PCI 66 MHz or 33 MHz systems Block Diagram Connecting Q0 to FB provides REF/2 outputs on Q1-Q7. Connecting any of Q1 - Q7 output to FB produces six copies of the REF input plus one REF x 2 on Q0. Test Mode In normal system operation, this pin is connected to ground. For testing purposes, the TEST pin can have a removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow drive by an external tester. If the TEST input is forced HIGH, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. Pinout 24-Pin H, Q, S 177 PS8096B 01/25/99 PI6C9930 3.3V Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................ 65°C to +150°C Ambient Temperature with Power Applied ......................... 55°C to +125°C Supply Voltage to Ground Potential ...................................... 0.5V to +7.0V DC Input Voltage ................................................................... 0.5V to +7.0V Output Current into Outputs (LOW) ...................................................... 64mA Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range Range Ambie nt Te mpe rature VCC Commercial 0°C to +70°C 3.3V ± 0.3V Pin Description Pin Name I/O Functional De s cription REF I Reference Frequency Input. This input supplies the frequency and timing against which all functional variation is measured FB I PLL feedback input (typically connected to one of eight outputs) FS I Two- level frequency range select. Internal Pull- up TEST I Two- level select. See Test Mode section. Internal Pull- up QO O Clock Output, no divider Q1 - Q7 O Clock outputs with internal divide by 2 VCCN PWR Power supply for output drivers VCCQ PWR Power supply for internal circuitry GND PWR Ground NC No Connection 178 PS8096B 01/25/99 PI6C9930 3.3V Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Electrical Characteristics Over Operating Range Symbol Parame te rs Te s t Conditions M in. M ax. VOH Output HIGH Voltage VCC = Min., IOH = - 24 mA VOL Output LOW Voltage VCC = Min., IOL = +24 mA VIH Input HIGH Voltage (REF and FB inputs only) 2.0 VCC VIL Input LOW Voltage (REF and FB inputs only) - 0.5 0.8 IIH Input HIGH Leakage Current (REF, Test, FS, and FB inputs only) VCC = Max., VIN = Max. IIL Input LOW Leakage Current (REF, Test, FS, and FB inputs only) VCC = Max., VIN = 0.4V IOS Output Short Circuit Current(2) VCC = Max., VOUT = GND (25°C only) ICCQ Operating Current Used by Internal Circuitry VCCN = VCCQ = Max., All Inputs Select Open 85 ICCN Output Buffer Current per Output Pair(3) VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fmax 14 Power Dissipation per Output Pair(4) VCCN = VCCQ = Max., IOUT = 0 mA Inputs Selects Open, fMAX 78 PD Units 2.4 0.4 10 V mA - 500 - 250 mA mW Notes: 1. If these inputs, which are normally wired to VCC, GND, are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 2. Tested one output at a time, output shorted for less than one second, less than l0% duty cycle. Room temperature only. 3. (TBD) Total output current per output pair is approximated by the following expression that includes device current plus load current. ICCN = [(4 + 0.11F) + [((835 - 3F)/Z) + (.0022FC)]N1] x 1.1 Where: F = frequency in MHz Z = line impedance in ohms C = capacitive load in pF FC = F × C N = number of loaded outputs: 0, l, or 2 4. (TBD) Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: PD = [(22 + 0.61F) + [((1550 - 2.7F)/Z) + (0.125FC)]N] × 1.1 (See note 3 for variable definition) 5. TBD 6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 179 PS8096B 01/25/99 PI6C9930 3.3V Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Capacitance(1,6) (TA = 25°C, f = 1 MHz, VIN = 0V, VOUT = 0V) Parame te r D e s cription Te s t Conditions M ax. Units CIN Input Capacitance TA = 25C, f = 1 MHz, VCC = 3.3V 10 pF AC Test Load and Waveform 3.3V T_cyc R1 CL R2 R1 = 100Ω R2 = 100Ω CL = 20pF (Includes fixture and probe capacitance) 3.3 Volt Clock 0.5Vcc 0.4Vcc 0.3Vcc T_high 0.6Vcc T_low 0.5Vcc 0.3Vcc 0.4Vcc 0.3Vcc 0.2Vcc 0.4Vcc p-to-p (minimum) Clock Waveforms AC Test Load Clock Waveforms AC Timing Diagram 180 PS8096B 01/25/99 PI6C9930 3.3V Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics Over Operating Range(14) (Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 10%) Symbol De s cription M in. Typ. M ax. fNOM FS = LOW Operation Clock Frequency in MHz FS = HIGH or Floating 25 50 50 100 tRPWH REF Pulse Width HIGH 5.0 tRPWL REF Pulse Width LOW 5.0 tSKEW Zero Output Skew (All Outputs)(7,8) 0.3 0.6 Units MHz ns tDEV Device- to- Device Skew(9,10) tPD Propagation delay, REF Rise to FB Rise - 0.5 0.0 +0.5 tCYC Output Duty Cycle, Target Spec @ 66MHz 45 50 55 % sRATE Slew Rate(11,12) 1 1.5 4 V/ns tLOCK PLL Lock Time(13) 0.5 ms Cycle- to- Cycle Output Jitter 325 ps tJR 1.2 Notes: 7. Skew is defined as the time between the earliest and the latest output transition among all outputs with AC Test Load. 8. tSKEW is defined as the skew between outputs. 9. tDEV is the output-to-output skew between any two outputs on separate devices operating under the same conditions (VCC, ambient temperature, air flow, etc.). 10. Tested initially and after any design or process changes that may affect these parameters. 11. Specified with outputs loaded without 20pF in AC Test Load. 12. Slew Rate (sRATE) measured between 0.3VCC and 0.5VCC (0.99V and 1.65V). 13. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 14. Test measurement levels for the PI6C9930 are PCI levels (0.4VCC to 0.4VCC). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. Ordering Information P/N De s cription PI6C9930H 24 pin SSOP Package PI6C9930Q 24 pin QSOP Package PI6C9930S 24 pin SOIC Package Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com 181 PS8096B 01/25/99