DG401/403/405 Vishay Siliconix Low-Power, High-Speed CMOS Analog Switches Wide Dynamic Range Break-Before-Make Switching Action Simple Interfacing 44-V Supply Max Rating 15-V Analog Signal Range On-Resistance—rDS(on): 20 Low Leakage—ID(on): 40 pA Fast Switching—tON: 100 ns Ultra Low Power Requirements—PD: 0.35 W TTL, CMOS Compatible Single Supply Capability Audio and Video Switching Sample-and-Hold Circuits Battery Operation Test Equipment Hi-Rel Systems PBX, PABX Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. On-resistance is very flat over the full 15-V analog range, rivaling JFET performance without the inherent dynamic range limitations. The DG401/403/405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. Combining low power (0.35 W, typ) with high speed (tON: 100 ns, typ), the DG401 series is ideally suited for portable and battery powered industrial and military applications. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. Built on the Vishay Siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup. DG401 DG401 Dual-In-Line and SOIC NC D1 NC NC NC NC NC NC D2 1 16 S1 2 15 IN1 3 14 4 13 5 12 Key 3 D1 2 LCC NC S1 1 20 IN1 19 Two SPST Switches per Package NC 4 18 V– GND NC 5 17 GND Logic Switch VL NC 6 16 NC 0 OFF V+ NC 7 15 VL 1 ON NC 8 14 V+ V– 6 11 7 10 IN2 8 9 S2 9 NC Top View Document Number: 70049 S-52433—Rev. F, 06-Sep-99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 11 D2 NC 12 S2 Logic “0” 0.8 V Logic “1” 2.4 24V 13 IN2 Top View www.siliconix.com FaxBack 408-970-5600 1 DG401/403/405 Vishay Siliconix DG403 DG403 LCC Dual-In-Line and SOIC D1 NC D1 NC 1 16 S1 2 15 D3 3 14 S3 4 13 S4 5 12 D4 6 11 7 10 IN2 8 9 S2 NC NC D2 IN1 Key 1 S1 20 S3 17 GND Logic SW1, SW2 SW3, SW4 NC 6 16 NC 0 OFF ON 7 15 VL 1 ON OFF 8 14 V+ S4 D4 9 10 11 12 2 15 3 14 S3 4 13 S4 5 12 6 11 7 8 D2 S2 IN2 LCC 16 S1 D3 NC 13 DG405 Dual-In-Line and SOIC D4 Logic “0” 0.8 V Logic “1” 1 2.4 V Top View DG405 NC V– 5 NC D2 NC 1 Two SPDT Switches per Package D3 Top View D1 IN1 19 18 VL V+ 2 4 V– GND 3 NC D1 NC Key 3 IN1 2 1 S1 20 IN1 Two DPST Switches per Package 19 V– D3 4 18 V– GND S3 5 17 GND NC 6 16 NC VL V+ S4 10 IN2 D4 9 S2 7 15 VL 8 14 V+ 9 10 11 NC D2 NC Top View www.siliconix.com FaxBack 408-970-5600 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 S2 Logic Switch 0 OFF 1 ON Logic “0” 0.8 V Logic “1” 2.4 V 13 IN2 Top View Document Number: 70049 S-52433—Rev. F, 06-Sep-99 DG401/403/405 Vishay Siliconix Temp Range Package Part Number DG401 –40 to 85_C 16-Pin Plastic DIP 16-Pin CerDIP –55 125_C 55 to 125 C LCC-20 DG401DJ DG401AK DG401AK/883, 5962-9056901MEA DG401AZ/883, 5962-9056901M2A DG403 –40 to 85_C 16-Pin Plastic DIP DG403DJ 16-Pin Narrow SOIC DG403DY 16-Pin CerDIP –55 55 to 125 125_C C LCC-20 DG403AK DG403AK/883, 5962-8976301MEA 5962-8976301M2A DG405 –40 to 85_C –55 to 125_C 16-Pin Plastic DIP DG405DJ 16-Pin Narrow SOIC DG405DY 16-Pin CerDIP LCC-20 DG405AK/883, 5962-8996101EA 5962-89961012A V+ to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND to V– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND – 0.3 V) to (V+) +0.3 V Digital Inputsa VS, VD . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+ plus 2 V) or 30 mA, whichever occurs first Current (Any Terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current, S or D (Pulsed 1 ms 10% duty) . . . . . . . . . . . . . . . . . . . . . . . 100 mA Storage Temperature (AK, AZ Suffix) . . . . . . . . . . . . . . –65 to 150_C (DJ, DY Suffix) . . . . . . . . . . . . . . –65 to 125_C Power Dissipation (Package)b 16-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW 16-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 16-Pin SOICe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW LCC-20f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Document Number: 70049 S-52433—Rev. F, 06-Sep-99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes: a. Signals on SX, DX, or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW/_C above 75_C d. Derate 12 mW/_C above 75_C e. Derate 7.6 mW/_C above 75_C f. Derate 13 mW/_C above 75_C www.siliconix.com S FaxBack 408-970-5600 3 DG401/403/405 Vishay Siliconix Test Conditions Unless Specified Parameter Symbol A Suffix D Suffix –55 to 125_C –40 to 85_C V+ = 15 V, V– = –15 V VL = 5 V, VIN = 2.4 V, 0.8 Vf Tempb Room Full 20 35 45 45 55 Room Full 3 3 5 3 5 Room Hot –0.01 –0.25 –20 0.25 20 –0.5 –5 0.5 5 Room Hot –0.01 –0.25 –20 0.25 20 –0.5 –5 0.5 5 Typc Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee VANALOG Full Drain-Source On-Resistance rDS(on) IS = –10 mA, VD = 10 V V+ = 13.5 V, V– = –13.5 V D Drain-Source On-Resistance DrDS(on) IS = –10 mA, VD = 5 V, 0 V V+ = 16.5 V, V– = –16.5 V Switch Off L k Leakage Current C t Channel On Leakage Current IS(off) ID(off) V+ = 16.5,, V– = –16.5 V VD = 15.5 15 5 V V, VS = 15.5 15 5 V –15 15 –15 15 ID(on) V+ = 16.5 V, V– = –16.5 V VS = VD = 15.5 V Room Hot –0.04 –0.4 –40 0.4 40 –1 –10 1 10 Input Current VIN Low IIL VIN under test = 0.8 V All Other = 2.4 V Full 0.005 –1 1 –1 1 Input Current VIN High IIH VIN under test = 2.4 V All Other = 0.8 V Full 0.005 –1 1 –1 1 V W nA A Digital Control mA Dynamic Characteristics Turn-On Time tON 100 150 150 tOFF RL = 300 W , CL = 35 p pF S See Fi Figure 2 Room Turn-Off Time Room 60 100 100 Break-Before-Make Time Delay (DG403) tD RL = 300 W , CL = 35 pF Room 12 Charge Injection Q CL = 10,000 pF Vgen = 0 V, Rgen = 0 W Room 60 Room 72 Room 90 Room 12 Room 12 CD, CS(on) Room 39 Positive Supply Current I+ Room Full 0.01 Negative Supply Current I– Room Full –0.01 Logic Supply Current IL Room Full 0.01 Room Full –0.01 Off Isolation Reject Ratio OIRR Channel-to-Channel Crosstalk XTALK Source Off Capacitance CS(off) Drain Off Capacitance CD(off) Channel On Capacitance RL = 100 W , CL = 5 pF p f = 1 MHz MH f = 1 MHz, MH VS = 0 V 5 ns 5 pC dB pF F Power Supplies Ground Current V+ V = 16.5 16 5 V, V, V– V = –16.5 16 5 V VIN = 0 or 5 V IGND 1 5 1 5 –1 –5 –1 –5 1 5 1 5 –1 –5 mA A –1 –5 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. www.siliconix.com S FaxBack 408-970-5600 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Document Number: 70049 S-52433—Rev. F, 06-Sep-99 DG401/403/405 Vishay Siliconix _ Input Switching Threshold vs. Logic Supply Voltage Input Switching Threshold vs. Supply Voltages 10 3.5 V+ = 15 V V– = –15 V TA = 25_C 8 3.0 6 V TH (V) V T (V) 2.5 DG403 SW3, 4 4 VL = 7 V 2.0 1.5 VL = 5 V 1.0 2 0.5 0 0 0 2 4 6 8 10 12 14 16 18 20 (V+) 5 10 15 20 25 30 35 40 VL – Logic Supply (V) rDS(on) vs. VD and Temperature rDS(on) vs. VD and Power Supply Voltage 40 V+ = 15 V, V– = –15 V VL = 5 V r DS(on)– Drain-Source On-Resistance ( ) r DS(on)– Drain-Source On-Resistance ( ) 35 30 125_C 25 85_C 20 25_C 0_C 15 –40_C –55_C 30 10 V 12 V 20 15 V 20 V 22 V 10 10 –15 –10 –5 0 5 10 15 –25 –15 –5 5 15 26 VD – Drain Voltage (V) VD – Drain Voltage (V) rDS(on) vs. VD and Power Supply Voltage (V– = 0 V) Charge Injection vs. Analog Voltage 70 200 TA = 25_C V+ = 15 V, V– = –15 V VL = 5 V 180 60 160 7.5 V CL = 10 k pF 140 50 120 Q (pC) r DS(on)– Drain-Source On-Resistance ( ) 6 V TA = 25_C 10 V 40 12 V 1 k pF 100 80 15 V 30 40 22 V 20 100 pF 60 20 V 20 10 0 0 5 10 15 20 VD – Drain Voltage (V) Document Number: 70049 S-52433—Rev. F, 06-Sep-99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 25 –15 –10 –5 0 5 10 15 VS – Source Voltage (V) www.siliconix.com S FaxBack 408-970-5600 5 DG401/403/405 Vishay Siliconix _ Leakage Current vs. Temperature Leakage Current vs. Analog Voltage 90 100 nA V+ = 15 V V– = –15 V VL = 5 V VD = 14 V 10 nA 60 30 I S, I D (pA) I D(off) 1 nA ID(off) 100 pA ID(on) 0 ID(off), IS(off) –30 ID(on) –60 10 pA –90 1 pA V+ = 15 V, V– = –15 V VL = 5 V, TA = 25_C For ID(off), VS = 0 V For IS(off), VD = 0 V –120 –150 0.1 pA –55 –35 –15 5 25 45 65 85 105 125 –15 –10 Temperature (_C) Supply Current vs. Temperature 210 I– t ON , t OFF (ns) L (A) I+, I–, I 1n 100 p VS = 10 V 90 I– 30 65 85 105 V+ = 15 V, V– = –15 V, VL = 5 V tOFF tON 120 60 45 VS = –10 V 0 125 –55 –35 –15 Switching Time vs. Power Supply Voltage* 180 270 0V 240 –5 V 210 –15 V VS = 5 V t ON , t OFF (ns) t ON , t OFF (ns) VS = –5 V 120 VS = 5 V 80 60 65 85 105 125 VS = 5 V 150 –15 V 120 0V –5 V –15 V 0V 60 VL = 5 V tON 20 45 180 90 VS = –5 V 40 25 Switching Time vs. Positive Supply Voltage* 300 100 5 TA – Temperature (_C) 200 140 VS = –10 V VS = 10 V TA – Temperature (_C) 160 15 150 IL 10.0 p 25 10 180 IL 5 5 240 I+ V+ = 15 V, V– = –15 V VL = 5 V 1p –55 –35 –15 0 Switching Time vs. Temperature* 100 n 10 n –5 VD or VS – Drain or Source Voltage (V) tOFF 30 tON tOFF 0 0 0 ”5 ”10 ”15 ”20 V+, V– Positive and Negative Supplies (V) *Refer to Figure 2 for test conditions. www.siliconix.com S FaxBack 408-970-5600 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ”25 0 5 10 15 20 25 V+ – Positive Supply (V) Document Number: 70049 S-52433—Rev. F, 06-Sep-99 DG401/403/405 Vishay Siliconix V+ S VL V– Level Shift/ Drive VIN V+ GND D V– FIGURE 1. VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. tr <20 ns tf <20 ns 3V +5 V Logic Input +15 V VL V+ S 10 V D Switch Input* VO 50% 0V tOFF VS VO 90% IN RL 1 k V– GND CL 35 pF Switch Output Switch Input* –15 V tON 90% VO –VS *VS = 10 V for tON, VS = –10 V for tOFF CL (includes fixture and stray capacitance) RL VO = VS 0V Note: RL + rDS(on) Logic input waveform is inverted for switches that have the opposite logic sense control FIGURE 2. Switching Time +5 V +15 V VL VS1 VS2 Logic Input V+ S1 D1 S2 D2 VO1 90% VO2 IN RL1 V– 50% 0V VS1 VO1 Switch Output GND 3V RL2 CL1 CL2 Switch Output 0V VS2 VO2 0V 90% tD tD –15 V CL (includes fixture and stray capacitance) FIGURE 3. Break-Before-Make Document Number: 70049 S-52433—Rev. F, 06-Sep-99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 www.siliconix.com FaxBack 408-970-5600 7 DG401/403/405 Vishay Siliconix Rg +5 V +15 V VL V+ S DVO D VO IN Vg VO IN CL 10 nF 3V On On Off V– GND Q = DVO x CL –15 V FIGURE 4. Charge Injection +5 V +15 V C C VL V+ S VS D Rg = 50 W C VL V– C VO D Rg = 50 W –15 V RL 100 W IN 0V, 2.4 V Off Isolation = 20 log V+ S VS GND +15 V C RL 100 W IN 0V, 2.4 V +5 V VO GND VS V– C VO C = RF bypass –15 V C = RF bypass FIGURE 5. Off Isolation C +5 V +15 V VL V+ S1 VS FIGURE 6. Insertion Loss C +5 V C Rg = 50 W C 50 W VO +15 V D VL V+ S S2 Meter RL IN IN GND C V– D GND V– –15 V XTALK Isolation = 20 log C = RF bypass HP4192A Impedance Analyzer or Equivalent 0 V, 2.4 V 0.8 V f = 1 MHz C VS VO FIGURE 7. Crosstalk www.siliconix.com FaxBack 408-970-5600 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 –15 V FIGURE 8. Capacitances Document Number: 70049 S-52433—Rev. F, 06-Sep-99 DG401/403/405 Vishay Siliconix Left Source 1 Right Left +5 V +15 V VL V+ S1 D1 S3 D3 Left IN1 D2 S4 D4 Right Integrate/ Reset TTL V+ D1 S3 D3 S2 D2 S4 D4 DG403 GND + – eout C2 IN2 IN2 Channel Select VL S1 C1 S2 TTL +15 V IN1 Source 2 Right ein +5 V V– DG403 Slope Select GND V– –15 V –15 V FIGURE 9. Stereo Source Selector FIGURE 10.Dual Slope Integrator Dual Slope Integrators: The DG403 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor C1 or C2. Another one selects ein or discharges the capacitor in preparation for the next integration cycle. +5 V +15 V VL V+ S1 D1 S3 D3 IN1 Band-Pass Switched Capacitor Filter: Single-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the DG403 allow for higher clock rates and consequently higher filter operating frequencies. ein S2 D2 S4 D4 IN2 DG403 Clock GND V– –15 V + – eout FIGURE 11.Band-Pass Switched Capacitor Filter Document Number: 70049 S-52433—Rev. F, 06-Sep-99 Powered by ICminer.com Electronic-Library Service CopyRight 2003 www.siliconix.com FaxBack 408-970-5600 9 DG401/403/405 Vishay Siliconix Peak Detector: A3 acting as a comparator provides the logic drive for operating SW1. The output of A2 is fed back to A3 and compared to the analog input ein. If ein > eout the output of A3 is high keeping SW1 closed. This allows C1 to charge up to the analog input voltage. When ein goes below eout A3 goes negative, turning SW1 off. The system will therefore store the most positive analog input experienced. Reset SW2 ein – A1 + + A3 – SW1 R1 + A2 – DG401 eout C1 FIGURE 12.Positive Peak Detector www.siliconix.com FaxBack 408-970-5600 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Document Number: 70049 S-52433—Rev. F, 06-Sep-99