EDI8F81024C 1Mx8 Static RAM CMOS, Module FEATURES DESCRIPTION n 1024Kx8 bit CMOS Static The EDI8F81024C is a 8Mb CMOS Static RAM based on eight 128Kx8 Static RAMs mounted on a multi-layered epoxy laminate (FR4) substrate. n Random Access Memory Access Times 70 thru 100ns A version featuring Low Power with Data Retention (EDI8F81024LP) is also available. Data Retention Function (EDI8F81024LP) TTL Compatible Inputs and Outputs The EDI8F81024C is offered in a double sided, 36 pin single-inline Package (SIP). Surface mount SIP technology is a cost effective solution to very high packing density requirements. Fully Static, No Clocks n High Density Packaging All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI8F81024C requires no clocks or refreshing for operation. 36 Pin SIP, No. 62 n Single +5V (±10%) Supply Operation PIN CONFIGURATIONS AND BLOCK DIAGRAM PIN NAMES AØ-A19 Chip Enable W Write Enable G DQØ-DQ7 VCC July 2002 Rev. 8A ECO #15405 1 Address Inputs E Output Enable Common Data Input/Output Power (+5V±10%) VSS Ground NC No Connection White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81024C RECOMMENDED DC OPERATING CONDITIONS A BSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Plastic Power Dissipation Output Current Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage -0.5V to 7.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C 1 Watt 20 mA Sym VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --- Max 5.5 0 6.0 0.8 Units V V V V AC TEST CONDITIONS *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V 1TTL, CL =100pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC ELECTRICAL CHARACTERISTICS Parameter Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) Sym ICC1 ICC2 ICC3 Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage ILI ILO VOH VOL Conditions W, E = VIL, II/O = 0mA, Min Cycle E ³ VIH, VIN £ VIL VIN ³ VIH E ³ VCC-0.2V VIN ³ VCC-0.2V or VIN £ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -1.0mA IOL = 2.1mA C LP Min -- Typ* 80 Max 130 Units mA -- 40 90 mA --- 10 400 20 950 mA µA --2.4 -- ----- ±10 ±10 -0.4 µA µA V V *Typical: TA = 25°C, VCC = 5.0V CAPACITANCE TRUTH TABLE G X H L X E H L L L W X H H L Mode Standby Output Deselect Read Write (f=1.0MHz, VIN=VCC or VSS) Output High Z High Z DOUT DIN Power ICC2, ICC3 ICC1 ICC1 ICC1 Parameter Input Capacitance (Except DQ Pins) Capacitance (DQ Pins) Input (E) Control Lines Input (W) Line (G) Sym Max Unit CI CD/Q CC CW 58 43 10 60 pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 July 2002 Rev. 8A ECO #15405 EDI8F81024C AC CHARACTERISTICS READ CYCLE Symbol Parameter 70ns JEDEC Alt. Min Read Cycle Time TAVAV TRC 70 Address Access Time TAVQV TAA Chip Enable Access Time TELQV TACS Chip Enable to Output in Low Z (1) TELQX TCLZ Chip Disable to Output in High Z (1) TEHQZ TCHZ Output Hold from Address Change TAVQX TOH Output Enable to Output Valid TGLQV TOE Output Enable to Output in Low Z (1) TGLQX TOLZ Output Disable to Output in High Z(1) TGHQZ TOHZ 85ns Max Min 100ns Max 85 70 85 5 30 3 3 0 ns 100 ns ns 40 3 45 0 30 ns 100 5 35 40 Max Units 100 85 70 5 Min 50 0 35 ns ns ns ns 40 ns Note: Parameter guaranteed, but not tested. READ CYCLE 1 - W HIGH, G, E LOW TAVAV A ADDRESS 1 ADDRESS 2 TAVQV TAVQX Q DATA 2 DATA 1 READ CYCLE 2 - W HIGH TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q July 2002 Rev. 8A ECO #15405 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81024C AC CHARACTERISTICS WRITE CYCLE Symbol JEDEC Alt. Parameter 70ns Min Max 85ns Min Max 100ns Min Max Units Write Cycle Time TAVAV TWC 70 85 100 ns Chip Enable to End of Write TELWH TELEH TCW TCW 65 65 70 70 80 80 ns ns Address Setup Time TAVWL TAVEL TAS TAS 0 0 0 0 0 0 ns ns Address Valid to End of Write TAVWH TAVEH TAW TAW 65 65 70 70 80 80 ns ns Write Pulse Width TWLWH TWLEH TWP TWP 65 65 70 70 80 80 ns ns Write Recovery Time TWHAX TEHAX TWR TWR 0 0 0 0 0 0 ns ns Data Hold Time TWHDX TEHDX TDH TDH 0 0 0 0 0 0 ns ns Write to Output in High Z (1) TWLQZ TWHZ 0 Data to Write Time TDVWH TDVEH TDW TDW 30 30 30 35 35 0 35 40 40 0 40 ns ns ns Output Active from End of Write (1) TWHQX TWLZ 5 5 5 ns Note 1: Parameter guaranteed, but not tested. WRITE CYCLE 1 - W CONTROLLED TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TDVWH D DATA VALID TWHQX TWLQZ HIGH Z Q White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com TWHDX 4 July 2002 Rev. 8A ECO #15405 EDI8F81024C WRITE CYCLE 2 - E CONTROLLED TAVAV A TAVEL TELEH E TAVEH TEHAX TWLEH W TDVEH D TEHDX DATA VALID HIGH Z Q Data Retention Characteristics Characteristic Data Retention Voltage Data Retention Quiescent Current Sym Test Conditions VDD VDD ICCDR VDD = 0.2V E ³ VDD -0.2V VIN ³ VDD -0.2V or VIN £ 0.2V 2V 3V Chip Disable to Data Retention Time (1) TCDR Operation Recovery Time (1) TR Min Typ 2 --0 TAVAV* -25 50 --- Max Unit 70°C 85°C --V 300 400 µA 450 550 µA --ns --ns Note 1: Parameter guaranteed, but not tested. * Read Cycle Time DATA RETENTION E CONTROLLED DATA RETENTION MODE 4.5V VCC VDD TCDR E July 2002 Rev. 8A ECO #15405 4.5V TR E≥VDD-0.2V 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F81024C ORDERING INFORMATION Standard Power EDI8F81024C70BSC EDI8F81024C85BSC EDI8F81024C100BSC Low Power with Data Retention EDI8F81024LP70BSC EDI8F81024LP85BSC EDI8F81024LP100BSC Speed (ns) 70 85 100 Package No. 62 62 62 Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, eg. EDI8F81024C70BSC becomes EDI8F81024C70BSI. PACKAGE DESCRIPTION PACKAGE NO. 62: 36 PIN SINGLE-IN-LINE PACKAGE ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 July 2002 Rev. 8A ECO #15405