HM51W4265C Series 262,144-word × 16-bit Dynamic Random Access Memory ADE-203-477B (Z) Rev. 2.0 Jul. 10, 1997 Description The Hitachi HM51W4265C Series is a CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51W4265C Series has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51W4265C Series offers Extended Data Out (EDO) Page Mode as a high speed access mode. It is packaged in standard 44-pin plastic TSOPII. Features • Single 3.3 V supply: 3.3 V ±0.15 V (HM51W4265C-6R) • 3.3 V ±0.3 V (HM51W4265C-6R) • Access time: 60 ns/70 ns/80 ns (max) • Power dissipation Active mode: 576 mW/552 mW/468 mW/396 mW (max) Standby mode: 6.9 mW (max) (HM51W4265C-6R) 7.2 mW (max) (HM51W4265C-6/7/8) 0.69 mW (max)(L-version) (HM51W4265CL-6R) 0.72 mW (max) (L-version) (HM51W4265CL-6/7/8) • EDO page mode capability • Refresh cycles 512 refresh cycles: 8 ms 128 ms (L-version) • 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Self refresh • 2CAS-byte control • Battery backup operation (L-version) Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Ordering Information Type No. Access time Package HM51W4265CTT-6 HM51W4265CTT-6R HM51W4265CTT-7 HM51W4265CTT-8 60 ns 60 ns 70 ns 80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DB) HM51W4265CLTT-6 HM51W4265CLTT-6R HM51W4265CLTT-7 HM51W4265CLTT-8 60 ns 60 ns 70 ns 80 ns 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Pin Arrangement HM51W4265CTT/CLTTSeries VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC WE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name Function A0 to A8 Address input − Row address − Column address − Refresh address I/O0 to I/O15 Data input/output RAS Row address strobe UCAS, LCAS Column address strobe WE Read/write enable OE Output enable VCC Power supply VSS Ground NC No connection A0 to A8 A0 to A8 A0 to A8 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series 128 k memory Array mat 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder 128 k memory Array mat Row decoder I/O bus & column decoder Powered by ICminer.com Electronic-Library Service CopyRight 2003 WE UCAS OE 128 k memory Array mat 128 k memory Array mat 128 k memory Array mat Row decoder Row decoder 128 k memory Array mat Row decoder Selector Row Row decoder decoder Selector Row Row decoder decoder Selector Row Row decoder decoder Selector Selector LCAS RAS 4 I/O buffer 128 k memory Array mat I/O bus & column decoder 128 k memory Array mat I/O bus & column decoder Row Row decoder decoder Selector Selector Selector I/O 8 128 k memory Array mat I/O bus & column decoder 128 k memory Array mat 128 k memory Array mat I/O bus & column decoder 128 k memory Array mat 128 k memory Array mat I/O bus & column decoder Row Row decoder decoder 128 k memory Array mat I/O 7 128 k memory Array mat I/O bus & column decoder 128 k memory Array mat 128 k memory Array mat I/O bus & column decoder Row decoder 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder I/O buffer Selector 128 k memory Array mat I/O 6 128 k memory Array mat I/O bus & column decoder Row Row decoder decoder 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder I/O buffer Selector Row decoder 128 k memory Array mat I/O 5 I/O 9 I/O buffer I/O buffer Selector 128 k memory Array mat Row decoder I/O bus & column decoder I/O 4 I/O 10 I/O buffer I/O buffer Peripheral circuit 128 k memory Array mat I/O buffer I/O buffer I/O 3 I/O 11 Address A0-A8 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder I/O buffer I/O 2 I/O 13 I/O buffer I/O buffer I/O 1 I/O 12 Selector 128 k memory Array mat I/O buffer I/O buffer Selector 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder I/O 15 I/O buffer Selector 128 k memory Array mat I/O 0 I/O 14 Selector 128 k memory Array mat Row Row decoder decoder I/O bus & column decoder I/O buffer Selector 128 k memory array mat Row decoder Block Diagram 128 k memory Array mat HM51W4265C Series Operation Table The HM51W4265C series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS-only refresh cycle 6. CAS-before-RAS refresh cycle 7. Self refresh cycle 8. EDO page mode read cycle 9. EDO page mode early write cycle 10. EDO page mode delayed write cycle 11. EDO page mode read-modify-write cycle Inputs RAS LCAS UCAS WE OE Output Operation H H H D D Open Standby H L L H L Valid Standby L L L H L L L L Valid Read cycle L* 2 D Open Early write cycle 2 H Undefined Delayed write cycle L L L L* L L L H to L L to H Valid Read-modify-write cycle L H H D D Open RAS-only refresh cycle H to L H L D D Open CAS-before-RAS refresh cycle L H L L H to L H to L L L H to L H to L Self refresh cycle H L Valid EDO page mode read cycle L* 2 D Open EDO page mode early write cycle 2 H Undefined EDO page mode delayed write cycle L H to L H to L L* L H to L H to L H to L L to H Valid EDO page mode read-modify-write cycle L L L H H Open Read cycle (Output disabled) Notes: 1. H: High(inactive) L: Low(active) D: H or L (H: VIH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) 2. t WCS ≥ 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write operation and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT −0.5 to +4.6 V Supply voltage relative to VSS VCC −0.5 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg −55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Notes Supply voltage VSS 0 0 0 V 2 VCC (HM51W4265C-6R) 3.15 3.3 3.45 V 1, 2 VCC (HM51W4265C-6/7/8) 3.0 3.3 3.6 V 1, 2 Input high voltage VIH 2.0 VCC + 0.3 V 1 Input low voltage VIL −0.3 0.8 V 1 Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ±0.15 V, VSS = 0 V) (HM51W4265C-6R)*5 (Ta = 0 to +70°C, VCC = 3.3 V ±0.3 V, VSS = 0 V) (HM51W4265C-6/7/8) *5 HM51W4265C -6/6R Parameter -7 -8 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 120 I CC2 2 2 1 1 I CC2 200 I CC3 120 Standby current* I CC5 5 CAS-before-RAS refresh current* 2 I CC6 120 EDO page mode current*1, * 3 I CC4 1, Operating current* * 2 Standby current Standby current (L-version) RAS-only refresh current*2 1 110 95 mA RAS, UCAS, LCAS cycling t RC = min 2 mA TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z 1 mA CMOS interface RAS, UCAS, LCAS WE, OE ≥ V CC − 0.2 V Dout = High-Z 200 200 µA CMOS interface RAS, UCAS, LCAS, WE, OE ≥ V CC − 0.2 V Dout = High-Z 105 92 mA t RC = min 5 mA RAS = VIH, UCAS, LCAS = VIL Dout = enable 105 92 mA t RC = min 160 130 110 mA t HPC = min 200 200 µA Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 µs t RAS ≤ 1 µs, UCAS, LCAS = VIL WE, OE = VIH 1 mA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z 200 µA CMOS interface RAS, UCAS, LCAS ≤ 0.2 V Dout = High-Z 5 Battery backup current* (Standby with CBR refresh) (L-version) I CC10 200 Self-refresh mode current I CC11 1 Self-refresh mode current (L-version) I CC11 200 Input leakage current I LI −10 10 −10 10 −10 10 µA 0 V ≤ Vin ≤ 4.6 V Output leakage current I LO −10 10 −10 10 −10 10 µA 0 V ≤ Vout ≤ 4.6 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = −2 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 2 mA 4 1 200 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series 2. 3. 4. 5. Address can be changed once or less while RAS = VIL. Address can be changed once or less within one EDO page cycle. VIH ≥ V CC − 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL. All the V CC pins should be supplied with the same voltage. And all the VSS pins should be supplied with the same voltage. Capacitance (Ta = +25°C, VCC = 3.3 V ±0.15 V) (HM51W4265C-6R) (Ta = +25°C, VCC = 3.3 V ±0.3 V) (HM51W4265C-6/7/8) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 5 pF 1 Input capacitance (Clocks) CI2 7 pF 1 Output capacitance (Data-in, Data-out) CI/O 10 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. UCAS and LCAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.15 V, VSS = 0 V) (HM51W4265C-6R)*1, *14, *15, *17, *18 (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W4265C-6/7/8)*1, *14, *15, *17, *18 Test Conditions • • • • • Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (50 pF) (Including scope and jig) 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM51W4265C -6/6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 104 124 144 ns RAS precharge time t RP 40 50 60 ns RAS pulse width t RAS 60 10000 70 10000 80 10000 ns 27 CAS pulse width t CAS 10 10000 13 10000 15 10000 ns 28 Row address setup time t ASR 0 0 0 ns Row address hold time t RAH 10 10 10 ns Column address setup time t ASC 0 0 0 ns 19 Column address hold time t CAH 10 13 15 ns 19 RAS to CAS delay time t RCD 20 45 20 50 20 60 ns 8 RAS to column address delay time t RAD 15 30 15 35 15 40 ns 9 RAS hold time t RSH 15 18 20 ns CAS hold time t CSH 48 58 68 ns 29 CAS to RAS precharge time t CRP 10 10 10 ns 20 OE to Din delay time t ODD 15 18 20 ns OE delay time from Din t DZO 0 0 0 ns CAS setup time from Din t DZC 0 0 0 ns Transition time (rise and fall) tT 2 50 2 50 2 50 ns Refresh period t REF 8 8 8 ms Refresh period (L-version) t REF 128 128 128 ms 7 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Read Cycle HM51W4265C -6/6R Parameter Symbol Min Access time from RAS t RAC Access time from CAS -7 -8 Max Min Max Min Max Unit Notes 60 70 80 ns 2, 3 t CAC 15 20 20 ns 3, 4, 13 Access time from address t AA 30 35 40 ns 3, 5, 13 Access time from OE t OAC 15 20 20 ns 3, 23 Read command setup time t RCS 0 0 0 ns 19 Read command hold time to CAS t RCH 0 0 0 ns 16, 20 Read command hold time to RAS t RRH 0 0 0 ns 16 Column address to RAS lead time t RAL 30 35 40 ns Column address to CAS lead time t CAL 18 23 28 ns Output buffer turn-off time t OFF1 15 15 15 ns 6, 25 Output buffer turn-off time to OE t OFF2 15 15 15 ns 6 CAS to Din delay time t CDD 15 18 20 ns RAS to Din delay time t RDD 15 18 20 ns WE to Din delay time t WDD 15 18 20 ns OE pulse width t OEP 15 20 20 ns 23 Turn-off to RAS t OFR 15 15 15 ns 6, 25 Turn-off to WE t WEZ 15 15 15 ns 6 Output data hold time t OH 5 5 5 ns 25 Output data hold time from RAS t OHR 5 5 5 ns 25 Read command hold time from RAS t RCHR 60 70 80 ns Read command hold time from CAS t RCHC 15 18 20 ns Read command hold time from column address 30 35 40 ns t RCHA 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Write Cycle HM51W4265C -6/6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 0 0 ns 10, 19 Write command hold time t WCH 10 13 15 ns 19 Write command pulse width t WP 10 10 10 ns Write command to RAS lead time t RWL 10 13 15 ns Write command to CAS lead time t CWL 10 13 15 ns 21 Data-in setup time t DS 0 0 0 ns 11, 21 Data-in hold time t DH 10 13 15 ns 11, 21 Read-Modify-Write Cycle HM51W4265C -6/6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 133 159 183 ns RAS to WE delay time t RWD 77 90 102 ns 10 CAS to WE delay time t CWD 32 38 42 ns 10 Column address to WE delay time t AWD 47 55 62 ns 10 OE hold time from WE t OEH 15 18 20 ns Refresh Cycle HM51W4265C -6/6R Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes CAS setup time (CBR refresh cycle) t CSR 10 10 10 ns 19 CAS hold time (CBR refresh cycle) t CHR 10 10 10 ns 20 RAS precharge to CAS hold time t RPC 10 10 10 ns 19 CAS precharge time in normal mode t CPN 10 13 15 ns 22 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series EDO Page Mode Cycle HM51W4265C -6/6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 25 30 35 ns 24 EDO page mode CAS precharge time t CP 10 13 15 ns 22 EDO page mode RAS pulse width t RASC 100000 100000 ns 12 Access time from CAS precharge t ACP 35 40 45 ns 3, 13, 20 RAS hold time from CAS precharge t RHCP 35 40 45 ns Output data hold time from CAS low t DOH 3 3 3 ns CAS hold time referred OE t COL 10 13 20 ns CAS to OE setup time t COP 5 5 5 ns Read command hold time from CAS precharge t RCHP 35 40 45 ns 100000 26 EDO Page Mode Read-Modify-Write Cycle HM51W4265C -6/6R Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes EDO page mode read-modify-write t HPCM cycle time 66 77 86 ns EDO page mode read-modify-write t CPW cycle CAS precharge to WE delay time 52 60 67 ns 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10, 20 HM51W4265C Series Self Refresh Mode HM51W4265C -6/6R -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 100 100 µs RAS precharge time (self refresh) t RPS 110 130 150 ns CAS hold time (self refresh) t CHS −50 −50 −50 ns 30, 31, 32, 33 21 Notes: 1. AC measurements assume t T = 2 ns. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 50 pF. (VOH = 2.0 V, VOL = 0.8 V) 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF1 (max), tOFF2 (max), tOFR (max) and tWEZ (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in EDO mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 µs is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 18. All the V CC and VSS pins shall be supplied with the same voltages. 19. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 20. t CRP , t CHR, t ACP, tCPW and tRCH are determined by the later rising edge of UCAS or LCAS. 21. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 22. t CPN and t CP are determined by the time that both UCAS and LCAS are high. 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 24. t HPC (min) can be achieved during a series of EDO page mode early write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle tHPC (tCAS + tCP + 2tT) becomes greater than the specified t HPC (min) value. 25. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH, and between tOFR and t OFF1. 26. t DOH defines the time at which the output level satisfied the output timing reference levels. Measured with the test conditions. 27. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 28. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 29. t CSH (min) can be achieved when tRCD ≤ tCSH (min) − tCAS (min). 30. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP. 31. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 32. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 33. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 34. XXX: H or L (H: VIH (min) ≤ V IN ≤ V IH (max), L: VIL (min) ≤ V IN ≤ V IL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Notes concerning 2CAS control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LCAS are allowed under the following conditions. 1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following. RAS Delayed write UCAS Early write LCAS WE 3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP ≤ tUL) is satisfied, EDO page mode can be performed. RAS UCAS LCAS t UL 4. Byte control operation by remaining UCAS or LCAS high is guaranteed. 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Timing Waveforms*34 Read Cycle t RC t RAS RAS tT t RP t CRP t RSH t CAS t CSH t RCD UCAS LCAS t RAD t ASR Address t RAL t CAH t RAH t ASC Row Column t RCS t RCHA t CAL t RDD t OH t OHR t RCHR t RCHC t RCH t RRH WE t OFR t CAC t AA t OFF1 Dout Dout t RAC t OFF2 t OAC t DZC t WDD t ODD t DZO 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WEZ High-Z Din OE t CDD t OEP HM51W4265C Series Early Write Cycle t RC t RAS RAS t RP tT t RSH t RCD t CAS t CRP t CSH UCAS LCAS t ASR t RAH Address t ASC Row t CAH Column t WCH t WCS WE t DS Din Dout t DH Din High-Z 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT UCAS LCAS t ASR Address t ASC t RAH t CWL t RWL t CAH Row Column t RCS t WP WE t DS t DH High-Z Din Din t DZC t ODD t DZO t OEH Dout Invalid Dout* t OFF2 OE * * Do not enable Dout during delayed write cycle. 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD UCAS LCAS t CRP t RAD t ASR Address t CAS t RAH tCAH t ASC Row Column t CWL t CWD t RCS t RWL t AWD t WP WE t RWD t AA t CAC t DS t RAC t DH t DZC High-Z Din Dout Din Dout t OAC t OFF2 t DZO OE t OEH t ODD t OEP 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC UCAS LCAS t RAH t ASR Address Row Dout 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z tCRP HM51W4265C Series CAS-Before-RAS Refresh Cycle t RC t RP t RC t RAS t RP t RAS t RP RAS tT t RPC t CPN t RPC t CSR t CHR t CPN t CRP t CSR t CHR UCAS LCAS Address t OFF1 Dout High-Z 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series EDO Page Mode Read Cycle (tHPC minimum cycle operation) t RASC t RHCP t RP RAS tT t CSH t RCD t HPC t CAS t CP t CAS t RSH t CP t CRP t CAS UCAS LCAS t ASR t CAL t RAD t RAH Address t CAH tASC Row Column 1 t CAL t CAL t ASC t CAH Column 2 t RAL t CAH t ASC Column 3 t RCHA t RRH t RCHP t RCS t RCH t RCHC WE t WEZ t DZC t CDD High-Z Din t CAC t CAC t RAC t AA t AA t ACP t DOH Dout 1 Dout t CAC t AA t ACP t DOH Dout 2 t OFR t OH t ODD t OHR t OFF1 Dout 3 t OAC t DZO OE 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t OFF2 HM51W4265C Series EDO Page Mode Read Cycle (High-Z control by WE and OE) t RP RAS tT t CSH UCAS LCAS t CP t HPC t CAS t RCS t CP t HPC t CAS tCAS tCAS t RCHP t RCHC t RCHA tASR tRAH t ASC Row tCAH t CAH t ASC Column 2 tCAL tDZC t RRH t RCH t t RAL RCHC t ASC Column 1 t CRP t RHCP t CP t RCH t RCS t RCHR WE Address t HPC t RASC tASC t CAH Column 3 t CAL t WDD t CAH Column 4 t CAL tRDD tCDD t CAL High-Z Din tCOL tDZO tCOP tODD OE tAA tCAC tCAC tAA Dout tOFF2 Dout 1 tACP tAA tCAC tWEZ tRAC tOFR tOHR tOFF2 tACP tACP tOAC tOAC Dout 2 tAA tOFF2 tDOH Dout 2 tCAC tOFF1 tOH tOAC Dout 3 Dout 4 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series EDO Page Mode Early Write Cycle (tHPC minimum cycle operation) t RASC t RP RAS tT t CSH t RCD t RSH t HPC t CAS t CP t CAS t CAS t CP UCAS LCAS t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t ASC t CAH Column t WCS t ASC t CAH Column t WCH t WCH t WCS WE t DS Din Din Dout 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t DH t DS Din High-Z t DH t DS t DH Din t CRP HM51W4265C Series EDO Page Mode Delayed Write Cycle t RASC t RP RAS tT t CSH tRCD t HPC t CAS t CP t CAS t RSH t CAS t CP t CRP UCAS LCAS t ASR t RAH Address t ASC t CAH t ASC t CAH Row t CAH t ASC Column Column Column t CWL t CWL t RCS t CWL t WP t WP t WP t RWL WE t DH t DS Din t RCS t DH t DS t DH t DS Din Din t RCS Din t OEH High-Z Dout t ODD OE 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series EDO Page Mode Read-Modify-Write Cycle t RP t RASC RAS t RCD t HPCM tT t CAS UCAS LCAS t CRP t CP t CP t CAS t CAS t RAD t RAH t ASR Address t ACP t CAH t ASC t ASC Row t ASC Column Column t CWL t AWD t CWD t RCS t CAH t CAH t AWD t CWL t CWD t RCS t WP t RWD Column t CPW t WP t RCS t CPW t CWL t AWD t RWL t CWD t WP WE t CAC t DZC t DZC t DH High-Z Din Din t AA tOAC t OEH Dout t OAC t OEH Dout t OFF2 t DS t DH t DZC High-Z Din t CAC t DZO t RAC t DZO t DH t CAC High-Z Din tAA Dout t ACP t DS t DS t AA t OAC t OEH Dout t OFF2 t DZO t OFF2 OE t ODD t ODD t OEP 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t OEP t ODD tOEP HM51W4265C Series EDO Page Mode Mix Cycle (1)*24 t RP t RASC RAS t CSH tT UCAS LCAS t CAS t WCS t CAS tCAS Address t RCHP t RCHC tCPW tAWD t ASC tRAH Row tCAH Column 1 tCAL t DS Din tCAS t WCH WE tASR t ASC t CAH tASC t CAH Column 2 Column 3 t CAL tWP tASC t RRH t RCH t RCHA t RAL t CAH Column 4 t CAL t DS t DH Din 1 t CRP t CP t CP t CP High-Z t DH tRDD tCDD t CAL Din 3 tODD tWDD OE t ACP tAA tOAC tCAC tDZO t ACP tOFF2 tAA tCAC Dout 2 tAA tOFF2 tCAC tOAC t DOH Dout tOFR tWEZ tACP Dout 3 tOFF1 tOH Dout 4 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series EDO Page Mode Mix Cycle (2)*24 t RP t RASC RAS tT t CSH UCAS LCAS t CAS t RCS t RCHR t CAS Address tCAS t RCH t WCS t WCH tCAS Row tCAH Column 1 t ASC t CAH t ASC t CAH Column 2 Column 3 tCAL t DS High-Z Din Column 4 Din 2 tODD t RRH t RCH t RCHA t RAL t CAH tASC t CAL t DS t CAL t DH t RCHC tWP tCPW t ASC tRAH t RCHP tCWL WE tASR t CRP t CP t CP t CP tRDD tCDD t CAL t DH Din 3 tDZO tODD tWDD tDZO OE tAA tOAC tOFF2 tCAC Dout 1 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 tOFR tWEZ tOFF2 tACP tCAC tRAC Dout t OAC tACP tAA tOFF2 tAA tCAC tOAC Dout 3 tOFF1 tOH Dout 4 HM51W4265C Series Self Refresh Cycle*30, 31, 32, 33 t RASS t RP t RPS RAS tT t RPC t CPN t CRP t CSR t CHS UCAS LCAS Address t OFF1 Dout High-Z 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Package Dimensions HM51W4265CTT/CLTT Series (TTP-44/40DB) Unit: mm Unit: mm 23 10.16 44 18.41 18.81 Max 35 32 10 13 0.80 0.27 ± 0.07 0.25 ± 0.05 22 0.80 0.13 M 11.76 ± 0.20 1.005 Max 0.10 Dimension including the plating thickness Base material dimension 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.13 ± 0.05 2.40 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC Code EIAJ Code Weight (reference value) TTP-44/40DB MO-133BA SC-504-8C 0.43 g 0.68 1 HM51W4265C Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein.1 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 31 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM51W4265C Series Revision Record Rev. Date Contents of Modification 0.0 Dec. 1, 1995 Initial issue T. Oono S. Suzuki M. Tsunozaki S. Suzuki 1.0 Jul. 31, 1996 Addition of HM51W4265C-6 Series AC Characteristics Change of note 25, 34 Addition of note 30 Notes concerning 2CAS control Addition of note 4 Timing waveforms Deletion of notes about undefined pins. Early write cycle. EDO pagemode early write cycle. CAS-before-RAS refresh cycle. RAS- only refresh cycle. Self refresh cycle. 2.0 Jul. 10, 1997 Correct errors DC Characteristics Test conditions of I CC1, I CC5: UCAS or ... to UCAS, ... Addition of note 5 AC Characteristics Correct numbers on tables t RPS max: 130/130/130 ns to 110/130/150 ns Notes concerning 2CAS control Addition of description Timing waveforms Change order of waveforms CAS-before-RAS refresh cycle Read-modify-write cycle 32 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Drawn by Approved by