HM5117800 Series 16 M FP DRAM (2-Mword × 8-bit) 2 k Refresh ADE-203-632E (Z) Rev. 5.0 Nov. 1997 Description The Hitachi HM5117800 is a CMOS dynamic RAM organized 2,097,152-word × 8-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117800 offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM5117800 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP. Features • • • • • • • • Single 5 V (±10%) High speed Access time: 60 ns/70 ns (max) Power dissipation Active mode: 550mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) Battery backup operation (L-version) Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Ordering Information Type No. Access time Package HM5117800J-6 HM5117800J-7 60 ns 70 ns 400-mil 28-pin plastic SOJ (CP-28DA) HM5117800LJ -6 HM5117800LJ -7 60 ns 70 ns HM5117800S-6 HM5117800S-7 60 ns 70 ns HM5117800LS-6 HM5117800LS-7 60 ns 70 ns HM5117800TT-6 HM5117800TT-7 60 ns 70 ns HM5117800LTT-6 HM5117800LTT-7 60 ns 70 ns HM5117800TS-6 HM5117800TS-7 60 ns 70 ns HM5117800LTS-6 HM5117800LTS-7 60 ns 70 ns 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 300-mil 28-pin plastic SOJ (CP-28DNA) 400-mil 28-pin plastic TSOP II (TTP-28DA) 300-mil 28-pin plastic TSOP II (TTP-28DB) HM5117800 Series Pin Arrangement HM5117800TT/LTT Series HM5117800TS/LTS Series HM5117800J/LJ Series HM5117800S/LS Series 1 28 VSS I/O0 2 27 I/O7 I/O6 I/O1 3 26 I/O6 25 I/O5 I/O2 4 25 I/O5 5 24 I/O4 I/O3 5 24 I/O4 WE 6 23 CAS WE 6 23 CAS RAS 7 22 OE RAS 7 22 OE NC 8 21 A9 NC 8 21 A9 A10 9 20 A8 A10 9 20 A8 A0 10 19 A7 A0 10 19 A7 A1 11 18 A6 A1 11 18 A6 A2 12 17 A5 A2 12 17 A5 A3 13 16 A4 A3 13 16 A4 14 15 VSS 14 15 VSS VCC 1 28 VSS I/O0 2 27 I/O7 I/O1 3 26 I/O2 4 I/O3 VCC VCC VCC (Top view) (Top view) Pin Description Pin name Function A0 to A10 Address input • Row/Refresh address A0 to A10 • Column address I/O0 to I/O7 Data input/data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection A0 to A9 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Block Diagram RAS CAS WE OE Timing and control Column decoder A0 Column A1 to • • • 2M array address 2M array buffers A9 • • • Row address buffers A10 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Row decoder 2M array 2M array 2M array 2M array 2M array 2M array I/O buffers I/O0 to I/O7 HM5117800 Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C Storage temperature Tstg –55 to +125 °C Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: 1. All voltage referred to VSS . 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) HM5117800 -6 Parameter -7 Symbol Min Max Min Max Unit Test conditions Operating current* , * 2 I CC1 — 100 — 90 mA t RC = min Standby current I CC2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2V Dout = High-Z I CC2 — 150 — 150 µA CMOS interface RAS, CAS ≥ VCC – 0.2V Dout = High-Z I CC3 — 100 — 90 mA t RC = min Standby current* I CC5 — 5 — 5 mA RAS = VIH CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 100 — 90 mA t RC = min Fast page mode current*1, * 3 I CC7 — 90 — 85 mA t PC = min Battery backup current (Standby with CBR refresh) (L-version) I CC10 — 500 — 500 µA CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 µs t RAS ≤ 0.3 µs Self refresh mode current (L-version) I CC11 — 300 — 300 µA CMOS interface RAS, CAS ≤ 0.2V Dout = High-Z Input leakage current I LI –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 4.2 mA 1 Standby current (L-version) RAS-only refresh current*2 1 Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V). 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *2, *18 Test Conditions • Input rise and fall time: 5 ns • Input timing reference levels: 0.8 V, 2.4 V • Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Random read or write cycle time t RC 110 — 130 — ns RAS precharge time t RP 40 — 50 — ns CAS precharge time t CP 10 — 10 — ns RAS pulse width t RAS 60 10000 70 10000 ns CAS pulse width t CAS 15 10000 18 10000 ns Row address setup time t ASR 0 — 0 — ns Row address hold time t RAH 10 — 10 — ns Column address setup time t ASC 0 — 0 — ns Column address hold time t CAH 10 — 15 — ns RAS to CAS delay time t RCD 20 45 20 52 ns 3 RAS to column address delay time t RAD 15 30 15 35 ns 4 RAS hold time t RSH 15 — 18 — ns CAS hold time t CSH 60 — 70 — ns CAS to RAS precharge time t CRP 5 — 5 — ns OE to Din delay time t OED 15 — 18 — ns 5 OE delay time from Din t DZO 0 — 0 — ns 6 CAS delay time from Din t DZC 0 — 0 — ns 6 Transition time (rise and fall) tT 3 50 3 50 ns 7 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes HM5117800 Series Read Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Access time from RAS t RAC — 60 — 70 ns 8, 9 Access time from CAS t CAC — 15 — 18 ns 9, 10, 17 Access time from address t AA — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 15 — 18 ns 9 Read command setup time t RCS 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — ns 12 Read command hold time to RAS t RRH 0 — 0 — ns 12 Column address to RAS lead time t RAL 30 — 35 — ns Column address to CAS lead time t CAL 30 — 35 — ns CAS to output in low-Z t CLZ 0 — 0 — ns Output data hold time t OH 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — ns Output buffer turn-off time t OFF — 15 — 15 ns 13 Output buffer turn-off to OE t OEZ — 15 — 15 ns 13 CAS to Din delay time t CDD 15 — 18 — ns 5 Write Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — ns 14 Write command hold time t WCH 10 — 15 — ns Write command pulse width t WP 10 — 10 — ns Write command to RAS lead time t RWL 15 — 18 — ns Write command to CAS lead time t CWL 15 — 18 — ns Data-in setup time t DS 0 — 0 — ns 15 Data-in hold time t DH 10 — 15 — ns 15 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Read-Modify-Write Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 155 — 181 — ns RAS to WE delay time t RWD 85 — 98 — ns 14 CAS to WE delay time t CWD 40 — 46 — ns 14 Column address to WE delay time t AWD 55 — 63 — ns 14 OE hold time from WE t OEH 15 — 18 — ns Refresh Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — ns Notes Fast Page Mode Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Fast page mode cycle time t PC 40 — 45 — ns Fast page mode RAS pulse width t RASP — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 35 — 40 ns 9, 17 RAS hold time from CAS precharge t CPRH 35 — 40 — ns 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes HM5117800 Series Fast Page Mode Read-Modify-Write Cycle HM5117800 -6 -7 Parameter Symbol Min Max Min Max Unit Fast page mode read-modify-write cycle time t PRWC 85 — 96 — ns WE delay time from CAS precharge t CPW 60 — 68 — ns Notes 14 Refresh Parameter Symbol Max Unit Note Refresh period t REF 32 ms 2048 cycles Refresh period (L-version) t REF 128 ms 2048 cycles Self Refresh Mode (L-version) HM5117800L -6 -7 Parameter Symbol Min Max Min Max Unit Notes RAS pulse width (self refresh) t RASS 100 — 100 — µs 19, 20, 21, 22 RAS precharge time (self refresh) t RPS 110 — 130 — ns CAS hold time (self refresh) t CHS –50 — –50 — ns Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in Fast page mode cycles. 17. Access time is determined by the longest among tAA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use tRPS instaed of tRP. 20. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 21. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 22. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Timing Waveforms*23 Read Cycle t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCH t RCS WE t DZC t CDD High-Z Din t DZO t OEA t OED OE t OEZ t CAC t OHO t AA t OFF t RAC t CLZ Dout t OH Dout 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column tWCS tWCH WE tDS Din Dout tDH Din High-Z* * t WCS Delayed Write Cycle*18 14 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t WCS (min) HM5117800 Series t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS WE t DZC t DS High-Z Din t DH Din t DZO t OEH t OED OE t OEZ t CLZ High-Z Dout Invalid Dout Read-Modify-Write Cycle*18 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR Address tRAH t ASC Row t CAH Column t RCS t CWD tCWL t AWD t RWL t RWD t WP WE t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA OE t CAC t OEZ t AA t RAC t OHO Dout Dout t CLZ 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z HM5117800 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t RPC t CRP t CRP CAS t ASR Address t RAH Row t OFF Dout High-Z CAS-Before-RAS Refresh Cycle 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RC t RP t RAS t RC t RP t RAS t RP RAS t RPC t CP tT t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP WE Address t OFF Dout Hidden Refresh Cycle 18 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z t WRH HM5117800 Series t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRP t RRH t WRH t WRP t WRH t RCS WE t DZC t CDD High-Z Din t DZO t OED t OEA OE t CAC t AA t RAC t OFF t OH t CLZ Dout t OEZ t OHO Dout 19 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD t PC t CAS t CP t RSH t CAS t CP t CRP t CAS CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH t CAL t ASC t CAH t CAL t ASC t CAH Column 1 Column 2 Column N t RCS t RCS t RCH t RCS t RRH t RCH t RCH WE t DZC Din t DZO t DZC t DZC t CDD t CDD High-Z High-Z t OED t DZO t OED t CDD High-Z t DZO t OED OE t RAC t AA t OH t OEA Fast Page Mode Early Write Cycle 20 Powered by ICminer.com Electronic-Library Service CopyRight 2003 t OHO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t CPA t AA Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N HM5117800 Series t RP t RASP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS Address t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS Din t DH Din 1 Dout t DS t DH Din 2 t DS t DH Din N High-Z* * t WCS t WCS (min) Fast Page Mode Delayed Write Cycle*18 21 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RASP t RP RAS tT t CP t CSH t CRP t CP t PC t RCD t CAS t RSH t CAS t CAS CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t RCS WE t WP t WP t WP t DZC t DS t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OED t OEH t OEH t OEH OE t CLZ t CLZ t OEZ t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Fast Page Mode Read-Modify-Write Cycle*18 22 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Invalid Dout Invalid Dout HM5117800 Series t RASP t RP RAS tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t ASC t CAH Column 2 t RWD t CWL Column N t CPW t AWD t CWL t CPW t AWD t CWD t RCS t CWL t AWD t CWD t RCS t RWL t CWD WE t RCS t WP t t DZC DS t WP t t DZC DS t WP t t DZC DS t DH t DH Din 1 Din t DZO t OED t DH Din 2 t OED t DZO t OED t DZO t OEH t OEH t OEH Din N OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t OEZ t CLZ t OHO t OEA t CAC t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 Dout 2 Dout N Self Refresh Cycle (L-version)* 19, 20, 21, 22 23 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series t RASS t RP t RPS RAS t RPC t CP tT t CRP t CSR t CHS CAS t WRP t WRH WE t OFF Dout Package Dimensions HM5117800J/LJ Series (CP-28DA) 24 Powered by ICminer.com Electronic-Library Service CopyRight 2003 High-Z HM5117800 Series Unit: mm 18.17 18.54 Max 10.16 ± 0.13 3.50 ± 0.26 1.30 Max 0.43 ± 0.10 0.41 ± 0.08 1.27 0.10 Dimension including the plating thickness Base material dimension 2.85 ± 0.12 14 0.74 0.80 +0.25 –0.17 1 11.18 ± 0.13 15 28 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DA Conforms Conforms 1.16 g HM5117800S/LS Series (CP-28DNA) 25 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Unit: mm 18.41 18.84 Max 7.62 ± 0.12 3.50 ± 0.26 1.165 Max 0.43 ± 0.10 0.41 ± 0.08 6.79 ± 0.18 1.27 0.10 Dimension including the plating thickness Base material dimension 26 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.25 2.45 +– 0.36 14 0.74 0.90 ± 0.26 1 8.51 ± 0.12 15 28 Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DNA — — 0.95 g HM5117800 Series HM5117800TT/LTT Series (TTP-28DA) Unit: mm 18.41 18.81 Max 15 10.16 28 1 0.42 ± 0.08 0.40 ± 0.06 1.27 0.21 14 0.80 M 11.76 ± 0.20 1.15 Max Dimension including the plating thickness Base material dimension 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) 0.68 0.13 ± 0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0° – 5° TTP-28DA Conforms — 0.43 g 27 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series HM5117800TS/LTS Series (TTP-28DB) Unit: mm 18.41 18.81 Max 15 7.62 28 0.42 ± 0.08 0.40 ± 0.06 1.27 14 0.21 M 0.80 9.22 ± 0.2 1.15 Max 0° – 5° Dimension including the plating thickness Base material dimension 28 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.13 ± 0.05 0.10 0.145 ± 0.05 0.125 ± 0.04 1.20 Max 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-28DB — — 0.35 g 0.63 1 HM5117800 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. 29 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HM5117800 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 1.0 Sep. 30, 1996 Initial issue Y. Kasama M. Mishima 2.0 Dec. 5, 1996 Addition of HM5117800-5 Series Y. Kasama M. Mishima Addition of HM5117800S/LS Series (CP-28DNA) Addition of HM5117800TS/LTS Series (TTP-28DB) Power dissipation (active) 660/605 mW(max) to 605/550/495 mW (max) DC Characteristics I CC1 max: I CC3 max: I CC6 max: I CC7 max: 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 120/110 mA to 110/100/90 mA 100/90 mA to 100/90/85 mA AC Characteristics t RRH min: 0/0 ns to 5/5/5 ns t RPC min: 0/0 ns to 5/5/5 ns 3.0 Feb. 24, 1997 AC Characteristics t RRH min: 5/5/5 ns to 0/0/0 ns Y. Kasama Y. Matsuno 4.0 Jun. 20, 1997 Deletion of HM5117800-5 Series Y. Kasama Y. Matsuno AC Characteristics Notes 10: tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max) to t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max) Notes 11: tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max) to t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 5.0 Nov. 1997 Change of Subtitle 30 Powered by ICminer.com Electronic-Library Service CopyRight 2003