ETC HM51W16405

HM51W16405 Series
HM51W17405 Series
16 M EDO DRAM (4-Mword × 4-bit)
4 k Refresh/2 k Refresh
ADE-203-647D(Z)
Rev. 4.0
Nov. 1997
Description
The Hitachi HM51W16405 Series, HM51W17405 Series are CMOS dynamic RAMs organized 4,194,304word × 4-bit. They employ the most advanced CMOS technology for high performance and low power.
The HM51W16405 Series, HM51W17405 Series offer Extended Data Out (EDO) Page Mode as a high
speed access mode. They have package variations of standard 300-mil 26-pin plastic SOJ and 300-mil 26pin plastic TSOP.
Features
• Single 3.3 V (±0.3 V)
• Access time: 50 ns/60 ns/70 ns (max)
• Power dissipation
 Active mode : 324 mW /288 mW /252 mW (max) (HM51W16405 Series)
: 360mW/324 mW/288 mW (max) (HM51W17405 Series)
 Standby mode : 7.2 mW (max)
: 0.36 mW (max) (L-version)
• EDO page mode capability
• Long refresh period
 4096 refresh cycles : 64 ms (HM51W16405 Series)
: 128 ms (L-version)
 2048 refresh cycles : 32 ms (HM51W17405 Series)
:128 ms (L-version)
• 4 variations of refresh
 RAS-only refresh
 CAS-before-RAS refresh
 Hidden refresh
 Self refresh (L-version)
• Battery backup operation (L-version)
• Test function
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HM51W16405 Series, HM51W17405
 16-bit parallel test mode
Ordering Information
Type No.
Access time
Package
HM51W16405S-5
HM51W16405S-6
HM51W16405S-7
50 ns
60 ns
70 ns
300-mil 26-pin plastic SOJ
(CP-26/24DB)
HM51W16405LS-5
HM51W16405LS-6
HM51W16405LS-7
50 ns
60 ns
70 ns
HM51W17405S-5
HM51W17405S-6
HM51W17405S-7
50 ns
60 ns
70 ns
HM51W17405LS-5
HM51W17405LS-6
HM51W17405LS-7
50 ns
60 ns
70 ns
HM51W16405TS-5
HM51W16405TS-6
HM51W16405TS-7
50 ns
60 ns
70 ns
HM51W16405LTS-5
HM51W16405LTS-6
HM51W16405LTS-7
50 ns
60 ns
70 ns
HM51W17405TS-5
HM51W17405TS-6
HM51W17405TS-7
50 ns
60 ns
70 ns
HM51W17405LTS-5
HM51W17405LTS-6
HM51W17405LTS-7
50 ns
60 ns
70 ns
2
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300-mil 26-pin plastic TSOP II
(TTP-26/24DA)
HM51W16405 Series, HM51W17405
Pin Arrangement
HM51W16405S/LS Series
HM51W16405TS/LTS Series
VCC
1
26
VSS
VCC
1
26
VSS
I/O1
2
25
I/O4
I/O1
2
25
I/O4
I/O2
3
24
I/O3
I/O2
3
24
I/O3
WE
4
23
CAS
WE
4
23
CAS
RAS
5
22
OE
RAS
5
22
OE
A11
6
21
A9
A11
6
21
A9
A10
8
19
A8
A10
8
19
A8
A0
9
18
A7
A0
9
18
A7
A1
10
17
A6
A1
10
17
A6
A2
11
16
A5
A2
11
16
A5
A3
12
15
A4
A3
12
15
A4
13
14
VSS
13
14
VSS
VCC
(Top view)
VCC
(Top view)
Pin Description
Pin name
Function
A0 to A11
Address input
•
Row/Refresh address A0 to A11
•
Column address
I/O1 to I/O4
Data input/Data output
RAS
Row address strobe
CAS
Column address strobe
WE
Read/Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
A0 to A9
3
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HM51W16405 Series, HM51W17405
Pin Arrangement
HM51W17405S/LS Series
HM51W17405TS/LTS Series
1
26
VSS
I/O1
2
25
I/O4
I/O3
I/O2
3
24
I/O3
23
CAS
WE
4
23
CAS
5
22
OE
RAS
5
22
OE
NC
6
21
A9
NC
6
21
A9
A10
8
19
A8
A10
8
19
A8
A0
9
18
A7
A0
9
18
A7
A1
10
17
A6
A1
10
17
A6
A2
11
16
A5
A2
11
16
A5
A3
12
15
A4
A3
12
15
A4
13
14
VSS
13
14
VSS
VCC
1
26
VSS
I/O1
2
25
I/O4
I/O2
3
24
WE
4
RAS
VCC
(Top view)
Function
A0 to A10
Address input
•
Row/Refresh address A0 to A10
•
Column address
I/O1 to I/O4
Data input/Data output
RAS
Row address strobe
CAS
Column address strobe
WE
Read/Write enable
OE
Output enable
VCC
Power supply
VSS
Ground
NC
No connection
4
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VCC
(Top view)
Pin Description
Pin name
VCC
A0 to A10
HM51W16405 Series, HM51W17405
Block Diagram(HM51W16405 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
A1
to
Column
•
•
•
4M array
address
buffers
A9
•
•
•
Row
address
Row decoder
4M array
I/O buffers
4M array
I/O1
to
I/O4
buffers
A10
4M array
A11
5
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HM51W16405 Series, HM51W17405
Block Diagram(HM51W17405 Series)
RAS
CAS
WE
OE
Timing and control
A0
Column decoder
A1
to
Column
•
•
•
4M array
address
buffers
A10
•
•
•
Row
address
Row decoder
4M array
I/O buffers
4M array
buffers
4M array
6
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I/O1
to
I/O4
HM51W16405 Series, HM51W17405
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5 (≤ +4.6 V (max))
V
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage
VCC
3.0
3.3
3.6
V
1, 2
Input high voltage
VIH
2.0
—
VCC + 0.3
V
1
Input low voltage
VIL
–0.3
—
0.8
V
1
Note:
1. All voltage referred to VSS .
7
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HM51W16405 Series, HM51W17405
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16405 Series)
HM51W16405
-5
Parameter
-6
-7
Symbol
Min Max Min Max Min Max Unit
Test conditions
I CC1
—
90
—
80
—
70
mA
t RC = min
I CC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC2
—
100 —
100 —
100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
90
—
80
—
70
mA
t RC = min
Standby current*
I CC5
—
5
—
5
—
5
mA
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
I CC6
—
90
—
80
—
70
mA
t RC = min
EDO page mode current*1, * 3 I CC7
—
80
—
70
—
65
mA
t HPC = min
Battery backup current
I CC10
—
300 —
300 —
300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 31.3 µs
t RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
I CC11
—
200 —
200 —
200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
I LI
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Output leakage current
I LO
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
VOH
2.4
VCC 2.4
VCC 2.4
VCC
V
High Iout = –2 mA
Output low voltage
VOL
0
0.4
0.4
0.4
V
Low Iout = 2 mA
Operating current* , *
1
2
Standby current
Standby current
(L-version)
RAS-only refresh current*2
1
0
0
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
8
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HM51W16405 Series, HM51W17405
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17405 Series)
HM51W17405
-5
Parameter
-6
-7
Symbol
Min Max Min Max Min Max Unit
Test conditions
Operating current* , * 2
I CC1
—
100 —
90
—
80
mA
t RC = min
Standby current
I CC2
—
2
—
2
—
2
mA
TTL interface
RAS, CAS = VIH
Dout = High-Z
—
1
—
1
—
1
mA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC2
—
100 —
100 —
100 µA
CMOS interface
RAS, CAS ≥ VCC – 0.2 V
Dout = High-Z
I CC3
—
100 —
90
—
80
mA
t RC = min
Standby current*
I CC5
—
5
5
—
5
mA
RAS = VIH
CAS = VIL
Dout = enable
CAS-before-RAS refresh
current
I CC6
—
100 —
90
—
80
mA
t RC = min
EDO page mode current*1, * 3 I CC7
—
90
80
—
75
mA
t HPC = min
Battery backup current
I CC10
—
300 —
300 —
300 µA
CMOS interface
Dout = High-Z, CBR
refresh: tRC = 62.5 µs
t RAS ≤ 0.3 µs
Self refresh mode current
(L-version)
I CC11
—
200 —
200 —
200 µA
CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current
I LI
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Output leakage current
I LO
–10 10
–10 10
–10 10
µA
0 V ≤ Vin ≤ 4.6 V
Dout = disable
Output high voltage
VOH
2.4
VCC 2.4
VCC 2.4
VCC
V
High Iout = –2 mA
Output low voltage
VOL
0
0.4
0.4
0.4
V
Low Iout = 2 mA
1
Standby current
(L-version)
RAS-only refresh current*2
1
—
—
0
0
Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
9
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HM51W16405 Series, HM51W17405
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1
Input capacitance (Clocks)
CI2
—
7
pF
1
Output capacitance (Data-in, Data-out)
CI/O
—
7
pF
1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
10
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HM51W16405 Series, HM51W17405
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18
Test Conditions
•
•
•
•
•
Input rise and fall time: 2 ns
Input levels: VIL = 0 V, V IH = 3 V
Input timing reference levels: 0.8 V, 2.0 V
Output timing reference levels: 0.8 V, 2.0 V
Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Random read or write cycle time
t RC
84
—
104
—
124
—
ns
RAS precharge time
t RP
30
—
40
—
50
—
ns
CAS precharge time
t CP
8
—
10
—
13
—
ns
RAS pulse width
t RAS
50
10000 60
10000 70
10000 ns
CAS pulse width
t CAS
8
10000 10
10000 13
10000 ns
Row address setup time
t ASR
0
—
0
—
0
—
ns
Row address hold time
t RAH
8
—
10
—
10
—
ns
Column address setup time
t ASC
0
—
0
—
0
—
ns
Column address hold time
t CAH
8
—
10
—
13
—
ns
RAS to CAS delay time
t RCD
12
37
14
45
14
52
ns
3
RAS to column address delay time
t RAD
10
25
12
30
12
35
ns
4
RAS hold time
t RSH
10
—
13
—
13
—
ns
CAS hold time
t CSH
35
—
40
—
45
—
ns
CAS to RAS precharge time
t CRP
5
—
5
—
5
—
ns
OE to Din delay time
t OED
13
—
15
—
18
—
ns
5
OE delay time from Din
t DZO
0
—
0
—
0
—
ns
6
CAS delay time from Din
t DZC
0
—
0
—
0
—
ns
6
Transition time (rise and fall)
tT
2
50
2
50
2
50
ns
7
11
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HM51W16405 Series, HM51W17405
Read Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Access time from RAS
t RAC
—
50
—
60
—
70
ns
8, 9, 20
Access time from CAS
t CAC
—
13
—
15
—
18
ns
9, 10, 17,
20
Access time from address
t AA
—
25
—
30
—
35
ns
9, 11, 17,
20
Access time from OE
t OEA
—
13
—
15
—
18
ns
9, 20
Read command setup time
t RCS
0
—
0
—
0
—
ns
Read command hold time to CAS
t RCH
0
—
0
—
0
—
ns
Read command hold time from
RAS
t RCHR
50
—
60
—
70
—
ns
Read command hold time to RAS
t RRH
0
—
0
—
0
—
ns
Column address to RAS lead time
t RAL
25
—
30
—
35
—
ns
Column address to CAS lead time
t CAL
15
—
18
—
23
—
ns
CAS to output in low-Z
t CLZ
0
—
0
—
0
—
ns
Output data hold time
t OH
3
—
3
—
3
—
ns
Output data hold time from OE
t OHO
3
—
3
—
3
—
ns
Output buffer turn-off time
t OFF
—
13
—
15
—
15
ns
13, 22
Output buffer turn-off to OE
t OEZ
—
13
—
15
—
15
ns
13
CAS to Din delay time
t CDD
13
—
15
—
18
—
ns
5
Output data hold time from RAS
t OHR
3
—
3
—
3
—
ns
22
Output buffer turn-off to RAS
t OFR
—
13
—
15
—
15
ns
22
Output buffer turn-off to WE
t WEZ
—
13
—
15
—
15
ns
WE to Din delay time
t WED
13
—
15
—
18
—
ns
RAS to Din delay time
t RDD
13
—
15
—
18
—
ns
RAS next CAS delay time
t RNCD
50
—
60
—
70
—
ns
12
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12
12
22
HM51W16405 Series, HM51W17405
Write Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write command setup time
t WCS
0
—
0
—
0
—
ns
14
Write command hold time
t WCH
8
—
10
—
13
—
ns
Write command pulse width
t WP
8
—
10
—
10
—
ns
Write command to RAS lead time
t RWL
8
—
10
—
13
—
ns
Write command to CAS lead time
t CWL
8
—
10
—
13
—
ns
Data-in setup time
t DS
0
—
0
—
0
—
ns
15
Data-in hold time
t DH
8
—
10
—
13
—
ns
15
Notes
Read-Modify-Write Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Read-modify-write cycle time
t RWC
111
—
135
—
161
—
ns
RAS to WE delay time
t RWD
67
—
79
—
92
—
ns
14
CAS to WE delay time
t CWD
30
—
34
—
40
—
ns
14
Column address to WE delay time
t AWD
42
—
49
—
57
—
ns
14
OE hold time from WE
t OEH
13
—
15
—
18
—
ns
Refresh Cycle
HM51W16405/HM51W17405
-5
Parameter
Symbol
-6
-7
Min
Max
Min
Max
Min
Max
Unit
CAS setup time (CBR refresh cycle) t CSR
5
—
5
—
5
—
ns
CAS hold time (CBR refresh cycle) t CHR
8
—
10
—
10
—
ns
WE setup time (CBR refresh cycle) t WRP
0
—
0
—
0
—
ns
WE hold time (CBR refresh cycle)
t WRH
8
—
10
—
10
—
ns
RAS precharge to CAS hold time
t RPC
5
—
5
—
5
—
ns
Notes
13
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HM51W16405 Series, HM51W17405
EDO Page Mode Cycle
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min Max
Min Max
Min Max
Unit
Notes
EDO page mode cycle time
t HPC
20
—
25
30
ns
21
EDO page mode RAS pulse width
t RASP
—
100000 —
100000 —
100000 ns
16
Access time from CAS precharge
t CPA
—
30
—
35
—
40
ns
9, 17, 20
RAS hold time from CAS precharge t CPRH
30
—
35
—
40
—
ns
Output data hold time from CAS low t DOH
3
—
3
—
3
—
ns
CAS hold time referred OE
t COL
8
—
10
—
13
—
ns
CAS to OE setup time
t COP
5
—
5
—
5
—
ns
Read command hold time from
CAS precharge
t RCHC
30
—
35
—
40
—
ns
—
—
9, 17
EDO Page Mode Read-Modify-Write Cycle
HM51W16405/HM51W17405
-5
Parameter
Symbol
-6
-7
Min
Max
Min
Max
Min
Max
Unit
Notes
EDO page mode read- modify-write t HPRWC
cycle time
57
—
68
—
79
ns
WE delay time from CAS precharge t CPW
45
—
54
—
62
ns
14
Notes
Test Mode Cycle *19
HM51W16405/HM51W17405
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Test mode WE setup time
t WTS
0
—
0
—
0
—
ns
Test mode WE hold time
t WTH
8
—
10
—
10
—
ns
Refresh (HM51W16405 Series)
Parameter
Symbol
Max
Unit
Notes
Refresh period
t REF
64
ms
4096 cycles
Refresh period (L-version)
t REF
128
ms
4096 cycles
14
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HM51W16405 Series, HM51W17405
Refresh (HM51W17405 Series)
Parameter
Symbol
Max
Unit
Notes
Refresh period
t REF
32
ms
2048 cycles
Refresh period (L-version)
t REF
128
ms
2048 cycles
Self Refresh Mode (L-version)
HM51W16405L/HM51W17405L
-5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
RAS pulse width (self refresh)
t RASS
100
—
100
—
100
—
µs
RAS precharge time (self refresh)
t RPS
90
—
110
—
130
—
ns
CAS hold time (self refresh)
t CHS
–50
—
–50
—
–50
—
ns
Notes
Notes: 1. AC measurements assume t T = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If
the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are
required.
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC .
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA .
5. Either t OED or tCDD must be satisfied.
6. Either t DZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V IH (min) and VIL (max).
8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, t RAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either t RCH or tRRH must be satisfied for a read cycles.
13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD
≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥
t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the
selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.
15
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HM51W16405 Series, HM51W17405
15. These parameters are referred to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16. t RASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among t AA , t CAC and t CPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to device.
19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M
×4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS-before-RAS
(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1
to I/O4) and read out from each I/O.
If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read
cycle, then the device has passed. If they are not equal, data output pin is a low state, then the
device has failed.
Refresh during test mode operation can be performed by normal read cycles or by WCBR
refresh cycles.
To get out of test mode and enter a normal operation mode, perform either a regular CASbefore-RAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of tRAC , t AA , t CAC and t CPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater
than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
22. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t OHR and t OH , and between t OFR and t OFF.
23. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If t RASS > 100 µs, then RAS
precharge time should use tRPS instead of tRP.
24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048
cycles (4096 cycles: HM51W16405 Series, 2048 cycles: HM51W17405 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 32 ms (64 ms: HM51W16405
Series, 32 ms: HM51W17405 Series) immediately after exiting from and before entering into the
self refresh mode.
26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
27. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
16
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HM51W16405 Series, HM51W17405
Timing Waveforms*27
Read Cycle
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
tT
CAS
t RAD
t ASR
Address
t RAH
t RAL
t ASC
t CAL
t CAH
Column
Row
t RRH
t RCHR
t RCH
t RCS
WE
t WED
t DZC
t CDD
t RDD
High-Z
Din
t DZO
t OEA
t OED
OE
t OEZ
t OHO
t OFF
t CAC
t AA
t OH
t OFR
t OHR
t RAC
t CLZ
t WEZ
Dout
Dout
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HM51W16405 Series, HM51W17405
Early Write Cycle
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRCD
tRSH
tCAS
tT
CAS
tASR
Address
tRAH
Row
tASC
tCAH
Column
tWCS
tWCH
WE
tDS
Din
Dout
tDH
Din
High-Z*
* t WCS
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t WCS (min)
HM51W16405 Series, HM51W17405
Delayed Write Cycle*18
t RC
t RAS
t RP
RAS
t CSH
t CRP
t RCD
t RSH
t CAS
tT
CAS
t ASR
Address
t RAH
t ASC
Row
t CAH
Column
t CWL
t RWL
t WP
t RCS
WE
t DZC
t DS
High-Z
Din
t DH
Din
t DZO
t OEH
t OED
OE
t OEZ
t CLZ
High-Z
Dout
Invalid Dout
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19
HM51W16405 Series, HM51W17405
Read-Modify-Write Cycle *18
t RWC
t RAS
t RP
RAS
tT
t RCD
t CAS
t CRP
CAS
t RAD
t ASR
Address
tRAH
t ASC
Row
t CAH
Column
t RCS
t CWD
tCWL
t AWD
t RWL
t RWD
t WP
WE
t DZC
t DH
t DS
High-Z
Din
Din
t OED
t DZO
t OEH
t OEA
OE
t CAC
t OEZ
t AA
t RAC
t OHO
Dout
Dout
t CLZ
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High-Z
HM51W16405 Series, HM51W17405
RAS-Only Refresh Cycle
t RC
t RAS
t RP
RAS
tT
t CRP
t RPC
t CRP
CAS
t ASR
Address
t RAH
Row
t OFR
t OFF
High-Z
Dout
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HM51W16405 Series, HM51W17405
CAS-Before-RAS Refresh Cycle
t RC
t RP
t RAS
t RP
RAS
t RPC
t CSR
t CHR
t RPC
tT
CAS
t CP
t WRP
t WRH
t CP
WE
Address
t OFR
t OFF
Dout
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High-Z
t CRP
HM51W16405 Series, HM51W17405
Hidden Refresh Cycle
t RC
t RAS
t RP
t RC
t RAS
t RC
t RP
t RAS
t RP
RAS
tT
t RSH
t CHR
t CRP
t RCD
CAS
t RAD
t ASR t RAH
Address
t RAL
t ASC
Row
t CAH
Column
t WRH
t WRP
t WRP
tWRH
t RCS
t RRH
t RRH
t RCH
WE
t DZC
High-Z
t WED
t CDD
t RDD
Din
t DZO
t OED
t OEA
OE
t CAC
t AA
t RAC
t OFF
t OH
t CLZ
Dout
t OEZ
t WEZ
t OHO
Dout
t OFR
t OHR
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HM51W16405 Series, HM51W17405
EDO Page Mode Read Cycle
t RP
t RNCD
RAS
tT
t CSH
t CP
t HPC
t CAS
CAS
t CP
t HPC
t CPRH
t CP
t
t CRP
RSH
t CAS
t RCHR
t RCS
t HPC
t RASP
tCAS
tCAS
t RCHC
t RCH t RCS
t RRH
t RCH
WE
tASR
Address
tRAH tASC
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
t CAL
t CAL
t RAL
t CAH
tASC
t WED
Column 4
t CAL
t CAL
tRDD
tCDD
tDZC
High-Z
Din
tCOL
tDZO
tCOP
tOED
OE
tAA
tCAC
tCAC
tAA
tWEZ
tCPA
tAA
tCAC
tOEZ
tOHO
tDOH
Dout 2
Dout 2
tOHO
Dout 3
tCAC
tOHO
tOFF
tOH
tOEA
Dout 4
Dout 1
tAA
tOEZ
tOEA
tRAC
Dout
tOFR
tOHR
tOEZ
tCPA
tCPA
tOEA
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HM51W16405 Series, HM51W17405
EDO Page Mode Early Write Cycle
tRP
tRASP
RAS
tT
tCSH
tHPC
tCAS
tRCD
tCP
tRSH
tCAS
tCP
tCAS
tCRP
CAS
tASR
Address
Row
tRAH
tASC
tCAH
Column 1
tWCS
tWCH
tASC
tCAH
Column 2
tWCS
tWCH
tASC
tCAH
Column N
tWCS
tWCH
WE
tDS
Din
tDH
Din 1
Dout
tDS
tDH
Din 2
tDS
tDH
Din N
High-Z*
* t WCS
t WCS (min)
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HM51W16405 Series, HM51W17405
EDO Page Mode Delayed Write Cycle *18
t RASP
t RP
RAS
tT
t CP
t CSH
t RCD
t CRP
t CP
t HPC
t CAS
t CAS
t RSH
t CAS
CAS
t RAD
t ASR
t ASC
t RAH
Address
t ASC
t CAH
Row
t ASC
t CAH
Column 1
t CAH
Column 2
t CWL
Column N
t CWL
t CWL
t RWL
t RCS
t RCS
t RCS
WE
t WP
t WP
t WP
t DZC t DS
t DZC t DS
t DZC t DS
t DH
t DH
Din
1
Din
Din
2
t DZO
Din
N
t DZO
t DZO
t DH
t OED
t OED
t OED
t OEH
t OEH
t OEH
OE
t CLZ
t CLZ
t OEZ
t CLZ
t OEZ
t OEZ
High-Z
Dout
Invalid Dout
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Invalid Dout
Invalid Dout
HM51W16405 Series, HM51W17405
EDO Page Mode Read-Modify-Write Cycle *18
t RASP
t RP
RAS
tT
t HPRWC
t CP
t RCD
t RSH
t CP
t CAS
t CAS
t CRP
t CAS
CAS
t RAD
t ASR
Address
t ASC
t RAH
Row
t ASC
t CAH
t CAH
Column 1
t ASC
t CAH
Column 2
t RWD
t CWL
Column N
t CPW
t AWD
t CWL
t CPW
t AWD
t CWD
t RCS
t CWL
t AWD
t CWD
t RCS
t RWL
t CWD
WE
t RCS
t WP
t
t DZC DS
t WP
t
t DZC DS
t WP
t
t DZC DS
t DH
t DH
Din
1
Din
t DZO
t OED
t DH
Din
2
t OED
t DZO
t OED
t DZO
t OEH
t OEH
t OEH
Din
N
OE
t OHO
t OEA
t CAC
t OHO
t OEA
t CAC
t AA
t AA
t CPA
t RAC
t OEZ
t CLZ
t OHO
t OEA
t CAC
t AA
t CPA
t OEZ
t CLZ
t OEZ
t CLZ
High-Z
Dout
Dout 1
Dout 2
Dout N
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HM51W16405 Series, HM51W17405
EDO Page Mode Mix Cycle (1)
t RP
t RASP
RAS
tT
t CAS
CAS
t CRP
t CP
t CP
t CP
t CAS
tCAS
tCAS
t CSH
tRSH
t RCD
t WCS
t WCH
tCPW
tAWD
WE
t ASC
tRAH
tASR
Address
Row
tCAH
Column 1
t CAL
t DS
Din
t ASC t CAH
tASC t CAH
Column 2
Column 3
t CAL
tWP
tASC
t RAL
t CAH
Column 4
t CAL
t DH
Din 1
t RRH
t RCH
t RCS
t RCS
High-Z
tRDD
tCDD
t CAL
t DH
t DS
Din 3
tOED
tWED
OE
tCPA
tAA
tCAC
Dout
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tOFR
tWEZ
tCPA
tCPA
tAA
tOEA
t DOH
Dout 2
t OEZ
tCAC t OHO
Dout 3
tAA
tOEZ
tCAC
tOHO
tOEA
tOFF
tOH
Dout 4
HM51W16405 Series, HM51W17405
EDO Page Mode Mix Cycle (2)
t RNCD
t RP
t RASP
RAS
tT
t CSH
t CAS
CAS
t RCD
t CAS
tCAS
t RCH tWCS t WCH
tRAH
Row
tCAH
Column 1
t ASC t CAH
t ASC t CAH
Column 2
Column 3
t CAL
t CAL
t RRH
t RCH
tWP
tCPW
t ASC
tRSH
t RCS
t RCS
WE
Address
tCAS
t RCHR
t RCS
tASR
t CRP
t CP
t CP
t RAL
t CAH
tASC
Column 4
t CAL
t CAL
t DS
t DS
High-Z
Din
t DH
tRDD
tCDD
t DH
Din 2
Din 3
tOED
tOED
tCOP
tWED
tCOL
OE
t OEA
tAA
tOEA
tCAC
tOEZ
tCPA
tAA
tCAC
tRAC
tOEZ
t OHO
t OHO
Dout
Dout 1
tOFR
tWEZ
tCPA
Dout 3
tAA
tCAC
tOEZ
tOEA
tOFF
tOH
tOHO
Dout 4
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HM51W16405 Series, HM51W17405
Test Mode Cycle *19
Set Cycle**
Test Mode Cycle
*,**
Reset Cycle
Normal Mode
RAS
CAS
WE
* CBR or RAS-only refresh
** Address, Din, OE: H or L
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HM51W16405 Series, HM51W17405
Test Mode Set Cycle
t RC
t RP
t RAS
t RP
RAS
t CSR
t CHR
tT
CAS
t CP
t WTS
WE
t RPC
t CRP
@@@
t RPC
t WTH
t CP
Address
t OFR
t OFF
Dout
High-Z
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HM51W16405 Series, HM51W17405
Self Refresh Cycle (L-version)* 23, *24, * 25, * 26
t RASS
t RP
t RPS
RAS
t RPC
t CP
tT
t CRP
t CSR
t CHS
CAS
t WRP
t WRH
WE
t OFR
t OFF
Dout
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High-Z
HM51W16405 Series, HM51W17405
Package Dimensions
HM51W16405S/LS Series
HM51W17405S/LS Series (CP-26/24DB)
Unit: mm
1.30 Max
0.43 ± 0.10
0.41 ± 0.08
1.27
2.54
Dimension including the plating thickness
Base material dimension
2.65 ± 0.12
13
0.80 +0.25
–0.17
6 8
0.74
3.50 ± 0.26
1
8.51 ± 0.13
14
7.62 ± 0.13
26
16.90
17.27 Max
21 19
+ 0.19
6.79 – 0.18
0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
CP-26/24DB
Conforms
Conforms
0.8 g
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HM51W16405 Series, HM51W17405
HM51W16405TS/LTS Series
HM51W17405TS/LTS Series (TTP-26/24DA)
Unit: mm
14
7.62
26
17.14
17.54 Max
21 19
0.42 ± 0.08
0.40 ± 0.06
6 8
1.27
13
0.80
0.21 M
9.22 ± 0.20
1.15 Max
0.10
Dimension including the plating thickness
Base material dimension
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0.13 ± 0.05
2.54
0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0° – 5°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
TTP-26/24DA
Conforms
—
0.30 g
0.68
1
HM51W16405 Series, HM51W17405
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
USA
Tel: 800-285-1601
Fax:303-297-0447
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
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HM51W16405 Series, HM51W17405
Revision Record
Rev.
Date
Contents of Modification
1.0
Oct. 14, 1996
Initial issue
Y. Kasama M. Mishima
Addition of HM51W16405-5 Series
Y. Kasama Y. Matsuno
2.0
Nov. 4, 1996
Drawn by
Approved by
Addition of HM51W17405-5 Series
Power dissipation (active)
360/324 mW(max) to 324/288/252 mW (max)
(HM51W16405 Series)
396/360 mW(max) to 360/324/288 mW (max)
(HM51W17405 Series)
DC Characteristics (HM51W16405 Series)
I CC7 max: 100/90 mA to 80/70/65 mA
DC Characteristics (HM51W17405 Series)
I CC1 max:
I CC3 max:
I CC6 max:
I CC7 max:
110/100 mA to 100/90/80 mA
110/100 mA to 100/90/80 mA
110/100 mA to 100/90/80 mA
110/100 mA to 90/80/75 mA
AC Characteristics
t RCD min: 20/20 ns to 12/14/14 ns
t RAD min: 15/15 ns to 10/12/12 ns
t RSH min: 15/18 ns to 10/13/13 ns
t RRH min: 0/0 ns to 5/5/5 ns
t RWC min: 149/175 ns to 111/135/161 ns
t RWD min: 82/95 ns to 67/79/92 ns
t CWD min: 37/43 ns to 30/34/40 ns
t AWD min: 52/60 ns to 42/49/57 ns
t RPC min: 0/0 ns to 5/5/5 ns
t HPRWC min: 79/90 ns to 57/68/79 ns
Timing Waveforms
Addition of t RNCD timing to EDO page mode mix
cycle (2)
3.0
Feb. 27, 1997
AC Characteristics
t RRH min: 5/5/5 ns to 0/0/0 ns
4.0
Nov. 1997
Change of Subtitle
36
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Y. Kasama Y. Matsuno