ETC IBM13N32644JCA-360T

.
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Features
• 168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
• 32Mx64/72 Synchronous DRAM DIMM
• Two speed sorts:
• -260 and -360 for PC100 applications
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks
• Module has 2 physical banks
• Fully Synchronous to positive Clock Edge
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge commands
• Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Suspend Mode and Power Down Mode
• 12/10/2 Addressing (Row/Column/Bank)
• 4096 Refresh cycles distributed across 64ms
• Serial Presence Detect
• Card size: 5.25" x 1.375" x 0.158" max
• Gold contacts
• SDRAMs in TSOP Type II Package
Description
IBM13N32644JCA / IBM13N32734JCA are unbuffered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
32Mx64 and 32Mx72 high-speed memory arrays
and are configured as two 16Mx64/72 physical
banks. The DIMMs use sixteen (32Mx64) or eighteen (32Mx72) 16Mx8 SDRAMs in 400mil TSOP II
packages. The DIMMs achieve high-speed datatransfer rates of up to 100MHz by employing a
prefetch/pipeline hybrid architecture that supports
the JEDEC 1N rule while allowing very low burst
power.
The -260 and -360 speed sort DIMMs are compatible with the Intel PC100 SDRAM unbuffered DIMM
specification.
All control, address, and data input/output circuits
are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0 - CK3). Internal operating modes are defined by combinations of RAS,
CAS, WE, S0-S3, DQMB, and CKE0-CKE1 signals.
A command decoder initiates the necessary timings
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
Card Outline
(Front) 1
(Back) 85
09K3540.F38351
8/99
10 11
94 95
40 41
124 125
84
168
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Pin Description
CK0 - CK3
Clock Inputs
CKE0 - CKE1
DQ0 - DQ63
Clock Enables
CB0 - CB7
RAS
Row Address Strobe
CAS
Column Address Strobe
VDD
WE
Write Enable
VSS
Ground
S0, S1, S2, S3
Chip Selects
NC
No Connect
A0 - A9, A11
DQMB0 - DQMB7
Data Input/Output
Check Bit Data Input/Output
Data Mask
Power (3.3V)
Address Inputs
SCL
Serial Presence Detect Clock Input
A10 /AP
Address Input/Autoprecharge
SDA
Serial Presence Detect Data Input/Output
BA0, BA1
SDRAM Bank Address Inputs
SA0-2
Serial Presence Detect Address Inputs
WP
Serial Presence Detect Write Protect Input
Pinout
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
1
VSS
85
VSS
22
CB1
106
CB5
43
VSS
127
VSS
64
VSS
148
VSS
2
DQ0
86
DQ32
23
VSS
107
VSS
44
NC
128
CKE0
65
DQ21
149
DQ53
3
DQ1
87
DQ33
24
NC
108
NC
45
S2
129
S3
66
DQ22
150
DQ54
4
DQ2
88
DQ34
25
NC
109
NC
46
DQMB2
130
DQMB6
67
DQ23
151
DQ55
5
DQ3
89
DQ35
26
VDD
110
VDD
47
DQMB3
131
DQMB7
68
VSS
152
VSS
6
VDD
90
VDD
27
WE
111
CAS
48
NC
132
NC
69
DQ24
153
DQ56
DQ57
7
DQ4
91
DQ36
28
DQMB0
112
DQMB4
49
VDD
133
VDD
70
DQ25
154
8
DQ5
92
DQ37
29
DQMB1
113
DQMB5
50
NC
134
NC
71
DQ26
155
DQ58
9
DQ6
93
DQ38
30
S0
114
S1
51
NC
135
NC
72
DQ27
156
DQ59
10
DQ7
94
DQ39
31
NC
115
RAS
52
CB2
136
CB6
73
VDD
157
VDD
11
DQ8
95
DQ40
32
VSS
116
VSS
53
CB3
137
CB7
74
DQ28
158
DQ60
12
VSS
96
VSS
33
A0
117
A1
54
VSS
138
VSS
75
DQ29
159
DQ61
13
DQ9
97
DQ41
34
A2
118
A3
55
DQ16
139
DQ48
76
DQ30
160
DQ62
14
DQ10
98
DQ42
35
A4
119
A5
56
DQ17
140
DQ49
77
DQ31
161
DQ63
15
DQ11
99
DQ43
36
A6
120
A7
57
DQ18
141
DQ50
78
VSS
162
VSS
16
DQ12
100
DQ44
37
A8
121
A9
58
DQ19
142
DQ51
79
CK2
163
CK3
17
DQ13
101
DQ45
38
A10/AP
122
BA0
59
VDD
143
VDD
80
NC
164
NC
BA1
123
A11
60
DQ20
144
DQ52
81
WP
165
SA0
61
NC
145
NC
82
SDA
166
SA1
NC
83
SCL
167
SA2
NC
84
VDD
168
VDD
18
VDD
102
VDD
39
19
DQ14
103
DQ46
40
VDD
124
VDD
DQ47
41
VDD
125
CK1
CB4
42
CK0
126
NC
20
21
DQ15
CB0
104
105
62
63
NC
146
*CKE1
147
Note: All pin assignments are consistent for all 8-byte unbuffered versions. Check Bits (CB0 - CB7) are applicable only to the x72 DIMM; for the x64 DIMM
these pins are no connects (NC). * CKE1 is terminated with a 10k ohm pullup resistor.
Ordering Information
Part Number
IBM13N32644JCA-260T
IBM13N32644JCA-360T
IBM13N32734JCA-260T
IBM13N32734JCA-360T
Organization
Leads
Dimension
Power
10ns
Gold
5.25" x 1.375" x 0.158"
3.3V
16Mx64
16Mx72
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 18
Clock Cycle
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
32Mx64 SDRAM DIMM Block Diagram
(2 Bank, 16Mx8 SDRAMs)
S0
S1
DQMB0
*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
CS
D8
DQMB1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
CS
D12
DQMB5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
S2
D9
S3
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D10
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D5
CS
D13
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
CS
D14
DQMB7
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB6
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
CS
D11
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
CS
D15
Note: Exact DQ wiring may differ from that shown above.
CK0
CLK: SDRAMs D0 - D1, D4 - D5, 3.3pF Cap
CK1
CLK: SDRAMs D8 - D9, D12 - D13, 3.3pF Cap
CK2
CLK: SDRAMs D2 - D3, D6 - D7, 3.3pF Cap
CK3
CLK: SDRAMs D10 - D11, D14 - D15, 3.3pF Cap
A0 - A11
10K
CKE1
CKE: SDRAMs D8 - D15
A0-A11: SDRAMs D0 - D15
BA0
A13/BS0: SDRAMs D0 - D15
BA1
A12/BS1: SDRAMs D0 - D15
Serial PD
RAS
VDD
.33µF
VSS
VDD
D0 - D15
0.1µF
D0 - D15
RAS: SDRAMs D0 - D15
CAS
CAS: SDRAMs D0 - D15
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D15
SCL
WP
47K
SDA
A0
A1
A2
SA0
SA1
SA2
* All resistor values are 10 ohms except as shown.
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
32Mx72 SDRAM DIMM Block Diagram
(2 Bank, 16Mx8 SDRAMs)
S1
S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
*
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D0
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D10
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D2
D11
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS
D3
CS
D4
A0-A11: SDRAMs D0 - D17
A13/BS0: SDRAMs D0 - D17
A12/BS1: SDRAMs D0 - D17
D0 - D17
VDD
.33µF
VSS
0.1µF
D0 - D17
* All resistor values are 10 ohms except as shown.
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
CS
D15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
CS
D16
CS
DQMB7
D12
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
CS
D17
CS
Note: Exact DQ wiring may differ from that shown above.
D13
CK0
CLK: SDRAMs D0 - D2, D5 - D6
CK1
CLK: SDRAMs D9 - D11, D14 - D15
CK2
CLK: SDRAMs D3 - D4, D7 - D8, 3.3pF Cap.
CK3
CLK: SDRAMs D12 - D13, D16 - D17, 3.3pF Cap.
VDD
Serial PD
10K
CKE1
RAS
CKE: SDRAMs D9 - D17
RAS: SDRAMs D0 - D17
CAS
CAS: SDRAMs D0 - D17
CKE0
CKE: SDRAMs D0 - D8
WE
WE: SDRAMs D0 - D17
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 18
D14
DQMB6
DQMB3
BA0
BA1
D5
CS
DQM
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB2
A0 - A11
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQMB5
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S3
S2
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SCL
WP
47K
SDA
A0
A1
A2
SA0
SA1
SA2
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0 - CK3
Input
Pulse
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
CKE0, CKE1
Input
Level
Active
High
Activates the SDRAM CLK signals when high and deactivates them when low. By deactivating the clocks, CKE0/CKE1 low initiates the Power Down mode, Suspend mode, or
the Self Refresh mode.
S0 - S3
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the comActive Low mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
BA0, BA1
Input
Level
A0 - A9
A10/AP
A11
Input
DQ0 - DQ63, Input
CB0 - CB7
Output
—
Selects which SDRAM bank is to be active.
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to precharge.
Level
—
Data and Check Bit Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the Write operation
if DQM is high.
DQMB0 DQMB7
Input
Pulse
Active
High
SA0 - SA2
Input
Level
—
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
Input
Output
Level
—
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
SCL
Input
Pulse
—
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
WP
Input
Level
Active
High
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
VDD, VSS
Supply
09K3540.F38351
8/99
Power and ground for the module.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Serial Presence Detect (Part 1 of 2)
Byte #
Description
0
Number of Serial PD Bytes Written during Production
1
Total Number of Bytes in Serial PD device
2
Fundamental Memory Type
3
4
5
Number of DIMM Banks
6-7
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
128
80
256
08
SDRAM
04
Number of Row Addresses on Assembly
12
0C
Number of Column Addresses on Assembly
9
0A
Data Width of Assembly
32M x 64
02
48
x72
00
Voltage Interface Level of this Assembly
LVTTL
01
9
SDRAM Device Cycle Time at CL=3
10.0ns
A0
10
SDRAM Device Access Time from Clock
at CL=3
6.0ns
60
11
DIMM Configuration Type
Non-Parity
00
12
Refresh Rate/Type
13
Primary SDRAM Device Width
8
32M x 72
2
x64
32M x 64
32M x 72
ECC
02
SR/1x(15.625us)
80
32M x 64
14
Error Checking SDRAM Device Width
15
SDRAM Device Attr: Min Clk Delay, Random Col Access
16
17
32M x 72
x8
08
N/A
00
x8
08
1 Clock
01
SDRAM Device Attributes: Burst Lengths Supported
1,2,4,8, Full Page
8F
SDRAM Device Attributes: Number of Device Banks
4
04
18
SDRAM Device Attributes: CAS Latencies Supported
2, 3
06
19
SDRAM Device Attributes: CS Latency
0
01
20
SDRAM Device Attributes: WE Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes: General
23
Minimum Clock Cycle at CL=2
0
01
Unbuffered
00
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, VDD +/- 10%
0E
-260
10.0ns
A0
-360
15.0ns
F0
-260
6.0ns
60
-360
9.0ns
90
24
Maximum Data Access Time (tAC) from
Clock at CL=2
25
Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time (tAC) from Clock at CL=1
N/A
00
27
Minimum Row Precharge Time (tRP)
20ns
14
28
Minimum Row Active to Row Active delay (tRRD)
20ns
14
1.
2.
3.
4.
5.
6.
7.
Notes
1
1
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 18
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Serial Presence Detect (Part 2 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
29
Minimum RAS to CAS delay (tRCD)
20ns
14
30
Minimum RAS Pulse width (tRAS)
50ns
32
31
Module Bank Density
128MB
20
32
Address and Command Setup Time Before Clock
2.0ns
20
33
Address and Command Hold Time After Clock
1.0ns
10
34
Data Input Setup Time Before Clock
2.0ns
20
35
Data Input Hold Time After Clock
36 - 61 Reserved
62
SPD Revision
63
Checksum for bytes 0 - 62
Module Manufacturing Location
10
00
1.2A
12
Checksum Data
cc
64 - 71 Manufacturers’ JEDEC ID Code
72
1.0ns
Undefined
Notes
2
IBM
A400000000000000
Toronto, Canada
91
Vimercate, Italy
53
32M x 64,
31334E33323634344A43rr
ASCII ‘13N32644JC”R”-260T’
-260
2D323630542020
73 - 90 Module Part Number
32M x 64,
31334E33323634344A43rr
ASCII ‘13N32644JC”R”-360T’
-360
2D333630542020
32M x 72,
31334E33323733344A43rr
ASCII ‘13N32734JC”R”-260T’
-260
2D323630542020
3, 4
32M x 72,
31334E33323733344A43rr
ASCII ‘13N32734JC”R”-360T’
-360
2D333630542020
91 - 92 Module Revision Code
“R” plus ASCII blank
rr20
3, 4
Year/Week Code
yyww
5, 6
Serial Number
ssssssss
7
Undefined
00
100 MHz
64
-260
CK0, CK1, CK2, CK3, CL3,
CL2, concurrent AP
F7
-360
CK0, CK1, CK2, CK3, CL3,
concurrent AP
F5
Undefined
00
93 - 94 Module Manufacturing Date
95 - 98 Module Serial Number
99 - 125 Reserved
126
Module Supports this Clock Frequency
127
Attributes for Clock Frequency defined in
byte 126
128 - 255 Open for Customer Use
1.
2.
3.
4.
5.
6.
7.
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) ➔ 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) ➔ 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Absolute Maximum Ratings
Symbol
Parameter
VDD
Power Supply Voltage
VIN
Input Voltage
VOUT
TA
TSTG
PD
IOUT
Rating
Units Notes
-0.3 to +4.6
SDRAM Devices
-0.3 to VDD+0.3
Serial PD Device
-0.3 to +6.5
SDRAM Devices
-0.3 to VDD+3.3
Serial PD Device
-0.3 to +6.5
Output Voltage
Operating Temperature (ambient)
Storage Temperature
V
1
0 to +70
°C
1
-55 to +125
°C
1
W
1
mA
1
x64
6.5
x72
7.3
Power Dissipation
Short Circuit Output Current
50
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
(TA= 0 to 70˚C)
Rating
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.0
—
VDD + 0.3
V
1, 2
VIL
Input Low Voltage
-0.3
—
0.8
V
1, 3
1. All voltages referenced to VSS.
2. VIH(max) = VDD + 1.2V for pulse width ≤ 5ns.
3. VIL(min) = VDD - 1.2V for pulse width ≤ 5ns.
Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V)
Organization
Symbol
Parameter
Units
x64 Max.
x72 Max.
CI1
Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, RAS, CAS, WE)
104
112
pF
CI2
Input Capacitance (CKE0 - CKE1)
54
58
pF
CI3
Input Capacitance (S0 - S3)
30
33
pF
CI4
Input Capacitance (CK0 - CK3)
40
40
pF
CI5
Input Capacitance (DQMB0 - DQMB7)
17
21
pF
CI6
Input Capacitance (SA0 - SA2, SCL, WP)
9
9
pF
CIO1
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
17
17
pF
CIO2
Input/Output Capacitance (SDA)
11
11
pF
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 18
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
DC Output Load Circuit
3.3 V
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
870Ω
Output Characteristics
(TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
x64
Symbol
II(L)
Parameter
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins
Not Under Test = 0V
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDD)
x72
Min.
Max.
Min.
Max.
RAS, CAS, WE,
A0-A9, A10/AP, A11, BA0, BA1
-80
+80
-90
+90
CK0, CK1
-20
+20
-25
+25
CK2, CK3
-20
+20
-20
+20
CKE0, CKE1
-40
+40
-45
+45
S0, S1
-20
+20
-25
+25
S2, S3
-20
+20
-20
+20
DQMB1, 5
-10
+10
-15
+15
DQMB0, 2, 3, 4, 5, 6, 7
-10
+10
-10
+10
DQ0 - 63
-10
+10
-10
+10
CB0 - 7
0
0
-10
+10
SA0, SA1, SA2, SCL, SDA
-10
+10
-10
+10
WP
-10
+50
-10
+50
DQ0 - 63
-10
+10
-10
+10
CB0 - 7
0
0
-10
+10
SDA
-10
+10
-10
+10
-
2.4
-
VOH
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
2.4
VOL
Output Level (LVTTL)
Output “L” Level Voltage (IOUT = +2.0mA)
-
Units Notes
µA
µA
V
0.4
-
1
0.4
1. See DC output load circuit.
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents
Parameter
Operating Current
tRC = tRC(min), tCK = min
Active-Precharge command cycling
without Burst operation
Symbol
(TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Test Condition
Speed/Organization
-260, -360/x64
-260, -360/x72
Units
Notes
ICC1
1 bank operation
960
1080
mA
1, 3, 4
ICC2P
CKE0, CKE1 ≤ VIL(max), tCK =
min,
S0 - S3 =VIH(min)
16
18
mA
2
ICC2PS
CKE0, CKE1 ≤ VIL(max), tCK =
Infinity,
S0 - S3 =VIH(min)
16
18
mA
2
ICC2N
CKE0, CKE1 ≥ VIH(min), tCK =
min,
S0 - S3 =VIH (min)
560
630
mA
2, 5
CKE0, CKE1 ≥ VIH(min), tCK =
ICC2NS Infinity,
S0 - S3 =VIH (min)
160
180
mA
2, 6
ICC3N
CKE0, CKE1 ≥ VIH(min), tCK =
min,
S0 - S3 =VIH (min)
640
720
mA
2, 5
ICC3P
CKE0, CKE1 ≤ VIL(max), tCK =
min,
S0 - S3 =VIH (min)
(Power Down Mode)
160
180
mA
2, 7
Burst Operating Current
ICC4
tCK = min,
Read/ Write command cycling,
multiple banks active,
gapless data, BL = 4
1040
1170
mA
1, 4, 8
Auto (CBR) Refresh Current
ICC5
tCK = min,
CBR command cycling
1800
2025
mA
1
Self Refresh Current
ICC6
CKE0, CKE1 ≤ 0.2V
32
36
mA
2
Serial PD Device Standby Current
ISB
VIN = GND or VDD
30
30
µA
9
SCL Clock Frequency =
100KHz
1
1
mA
10
Precharge Standby Current in Power
Down Mode
Precharge Standby Current in NonPower Down Mode
No Operating Current
(Active state: 4 bank)
Serial PD Device Active Power Supply Current
ICCA
1. The specified values are for one DIMM bank in the specified mode, and the other DIMM bank in Active Standby (ICC3N).
2. The specified values are for both DIMM banks operating in the specified mode.
3. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.
Input signals are changed up to three times during tRC(min).
4. The specified values are obtained with the output open.
5. Input signals are changed once during three clock cycles.
6. Input signals are stable.
7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ).
8. Input signals are changed once during tCK(min).
9. VDD = 3.3V.
10. As follows:
• Input pulse levels VDD x 0.1 to VDD x 0.9
• Input and output timing levels VDD x 0.5
• Output load 1 TTL gate and CL=100pF
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 18
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQMB0-7 and CKE0-CKE1 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles
before or after the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
4. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point
5. AC measurements assume tT=1.2 ns.
AC Characteristics Diagrams
tCKH
Clock
VIH
1.4V
VIL
tCKL
tSETUP
tT
tHOLD
Output
Zo = 50Ω
Input
50pF
1.4V
AC Output Load Circuit
tAC
tOH
tLZ
Output
09K3540.F38351
8/99
1.4V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Clock and Clock Enable Parameters
-260
Symbol
-360
Parameter
Units
Min.
Max.
Min.
Max.
Notes
tCK3
Clock Cycle Time, CAS Latency = 3
10
1000
10
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
10
1000
15
1000
ns
1
tAC3 (A)
Clock Access Time, CAS Latency = 3
—
—
—
—
ns
2
tAC2 (A)
Clock Access Time, CAS Latency = 2
—
—
—
—
ns
2
tAC3 (B)
Clock Access Time, CAS Latency = 3
—
6
—
6
ns
3
tAC2 (B)
Clock Access Time, CAS Latency = 2
—
6
—
9
ns
3
tCKH
Clock High Pulse Width
3
—
3
—
ns
4
tCKL
Clock Low Pulse Width
3
—
3
—
ns
4
tCES
Clock Enable Set-up Time
2
—
2
—
ns
tCEH
Clock Enable Hold Time
1
—
1
—
ns
1.
2.
3.
4.
tSB
Power down mode Entry Time
0
10
0
10
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
ns
For -360 sort, 66Mhz clock: CAS Latency = 2.
Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 4, 5 and load circuit A.
Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 6, 7 and load circuit B.
tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse
width of CLK measured from the negative edge to the positive edge referenced to VIL (max).
Common Parameters
-260
Symbol
-360
Parameter
Units
Min.
Max.
Min.
Max.
Notes
tCS
Command Setup Time
2
—
2
—
ns
tCH
Command Hold Time
1
—
1
—
ns
tAS
Address and Bank Select Set-up Time
2
—
2
—
ns
tAH
Address and Bank Select Hold Time
1
—
1
—
ns
tRCD
RAS to CAS Delay
20
—
20
—
ns
1
tRC
Bank Cycle Time
70
—
70
—
ns
1
tRAS
Active Command Period
50
100000
50
100000
ns
1
tRP
Precharge Time
20
—
20
—
ns
1
tRRD
Bank to Bank Delay Time
20
—
20
—
ns
1
tCCD
CAS to CAS Delay Time
1
—
1
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 18
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Mode Register Set Cycle
Symbol
-260
Parameter
tRSC
-360
Min.
Max.
Min.
Max.
2
—
2
—
Mode Register Set Cycle Time
Units
Notes
CLK
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
Symbol
Parameter
-260
-360
Units
Min.
Max.
Min.
Max.
2.5
—
2.5
—
ns
Notes
tOH
Data Out Hold Time
tLZ
Data Out to Low Impedance Time
0
—
0
—
ns
tHZ3
Data Out to High Impedance Time
3
6
3
6
ns
1
tHZ2
Data Out to High Impedance Time
3
6
3
8
ns
1
tDQZ
DQM Data Out Disable Latency
2
—
2
—
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
-260
-360
Min.
Max.
Min.
Max.
64
—
64
tREF
Refresh Period
—
tSREX
Self Refresh Exit Time
10
10
Units
Notes
ms
1
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
Parameter
-260
-360
Min.
Max.
Min.
Max.
—
tDS
Data In Set-up Time
2
—
2
Units
ns
tDH
Data In Hold Time
1
—
1
—
ns
tDPL
Data input to Precharge
10
—
10
—
ns
tDQW
DQM Write Mask Latency
0
-
0
-
CLK
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Presence Detect Read and Write Cycle
Symbol
Max
Unit
SCL Clock Frequency
100
kHz
TI
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
µs
tBUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
µs
Start Condition Hold Time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4.0
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
µs
tHD:DAT
Data in Hold Time
0
µs
tSU:DAT
Data in Setup Time
250
ns
fSCL
tHD:STA
Parameter
Min
tr
SDA and SCL Rise Time
1
µs
tf
SDA and SCL Fall Time
300
ns
Stop Condition Setup Time
4.7
µs
tDH
Data Out Hold Time
300
ns
tWR
Write Cycle Time
tSU:STO
15
ms
Notes
1
1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle.
During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 18
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Functional Description and Timing Diagrams
Refer to the IBM 128Mb Synchronous DRAM Die Revision A data sheet, document 33L8019, for the functional description and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 18
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Layout Drawing
133.35
5.25
131.35
5.171
127.35
5.014
*
1780
.700
(2) 0
3.18
.1255
34.925
1.375
(2x) 4.00
.157
Front
3.0
.118
6.35
.250
1.27 Pitch
.050
42.18
1.661
1.00 Width
.039
66.68
2.63
See Detail A
* Note: on x72 Module Only
Side
Detail A
SCALE 4/1
4.01
.158 max.
2.0
.078
3.0
.118
5.95
.234 min.
R 1.00
.0393
_ 0.10
1.27 +
_ .004
.050 +
Note: All dimensions are typical unless otherwise stated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 18
Millimeters
Inches
09K3540.F38351
8/99
IBM13N32644JCA
IBM13N32734JCA
32M x 64/72 Two-Bank Unbuffered SDRAM Module
Revision Log
Rev
Contents of Modification
7/99
Initial Release.
8/99
Removed Preliminary
09K3540.F38351
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 18

 International Business Machines Corp.1999
Copyright
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.