NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM NT56V6650C0T (16Mx4) 64Mb Synchronous DRAM Data Sheet REV 1.1 June, 2000 1 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Revision Log Rev Date Version Content of Modification Sep / 1999 1.0 1 st Revision June / 2000 1.1 Added speed grade –75B (PC133@CL3 & PC100@CL2) to following items as : 1. Product Family 2. DC currents 3. AC Timing Parameters REV 1.1 June, 2000 2 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Contents Revision Log ............................................................................................................................................................................................. 02 Table of Contents .................................................................................................................................................................................... 03 Description................................................................................................................................................................................................ 05 Features.....................................................................................................................................................................................................05 Product Family ........................................................................................................................................................................................05 Pin Assignment ........................................................................................................................................................................................05 Pin Description.........................................................................................................................................................................................07 Functional Block Diagram .....................................................................................................................................................................08 Ordering Information..............................................................................................................................................................................09 DC Characteristics.................................................................................................................................................................................. 10 Absolute Maximum Ratings ............................................................................................................................................................. 10 Recommended DC Operating Conditions ........................................................................................................................................ 10 Capacitance .................................................................................................................................................................................... 10 DC Electrical Characteristics ..........................................................................................................................................................11 DC Output Load Circuit ...................................................................................................................................................................11 Operating, Standby, and Refresh Currents ....................................................................................................................................11 AC Characteristics.................................................................................................................................................................................. 13 AC Output Load Circuits ..................................................................................................................................................................13 AC Timing Parameters........................................................................................................................................................................... 14 Clock and Clock Enable Parameters ...............................................................................................................................................14 Common Parameters ....................................................................................................................................................................... 14 Mode Register Set Cycle ................................................................................................................................................................ 14 Read Cycle ..................................................................................................................................................................................... 15 Refresh Cycle .................................................................................................................................................................................15 Write Cycle ..................................................................................................................................................................................... 15 Clock Frequency and Latency ........................................................................................................................................................15 Command Truth Table............................................................................................................................................................................ 17 DEVICE OPERATIONS..............................................................................................................................................................................23 Power On and Initialization ............................................................................................................................................................. 23 Programming the Mode Register ..................................................................................................................................................... 23 Mode Register Definition ................................................................................................................................................................. 23 Burst Mode Operation .....................................................................................................................................................................25 Burst Length and Sequence ...........................................................................................................................................................25 Bank Activate Command ................................................................................................................................................................. 26 Bank Select ..................................................................................................................................................................................... 26 Read and Write Access Modes ...................................................................................................................................................... 27 Burst Read Command .....................................................................................................................................................................27 Read Interrupted by a Read ............................................................................................................................................................ 28 Read Interrupted by a Write ............................................................................................................................................................ 29 Burst Write Command .....................................................................................................................................................................29 Write Interrupted by a Write ............................................................................................................................................................ 30 Write Interrupted by a Read ............................................................................................................................................................ 30 Burst Stop Command ......................................................................................................................................................................31 Auto-Precharge Operation ............................................................................................................................................................. 32 Precharge Command ......................................................................................................................................................................36 Bank Selection for Precharge by Address Bits .............................................................................................................................. 36 Precharge Termination ....................................................................................................................................................................38 Automatic Refresh Command .........................................................................................................................................................39 Self Refresh Command ...................................................................................................................................................................39 Power Down Mode ......................................................................................................................................................................... 40 Data Mask .......................................................................................................................................................................................40 No Operation Command ..................................................................................................................................................................41 REV 1.1 June, 2000 3 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Deselect Command ......................................................................................................................................................................... 41 Clock Suspend Mode ......................................................................................................................................................................42 Package Dimension................................................................................................................................................................................43 REV 1.1 June, 2000 4 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Description The NT56V6650C0T is four-bank Synchronous DRAMs organized as 4Mbit x 4 I/O x 4 Bank . The devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NANYA advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. /RAS, /CAS, /WE, and /CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional /RAS /CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (A12, A13) are strobed with /RAS. Ten column addresses (A0-A9) plus bank select addresses and A10 are strobed with /CAS. Prior to any access operation, the /CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A9 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, /CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR), Self Refresh, and Low Power operation are supported. Feature • • • • • • • • • • • • • • • JEDEC standard 3.3V± 0.3V Power Supply LVTTL compatible inputs and outputs Four Banks controlled by Bank Selects(A12/A13) Single Pulsed /RAS Interface Fully Synchronous to Positive Clock Edge MRS cycle with address key programmability for : - CAS Latency ( 2, 3 ) - Burst Length ( 1, 2, 4, 8 & Full-page ) - Burst Type ( Sequential or Interleave ) Multiple Burst Read with Single Write Option Automatic and Controlled Precharge Command Data Mask for Read/Write control Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode Standard Power operation 4096 refresh cycles/64ms Random Column Address every CLK (1-N Rule) Package:54-pin 400 mil TSOP-Type II Product Family Part NO. Organization NT56V6650C0T-7 Speed ( MHz@CL-tRP-tRCD) 143 MHz @ 3-3-3 - 133 MHz @ 3-3-3 100 MHz @ 2-2-2 133 MHz @ 3-3-3 - NT56V6650C0T-8A 125 MHz @ 3-3-3 100MHZ @ 2-2-2 NT56V6650C0T-8B 125 MHz @ 3-3-3 100MHz @ 3-2-2 NT56V6650C0T-75B NT56V6650C0T-75 REV 1.1 June, 2000 16M x 4 Interface Package LVTTL 54pin TSOP II 5 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Pin Assignment ( Top View ) 16M x 4 V DD 1 54 Vss NC 2 53 NC V DDQ 3 52 Vss Q NC 4 51 NC DQ0 5 50 DQ3 V SSQ 6 49 V DDQ NC 7 48 NC NC 8 47 NC V DDQ 9 46 V SSQ NC 10 45 NC DQ1 11 44 DQ2 V SSQ 12 43 V DDQ NC 13 42 NC V DD 14 41 V SS NC 15 40 NC WE 16 39 DQM CAS 17 38 CLK RAS 18 37 CKE CS 19 36 NC A13/BS0 20 35 A11 A12/BS1 21 34 A9 A10/AP 22 33 A8 A0 23 32 A7 A1 24 31 A6 A2 25 30 A5 A3 26 29 A4 V DD 27 28 V SS 54-pin Plastic TSOP-II 400 mil REV 1.1 June, 2000 6 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Pin Description CLK CKE /CS (/CS0, /CS1 ) /RAS /CAS /WE Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable DQ0-DQ15 DQM, LDQM, UDQM VDD VSS VDDQ VSSQ Data Input/Output Data Mask Power (+3.3V) Ground Power for DQs (+3.3V) Ground for DQs BS1, BS0 (A12, A13) A0-A11 Bank Select Address Inputs NC -- No Connection -- Input / Output Functional Description Symbol Type Polarity Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. /CS ( /CS0 , /CS1 for stacked devices) enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, /CAS, /RAS, and /WE define the operation to be executed by the SDRAM. CLK Input Positive Edge CKE Input Active High /CS, /CS0, /CS1 Input Active Low /RAS, /CAS /WE Input Active Low BS1, BS0 (A12, A13) Input -- Selects which bank is to be active. A0 - A11 Input -- During a Bank Activate command cycle, A0-A11 defines the row address (RA0RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0CA9) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0-DQ3 InputOutput -- Data Input/Output pins operate in the same manner as on conventional DRAMs DQM Input Active High VDD, VSS Supply -- VDDQ, VSSQ Supply -- REV 1.1 June, 2000 The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. 7 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Functional Block Diagram CLK CLK Buffer Column Decoder Cell Array Memory Bank 0 Column Decoder Row Decoder CKE Buffer Row Decoder CKE Sense Amplifiers Cell Array Memory Bank 1 Sense Amplifiers A0 A1 A2 A3 A8 A9 Mode Register A11 A12 A13 A10 Data Input / Output Buffers A7 Data Control Circuitry A6 DQ0 Control Signal Generator A5 Address Buffers ( 14 ) A4 DQX CAS WE Cell Array Memory Bank 2 Sense Amplifiers Column Decoder Row Decoder Column Decoder Row Decoder RAS Command Decoder CS Column Address Counter Refresh Counter DQM Cell Array Memory Bank 3 Sense Amplifiers Cell Array , per bank , for 4Mb x 4 DQ : 4096 Row x 1024Col x 4DQ (DQ0-DQ3 ). REV 1.1 June, 2000 8 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Part Number Guide NT 56 V 6 6 50 C 0 T - XX Speed*(10) NANYA Memory*(1) Device*(2) Package*(9) Voltage*(3) Interface*(8) Density*(4) Revision*(7) Refresh Time*(5) Configration*(6) (1) NANYA Memory (6) Configuration 10 - - - - - - - - 4 bank, x 8 20 - - - - - - - - 4 bank, x 16 50 - - - - - - - - 4 bank, x 4 (2) Device 56 - - - - - - - - SDRAM (7) Revision A - - - - - - - - 1st version B - - - - - - - - 2nd version C - - - - - - - - 3rd version D - - - - - - - - 4th version (3) Voltage (8) Interface V - - - - - - - - 3.3V 0 - - - - - - - - LVTTL 1 - - - - - - - - SSTL (4) Density (9) Package 1 - - - - - - - - 16M T - - - - - - - -TSOP II 6 - - - - - - - - 64M 2 - - - - - - - - 128M F - - - - - - - -TQFP Q - - - - - - - -QFP (5) Refresh Time 7 - - - - - - - - 2K/32ms (10) Speed 7 - - - - - - - -143MHz 6 - - - - - - - - 4K/64ms 75 - - - - - - -133MHz 8 - - - - - - - -125MHz 10 - - - - - - -100MHz REV 1.1 June, 2000 9 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM DC Characteristics Absolute Maximum Ratings Symbol V DD V DDQ V IN Parameter Power Supply Voltage Power Supply Voltage for Output Input Voltage Rating -0.3 to +4.6 -0.3 to +4.6 -0.3 to V DD+0.3 Units V V V Notes 1 1 1 V OUT Output Voltage -0.3 to V DD+0.3 V TA Operating Temperature (ambient) 0 to +70 °C TSTG Storage Temperature -55 to +125 °C PD Power Dissipation 1.0 W IOUT Short Circuit Output Current 50 mA 1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1 1 1 1 1 Recommended DC Operating Conditions (TA = 0 to 70 °C ) Symbol V DD Parameter Power Voltage V DDQ Power Voltage for Output V IH Input High Voltage V IL Input Low Voltage 1. All voltages referenced to VSS and V SSQ. 2. V IH (max) = V DD / V DDQ + 1.2V for pulse width ≤ 5ns 3. VIL (min) = V SS /V SSQ - 1.2V for pulse width ≤ 5ns . Min. 3.0 Rating Typ. 3.3 Max. 3.6 3.0 2.0 -0.3 3.3 - 3.6 V DD + 0.3 0.8 Units Notes V 1 V V V 1 1,2 1,3 Capacitance (TA = 25 °C, f = 1MHz, VDD = 3.3V ± 0.3V) Symbol CI CO Parameter Input Capacitance (A0-A11, BS0, BS1, /CS, /RAS, /CAS, /WE, CKE, DQM) Min. Typ. Max. 2.5 3.0 3.8 Input Capacitance (CLK) 2.5 2.8 3.5 Output Capacitance (DQ0 – DQ15) 4.0 4.5 6.5 Units Notes pF 1 1. Multiply given planar values by 2 for 2-High stacked device except /CS. REV 1.1 June, 2000 10 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM DC Electrical Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V) Symbol Parameter Input Leakage Current, any input II(L) (0.0V ≤ V IN ≤ V DD), All Other Pins Not Under Test = 0V Output Leakage Current IO(L) (DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ) Output Level (LVTTL ) VOH Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL ) VOL Output "L" Level Voltage (IOUT = +2.0mA) 1. Multiply given planar values by 2 for 2-High stacked device. Min. Max. Units Notes -1 +1 uA 1 -1 +1 uA 1 2.4 - V - - 0.4 V - DC Output Load Circuit 3.3 V 1200 ohms V OH(DC) = 2.4V,I OH= -2mA Output V OL (DC) = 0.4V,I OL = -2mA 50 pF REV 1.1 June, 2000 870 ohms 11 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Operating, Standby, and Refresh Currents (VDD =3.3V ± 10% , TA =0°C to 70°C) Parameter Symbol Operating current ICC1 Precharge standby current in power-down mode ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS No Operating current ( Active state : 4 bank) Operating current ( Burst mode ) Auto(CBR) refresh current Self refresh current 1. 2. 3. 4. 5. 6. 7. ICC3P ICC3N ICC4 ICC5 ICC6 Version Test condition 1 bank operation , tRC = tRC(mim), tCK = min Active-Precharge Command cycling without burst operation CKE <= VIL(max), tCK = min, /CS = V IH(min), CKE <= VIL(max), tCK =oo, /CS = V IH(min) CKE >= VIH(min), /CS = V IH(min), tCK = min Unit Note mA 1,2,3 2 mA 1 2 mA 1 mA 1 -7 - 75(B) - 8B - 8A 75 75 70 70 35 35 25 25 CKE >= VIH(min), tCK =oo 5 mA 1,5 CKE<=VIL(max), tCK =min 3 mA 1,7 CKE >=VIH(min), /CS = V IH(min), tCK =min t CK =min , Read/ Write command cycling, Multiple banks active, gapless data, BL=4 t RC = tRC(min) ; tCK =min CBR command cycling CKE <= 0.2V 40 40 30 30 mA 1,5 120 120 90 90 mA 1,6 145 145 140 140 mA 1,3,4 mA 1 1 Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the other deck. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during t RC(min). The specified values are obtained with the output open. Input signals are changed once during tCK(min). Input signals are changed once during three clock cycles. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). Input signals are stable. REV 1.1 June, 2000 12 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM AC Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V) 1. 2. 3. 4. 5. 6. 7. An initial pause of 200ms,with DQM and CKE held high , is required after power-up. A precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation . The Transition time is measured between V IH and V IL (or between VIL and V IH). In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and V IL (or between V IL and V IH) in a monotonic manner. Load Circuit A : AC timing tests have V IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point Load Circuit A : AC measurement s assume t T = 1.0ns. Load Circuit B : AC timing tests have V IL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point Load Circuit B : AC measurements assume tT = 1.2ns. AC Output Load Circuits tT tCKL Clock tSETUP tCKH V IH 1.4V V IL Vtt = 1.4V 50 ohm Output Zo = 50 ohm 50 pF tHOLD AC Output Load Circuit ( A ) Input 1.4V tAC Output tOH Zo = 50 ohm tLZ Output 1.4V 50 pF AC Output Load Circuit ( B ) REV 1.1 June, 2000 13 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM AC Timing Parameters Clock and Clock Enable Parameters Symbol Parameter Min. -7 Max. - 75B Min. Max. - 75 Min. Max. - 8B Min. Max. - 8A Min. Max. Unit Note tCK3 Clock Cycle Time, /CAS Latency = 3 7 - 7.5 - 7.5 - 8 - 8 - ns tCK2 Clock Cycle Time, /CAS Latency = 2 - - 10 - - - 10 - 12 - ns tAC3(A) Clock Access Time, /CAS Latency = 3 - 6 - - - - - - - - ns 1 tAC2(A) Clock Access Time, /CAS Latency = 2 - - - - - - - - - - ns 1 tAC3(B) Clock Access Time, /CAS Laten cy = 3 - - - 5.4 - 5.4 - 6 - 6 ns 2 tAC2(B) Clock Access Time, /CAS Latency = 2 - - 6 - - - - 6 - 6 ns 2 tCKH tCKL tCES Clock High Pulse Width Clock Low Pulse Width Clock Enable Set-up Time 3 3 2 - 2.5 2.5 1.5 - 2.5 2.5 1.5 - 3 3 2 - 3 3 2 - ns ns ns tCEH Clock Enable Hold Time Power down mode Entry Time Transition Time (Rise and Fall) 1 - 0.8 - 0.8 - 1 - 1 - ns 0 7 0 7.5 0 7.5 0 10 0 12 ns 0.5 10 0.5 10 0.5 10 0.5 10 0.5 10 ns tSB tT 1.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A 2.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B. Common Parameters Symbol Parameter -7 - 75B - 75 - 8B - 8A Unit Min. 2 Max. - Min. 1.5 Max. - Min. 1.5 Max. - Min. 2 Max. - Min. 2 Max. - 1 - 0.8 - 0.8 - 1 - 1 - ns 2 - 1.5 - 1.5 - 2 - 2 - ns Note tCS Command Setup Time tCH 1 - 0.8 - 0.8 - 1 - 1 - ns tRCD Command Hold Time Address and Bank Select Set-up Time Address and Bank Select Hold Time /RAS to /CAS Delay 21 - 20 - 20 - 20 - 20 - ns 1 tRC tRAS tRP Bank Cycle Time Active Command Period Precharge Time 70 49 21 - - - 70 50 20 - - 65 45 20 - - 65 45 20 - 70 50 20 - ns ns ns 1 1 1 tRRD tCCD Bank to Bank Delay Time /CAS to /CAS Delay Time 14 1 - 15 1 - 15 1 - 20 1 - 20 1 - ns CLK 1 tAS tAH ns 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). REV 1.1 June, 2000 14 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Mode Register Set Cycle Symbol tRSC Parameter Mode Register Set Cycle Time Min. 2 -7 Max. - - 75B Min. Max. 2 - - 75 Min. Max. 2 - - 8B Min. Max. 2 - - 8A Min. Max. 2 - Unit Note CLK 1 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Read Cycle Symbol tOH tLZ tHZ3 tHZ2 Parameter Data Out Hold Time Data Out to Low Impedance Time Data Out to High Impedance Time Min. -7 Max. - 75B Min. Max. - 75 Min. Max. - 8B Min. Max. - 8A Min. Max. Unit Note 1 2 2.5 - 2.7 - 2.7 - 2.5 3 - 2.5 3 - ns ns 0 - 0 - 0 - 0 - 0 - ns 3 6 3 5.4 3 5.4 3 6 3 6 ns 3 - - - - - - 3 6 3 8 ns 3 - CLK DQM Data Out Disable tDQZ 2 2 2 2 2 Latency 1.AC Output Load Circuit A. 2.AC Output Load Circuit B. 3.Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Refresh Cycle Symbol tREF tSREX Parameter Refresh Period Self Refresh Exit Time Min. 10 -7 Max. 64 - - 75B Min. Max. - 75 Min. Max. - 8B Min. Max. - 8A Min. Max. Unit 10 10 10 10 ms ns 64 - 64 - 64 - 64 - Note Write Cycle Symbol Parameter Min. -7 Max. - 75B Min. Max. - 75 Min. Max. - 8B Min. Max. - 8A Min. Max. Unit tDS tDH Data In Set -up Time Data In Hold Time 2 1 - 1.5 0.8 - 1.5 0.8 - 2 1 - 2 1 - ns ns tDPL Data input to Precharge Data In to Active Delay /CAS Latency = 3 Data In to Active Delay /CAS Latency = 2 DQM Write Mask Latency 14 - 15 - 15 - 15 - 15 - ns 5 - 5 - 5 - 5 - 5 - CLK - - - - - - 4 - 3 - CLK 0 - 0 - 0 - 0 - 0 - ns tDAL3 tDAL2 tDQW REV 1.1 June, 2000 Note 15 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Clock Frequency and Latency Symbol Parameter -7 - 75B - 75 - 8B - 8A Units tCK tCK tAA tRP Clock Frequency Clock Cycle Time /CAS Latency Precharge Time 143 7 3 3 133 7.5 3 3 100 10 2 2 133 7.5 3 3 125 8 3 3 100 10 2 2 125 8 3 3 83 12 2 2 MHz ns CLK CLK tRCD tRC tRAS tDPL tDAL tRRD /RAS to /CAS Delay Bank Cycle Time Minimum Bank Active Time Data In to Precharge Data In to Active/Refresh Bank to Bank Delay Time 3 10 7 2 5 2 3 9 6 2 5 2 2 7 5 2 4 2 3 9 6 2 5 2 3 9 6 2 5 2 2 7 5 2 4 2 3 9 6 2 5 2 2 6 4 2 4 2 CLK CLK CLK CLK CLK CLK tCCD tWL tDQW tDQZ tCSL /CAS to /CAS Delay Time Write Latency DQM Write Mask Latency DQM Data Disable Latency Clock Suspend Latency 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 1 0 0 2 1 CLK CLK CLK CLK CLK REV 1.1 June, 2000 16 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Command Truth Table Function Mode Register Set Auto (CBR) Refresh Entry Self Refresh Exit Self Refresh Single Bank Precharge Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge Burst Termination No Operation Device Deselect Clock Suspend Mode Entry Clock Suspend Mode Exit Data Write/Output Enable Data Mask/Output Disable Power Down Mode Entry Power Down Mode Exit 1 2. 3. 4. 5. 6. 7. 8. Device State CKE Previous Current Cycle Cycle /CS /RAS /CAS /WE DQM A12, A13 A10 A11, A0-A9 Notes Idle H X L L L L X Idle H H L L L H X X X X Idle H L L L L H X X X X L H H L X H X H X H X X X X H X L L H L X BS L X H X L L H L X X H X H H X X L L L H H L H L X X BS BS Row address L Column 2 2 Active H X L H L L X BS H Column 2 Active H X L H L H X BS L Column 2 Active H X L H L H X BS H Column 2 Active H X L H H L X X X X 3,8 Any H X L H H H X X X X Any H X H X X X X X X X Active H L X X X X X X X X Idle(SelfRefresh) See Current State Table See Current State Table Idle Active OP Code 2 4 Active L H X X X X X X X X Active H X X X X X L X X X Active H X X X X X H X X X Idle/Active H L X H X X X 6,7 H X H X X L X H X X Any (Power Down) H L H L H H H X X X X 6,7 5 All of the SDRAM operations are defined by states of /CS, /WE, /RAS, /CAS, and DQM at the positive rising edge of the clock. Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the Current State Truth Table. Bank Select(BS0,BS1):BS0,BS1=0,0 selects bank0; BS0,BS1=0,1 selects bank1; BS0,BS1=1,0 selects bank2; BS0,BS1= 1,1 selects bank 3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the /CAS latency. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high data clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal. REV 1.1 June, 2000 17 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Clock Enable (CKE) Truth Table Current State Self Fresh Power Down All Banks Idle Any State other than listed above 1. 2. 3. 4. 5. Previous Cycle H CKE Current Cycle X Command X A12, A13 X A11– A10 X /CS /RAS /CAS /WE X X X L H H X X X X X L H L H H H X X L L L L H H H H L X L L L X X H H L X X H L X X X L X X X X X X X X X X X X X X L H H X X X X X L H L X X X X X L L X X X X X X H H H H H H H H H H L H H H H H L L L L L X H L L L L H L L L L X X H L L L X H L L L X X X H L L X X H L L X X X X H L X X X H L X H H X X X X X X H L X X X X X X L H X X X X X X X X OP Code X X OP Code X X Action Notes INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 1 2 2 2 2 2 1 2 2 3 3 3 4 3 3 3 4 4 5 L L X X X X X X For the given Current State CKE must be low in the previous cycle. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high . The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. The Precharge Power Down Mode,the Self Refresh Mode,and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. REV 1.1 June, 2000 18 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 1 of 3)(See note 1) Current State Idle Row Active Read Write Command A12, A11-A0 A13 OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X BS X Row BS Address Description Action Mode Register Set Auto or Self Refresh Precharge 2 2,3 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge Bank Active ILLEGAL 4 /CS /RAS /CAS /WE L L L L L L L L H L H L L L H H L L L L H L L L H H H H X L L L L L H H X L L H L H L H X L H L L L H H L H L L BS Column Write L H L H BS Column Read L L H L L H H X L L H H X L L L H X L H X X X X X X OP Code X X Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh L L H L BS X Precharge L L H H BS Row Address L H L L L H L L L Bank Active Bank Active L L BS Column Write H L H BS Column Read H H X L L H H X L L L H X L H X X X X X X OP Code X X Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh L H L BS X Precharge Bank Active L L H H BS Row Address L H L L BS Column Write L H L H BS Column Read L L H H H X H H X L H X X X X X X X Burst Termination No Operation Device Deselect Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst Notes 4 4 5 6 7,8 7,8 4 8,9 8,9 4 8,9 8,9 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (t RCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 19 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 2 of 3)(See note 1) Current State /CS /RAS /CAS /WE L L L L L L L L H L H L Read with Auto Precharge L L H H L L L L H L L L H H H H X L L L L L H H X L L H L H L H X L H L Write with Auto Precharge L L H H L L L L H L L H H H H X L L L L H H X L L L H L H X L H L L H L Precharging Row Activating Command A12, A11-A0 A13 OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X BS X Action Description Notes Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL 4 Bank Active ILLEGAL 4 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL 4 4 Bank Active ILLEGAL 4 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP 4 4 Bank Active ILLEGAL 4 Write Read 4 4 Precharge L L H H BS L L H H L L L H BS BS Row Address Column Column L H H L X X Burst Termination L H H H X X No Operation H X X X X X Device Deselect L L L L L L L L H L H L X BS L L H H L L H H L L L H L H 4 Mode Register Set Auto or Self Refresh Precharge Bank Active ILLEGAL 4,10 L H OP Code X X Row BS Address BS Column BS Column ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL Write Read 4 4 H L X X Burst Termination H H H X X No Operation X X X X X Device Deselect ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 20 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 3of 3)(See note 1) Current State Write Recovering Write Recovering With Auto Precharge Refreshing Mode Register Accessing Command A12, A13 /CS /RAS /CAS /WE A11-A0 L L L L L L L H X X L L H L BS L L H H BS X Row Address OP Code Mode Register Set Auto or Self Refresh Precharge Bank Active L H L L BS Column Write L H L H BS Column Read L H H L X X Burst Termination L H H H X X No Operation H X X X X X Device Deselect L L L L L L L H X X L L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X X L H H H X X No Operation H X X X X X Device Deselect L L L L L L L H X X L L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X L H H H H X X X L L L L L L L H X X L L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X X L H H X H X H X X X X X REV 1.1 June, 2000 OP Code OP Code Action Description Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL 4 ILLEGAL 4 Start Write; Determine if Auto Precharge Start Write; Determine if Auto Precharge No Operation; Row Active after t DPL No Operation;Row Active after tDPL No Operation; Row Active after t DPL 9 9 ILLEGAL ILLEGAL ILLEGAL 4 Bank Active ILLEGAL 4 Write Read Burst Termination ILLEGAL ILLEGAL No Operation; Precharge Active after t DPL No Operation; Precharge Active after t DPL No Operation; Precharge Active after t DPL 4,9 4,9 Mode Regis ter Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL X Write Read Burst Termination X X No Operation X X Device Deselect ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC OP Code Notes Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL 21 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 22 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM DEVICE OPERATIONS Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, /CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re -executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of /RAS, /CAS, /CS, and /WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. /CAS Latency The /CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The /CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the /CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the /CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate /CAS latency has been sele cted it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section. REV 1.1 June, 2000 23 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Mode Register Definition Mode Register set: (Programming mode) A13 A12 A11 A10 A9 A8 A7 A6 Operation Mode CAS Latency M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 A5 A4 CAS Latency A3 A2 BT M3 0 1 A0 Burst Length Burst Type Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A1 Address bus (Ax) Mode Register (Mx) Burst Length Type Sequential Interleave M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 Reserved Reserved Reserved Full Page BT=1 1 2 4 8 Reserved Reserved Reserved Reserved Operation Mode M13 0 0 M12 0 0 M11 0 0 M10 0 0 M9 0 1 M8 0 0 M7 0 0 Mode Normal Multiple Burst with Single Write Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). Three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is al so programmable and is set by address bits A7 - A13. Burst sequence defines the order in which the burst data will be delivered or stored to the SDRAM. The two types of burst sequence supported are sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organi zation: x4, x8, or x16). Full page burst operation is only possible using the sequential burst type. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cyc les are single write operations when this mode is selected. REV 1.1 June, 2000 24 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Length and Sequence Burst Length Starting Bit A0 0 1 2 A1 0 0 1 1 4 8 A2 0 0 0 0 1 1 1 1 A0 0 1 0 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Full Page n n n (Note) Note : Page length is a function of I/O organization and column addressing. X 4 organization (CA0-CA9); Page Length = 1024 bits Interleave Sequential 0-1 1-0 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Not supported Cn, Cn+1,Cn+2….. Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling /RAS signal. The Bank Activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank select address A12 A13 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the /RAS to /CAS delay time (tRCD). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). REV 1.1 June, 2000 25 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Bank Activate Command Cycle CAS Latency = 3, tRCD = 3 T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK Bank A Row Addr. ADDRESS Bank A Col. Addr. Bank B Row Addr. RAS-CAS delay(tRCD) Bank A Activate COMMAND NOP Bank A Row Addr. RAS-RAS delay(tRCD) Write A with Aotu Precharge Bank B Activate NOP Bank A Activate NOP RAS Cycle time (tRC) : "H" or "L" Bank Select The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits BS0 0 0 1 1 BS1 0 1 0 1 Bank Bank 0 Bank 1 Bank 2 Bank 3 Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high and /CAS low at the clock's rising edge after the necessary /RAS to /CAS delay (tRCD). /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high), or a write operation (/WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 150 MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. If the burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge Command is issued. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is refer red to as the 1 -N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary, providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. REV 1.1 June, 2000 26 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Read Command The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the /CAS latency that is set in the Mode Register. Burst Read Operation Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, DQs NOP NOP DOU A0 CAS latency = 3 tCK3, DQs NOP NOP DOU A1 DOU A2 DOU A3 DOU A0 DOU A1 DOU A2 NOP NOP NOP DOU A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the /CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read Burst Length = 4, CAS Latency = 2, 3 T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs REV 1.1 June, 2000 NOP DOU A0 NOP NOP NOP NOP NOP DOU B0 DOU B1 DOU B2 DOU B3 DOU A0 DOU B0 DOU B1 DOU B2 NOP DOU B3 27 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Minimum Read to Write Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ A WRITE A NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP CLK DQM COMMAND NOP : "H" or "L" Non-Minimum Read to Write Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 CLK DQM COMMAND NOP READ A NOP WRITE A CL = 2 : DQM needed to mask first, second bit of READ data. CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CL = 3 : DQM needed to mask first, second bit of READ data. CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 REV 1.1 June, 2000 28 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Write Command The Burst Write command is initiated by having /CS, /CAS, and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no /CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A DQs NOP NOP DOU A0 NOP DOU A1 NOP DOU A2 NOP DOU A3 NOP NOP Don't care The First data elemant and the Write are registered on the same clock edge. Extra data is masked Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP 1 Clk Interval DQs REV 1.1 June, 2000 DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 29 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 WRITE A READ B CAS latency = 2 tCK2, DQs DIN A0 don't care CAS latency = 3 tCK3, DQs DIN A0 don't care T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP DOU B0 don't care NOP NOP NOP DOU B1 DOU B2 DOU B3 DOU B0 DOU B1 DOU B2 NOP DOU B3 Input data must be removed from the DQs at least one clock cycle before the data appears on the outputs to avoid data contention. Input data for the write is masked Non-Minimum Write to Read Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A NOP READ B CAS latency = 2 tCK2, DQs DIN A0 DIN A1 don't care CAS latency = 3 tCK3, DQs DIN A0 DIN A1 don't care NOP NOP NOP DOUT B0 don't care NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 NOP DOUT B3 Input data must be removed from the DQs at least one clock cycle before the data appears on the outputs to avoid data contention. Input data for the write is masked Burst Stop Command Once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation or using a Precharge Command to interrupt a burst cycle and close the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. Use of the Burst Stop Command during other burst length REV 1.1 June, 2000 30 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM operations is illegal. The Burst Stop Command is defined by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock. When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state after a delay which is equal to the /CAS Latency set in the Mod e Register. Termination of a Burst Read Operation Burst Length = Full Page, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP Burst Stop NOP NOP NOP NOP NOP The burst ends after a delay equal to the CAS latency. CAS latency = 2 tCK2, DQs DOUT A0 CAS latency = 3 tCK3, DQs DOUT A1 DOUT A2 DOUT A0 DOUT A1 DOUT A3 DOUT A2 DOUT A3 If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Termination of a Burst Write Operation Burst Length = Full Page, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency=2,3 DQs NOP WRITE A NOP NOP Burst Stop DIN A0 DIN A1 DIN A2 don't care NOP NOP NOP NOP Input data for the Write is masked Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the autoprecharge function. When a Read or a Write Command is given to the SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto -precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (/CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. REV 1.1 June, 2000 31 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge can not be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted that the device will not respond to the Auto-Precharge command if the device is programmed for full page burst read or write cycles, or full page burst read cycles with single write operation. When using the Auto-Precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. Burst Read with Auto-Precharge Burst Length = 1, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP tRP# CL = 2 tCK2, DQs NOP NOP NOP NOP NOP * DOUT A0 * tRP# CL = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge REV 1.1 June, 2000 Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. * 32 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Read with Auto-Precharge Burst Length = 2, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP tRP# CL = 2 tCK2, DQs DOUT A0 NOP NOP NOP NOP * DOUT A1 * tRP# CL = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge DOUT A1 Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. * Burst Read with Auto-Precharge Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP NOP NOP tRP# CL = 2 tCK2, DQs DOUT A0 DOUT A1 DOUT A2 NOP NOP * DOUT A3 * tRP# CL = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge REV 1.1 June, 2000 DOUT A1 DOUT A2 DOUT A3 * Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. 33 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Although a Read Command with auto-precharge cannot be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the interrupting command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP. Burst Read with Auto-Precharge Interrupted by Read Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP READ B NOP NOP tRP# CL = 2 tCK2, DQs DOUT A0 NOP NOP NOP * DOUT A1 DOUT B0 tRP# CL = 3 tCK3, DQs NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 * DOUT A0 DOUT A1 DOUT B3 Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. * If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP WRITE B NOP tRP# CL = 2 tCK2, DQs DOUT A0 DOUT B0 NOP NOP NOP DOUT B3 DOUT B4 * DOUT B1 DOUT B2 DQM Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. * REV 1.1 June, 2000 34 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-precharge can not be reactivated until tDAL, Data -in to Active delay , is satisfied. Burst Write with Auto-Precharge Burst Length = 2, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP DIN A0 DIN A0 NOP NOP DIN A1 * tDAL# CL = 3 tCK3, DQs NOP * tDAL# CL = 2 tCK2, DQs NOP DIN A1 * Bank can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. Similar to the Read Command, a Write Command with auto -precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The precharge function will begin with the new command. The bank may be reactivated after tRP is satisfied. Burst Write with Auto-Precharge Interrupted by Write Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A AutoPrecharge NOP WRITE B NOP NOP DIN A0 DIN A1 DIN B0 NOP NOP NOP * tDAL# CAS latency = 3 tCK3, DQs NOP DIN B1 DIN B2 DIN B3 * Bank can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. REV 1.1 June, 2000 35 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A AutoPrecharge NOP NOP READ B NOP DIN A0 DIN A1 NOP NOP NOP * tDAL# CAS latency = 3 tCK3, DQs NOP DIN A2 DOUT B0 DOUT B1 DOUT B2 * Bank A can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits --A10, A12, and A13--are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 LOW Bank Select BS0, BS1 Precharged Bank(s) Bank defined by BS0, BS1 only HIGH DON'T CARE All Banks For read cycles, the Precharge Command may be applied (/CAS latency - 1) clocks prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Datain to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). REV 1.1 June, 2000 36 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst Read followed by the Precharge Command Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP NOP Precharge A NOP NOP * tRP CAS latency = 2 tCK2, DQs DOUT Ax0 DOUT Ax1 * DOUT Ax2 NOP DOUT Ax3 Bank A can be reactivated at completion of tRP. Burst Write followed by the Precharge Command Burst Length = 2, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP Activate Bank Ax NOP WRITE Ax0 NOP NOP tDPL# CAS latency = 2 tCK2, DQs DIN Ax0 Precharge A NOP tRP# NOP * DIN Ax1 Bank can be reactivated at completion of tRP. # tDPL and tRP are functions of clock cycle time and speed sort.See the clock Frequency and Latency table. * REV 1.1 June, 2000 37 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of /CAS Latency. Burst Read Interrupted by Precharge Burst Length = 8, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP Precharge A NOP DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax0 DOUT Ax1 NOP DOUT Ax3 * tRP# CAS latency = 3 tCK3, DQs NOP * tRP# CAS latency = 2 tCK2, DQs NOP DOUT Ax2 DOUT Ax3 * Bank A can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. REV 1.1 June, 2000 38 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write Burst Length = 8, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP WRITE Ax0 NOP NOP NOP Precharge A NOP NOP DQM tDPL# CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL CAS latency = 3 tCK3, DQs DIN Ax0 DIN Ax1 DIN Ax2 # tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time . Automatic Refresh Command ( /CAS before /RAS Refresh) When /CS, /RAS, and /CAS are held low with CKE and /WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device, both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the /RAS cycle time (tRC). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having /CS, /RAS, /CAS, and CKE held low with /WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the /RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a stacked device may be refreshed at the same time. REV 1.1 June, 2000 39 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or a Device Deselect Command) is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CLK tCK CKE tCES(min) COMMAND NOP COMMAND NOP NOP NOP NOP NOP : "H" or "L" Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two clock delay, independent of /CAS latency. Data Mask Activated During a Read Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP DQs READ A NOP NOP NOP DOUT A0 NOP NOP NOP NOP DOUT A1 A two-clock delay before the DQs become Hi-Z : "H" or "L" REV 1.1 June, 2000 40 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when /CS is brought high, the /RAS, /CAS, and /WE signals become don't cares. Clock Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend During a Read Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operaton starts COMMAND NOP DQs READ A NOP NOP NOP DOUT A0 : "H" or "L" NOP DOUT A1 NOP DOUT A2 DOUT element at the DQs when the suspend operation starts is held valid If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the Clock Suspend mode is exited. REV 1.1 June, 2000 41 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Clock Suspend During a Write Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK A one clock delay to exit the Suspend command CKE A one clock delay before suspend operaton starts COMMAND NOP DQs WRITE A NOP NOP DIN A0 DIN A1 DIN A2 NOP NOP NOP DIN A3 : "H" or "L" DIN is masked during the Clock Suspend Period REV 1.1 June, 2000 42 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6650C0T 64Mb : x4 PC133 / PC100 Synchronous DRAM Package Dimension ( 400 mil; 54 pin; Thin Small Outline Package ) SYMBOL A A1 A2 B c D HE E e L L1 MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40 S θ 0° MILLIMETER NOM. 0.10 1.00 0.35 22.22 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 MIN. 0.002 0.037 0.012 0.005 0.60 0.460 0.390 0.031 0.016 8° 0° INCH NOM. 0.004 0.039 0.014 0.875 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.018 0.008 0.470 0.410 0.024 8° Note: 1. 2. 3. 4. Dimension D odes not include mold protrusions or gate burrs. Mold protrusion and gate burrs shall exceed 0.15 mm per side. Dimension E1 does not include interlead mold protrusions. Interlead mold protrusions shall not exceed 0.25 mm per side. REV 1.1 June, 2000 43 © NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.