NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM NT56V6610C0T (8Mx8) NT56V6620C0T (4Mx16) 64Mb Synchronous DRAM Data Sheet REV 1.1 June, 2000 1 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Revision Log Rev Date Version Content of Modification Sep / 1999 1.0 1 st Revision June / 2000 1.1 Added speed grade –75B (PC133@CL3 & PC100@CL2) to following items as : 1. Product Family 2. DC currents 3. AC Timing Parameters REV 1.1 June, 2000 2 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Contents Revision Log ................................................................................................................................................................02 Table of Contents.........................................................................................................................................................03 Description ...................................................................................................................................................................05 Features........................................................................................................................................................................06 Product Family ............................................................................................................................................................07 Pin Assignment............................................................................................................................................................07 Pin Description.............................................................................................................................................................08 Functional Block Diagram ...........................................................................................................................................09 Ordering Information ...................................................................................................................................................10 DC Characteristics .......................................................................................................................................................11 Absolute Maximum Ratings .......................................................................................................................................11 Recommended DC Operating Conditions .....................................................................................................................11 Capacitance ..........................................................................................................................................................11 DC Electrical Characteristics .....................................................................................................................................11 DC Output Load Circuit ............................................................................................................................................12 Operating, Standby, and Refresh Currents ...................................................................................................................13 AC Characteristics .......................................................................................................................................................14 AC Output Load Circuits ...........................................................................................................................................14 AC Timing Parameters.................................................................................................................................................15 Clock and Clock Enable Parameters ............................................................................................................................15 Common Parameters ...............................................................................................................................................15 Mode Register Set Cycle ..........................................................................................................................................15 Read Cycle ...........................................................................................................................................................16 Refresh Cycle ........................................................................................................................................................16 Write Cycle ...........................................................................................................................................................16 Clock Frequency and Latency ....................................................................................................................................16 Command Truth Table .................................................................................................................................................18 DEVICE OPERATIONS .................................................................................................................................................24 Power On and Initialization ........................................................................................................................................24 Programming the Mode Register ................................................................................................................................24 Mode Register Definition ..........................................................................................................................................24 Burst Mode Operation ..............................................................................................................................................25 Burst Length and Sequence ......................................................................................................................................25 Bank Activate Command ..........................................................................................................................................26 Bank Select ...........................................................................................................................................................26 Read and Write Access Modes ..................................................................................................................................27 Burst Read Command .............................................................................................................................................28 Read Interrupted by a Read .......................................................................................................................................29 Read Interrupted by a Write ......................................................................................................................................30 Burst Write Command .............................................................................................................................................30 Write Interrupted by a Write ......................................................................................................................................31 Write Interrupted by a Read ......................................................................................................................................31 Burst Stop Command ..............................................................................................................................................32 Auto-Precharge Operation ........................................................................................................................................33 Precharge Command ...............................................................................................................................................37 Bank Selection for Precharge by Address Bits ...............................................................................................................37 Precharge Termination .............................................................................................................................................39 Automatic Refresh Command ....................................................................................................................................40 Self Refresh Command ............................................................................................................................................40 Power Down Mode ..................................................................................................................................................41 Data Mask ............................................................................................................................................................41 REV 1.1 June, 2000 3 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM No Operation Command ...........................................................................................................................................41 Deselect Command .................................................................................................................................................41 Clock Suspend Mode ...............................................................................................................................................42 Timing Diagrams .........................................................................................................................................................43 AC Parameters for Write Timing ................................................................................................................................43 AC Parameters for Read Timing (3/3/3) .......................................................................................................................44 AC Parameters for Read Timing (2/2/2) .......................................................................................................................45 AC Parameters for Read Timing (3/2/2) .......................................................................................................................46 AC Parameters for Read Timing (3/3/3) .......................................................................................................................47 Mode Register Set ..................................................................................................................................................48 Power On Sequence and Auto Refresh (CBR) ...............................................................................................................49 Clock Suspension, DQM during Burst Read ..................................................................................................................50 Clock Suspension, DQM during Burst Write .................................................................................................................51 Power Down Mode and Clock Suspend ........................................................................................................................52 Auto Refresh (CBR) ................................................................................................................................................54 Self Refresh (Entry and Exit) .....................................................................................................................................54 Random Row Read (Interleaving Banks) with Precharge ..................................................................................................55 Random Row Read (Interleaving Banks) with Auto Precharge ...........................................................................................56 Random Row Write (Interleaving Banks) with Auto Precharge ...........................................................................................57 Random Row Write (Interleaving Banks) with Precharge ..................................................................................................58 Read-Write Cycle ...................................................................................................................................................59 Interleaved Column Read Cycle ..................................................................................................................................60 Auto Precharge after Read Burst ...............................................................................................................................61 Auto Precharge after Write Burst ................................................................................................................................62 Burst Read and Single Write Operation ........................................................................................................................63 Full Page Burst Read and Single Write Operation ...........................................................................................................64 /CS Function (Only /CS signal needs to be asserted at minimum rate) .................................................................................65 Package Dimension .....................................................................................................................................................66 REV 1.1 June, 2000 4 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Description The NT56V6610C0T and NT56V6620C0T are four-bank Synchronous DRAMs organized as 2Mbit x 8 I/O x 4 Bank and 1Mbitx16I/Ox4Bank, respectively. These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NANYA advanced 64Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. /RAS, /CAS, /WE, and /CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional /RAS /CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (A12, A13) are strobed with /RAS. Ten column addresses (A0-A9) plus bank select addresses and A10 are strobed with /CAS. Column address A9 is dropped on the x8 device and column addresses A8 and A9 are dropped on the x16 device. Access to the lower or upper DRAM in a stacked device is controlled by /CS0 and /CS1, respectively. Prior to any access operation, the /CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A9 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133MHz is possible depending on burst length, /CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR), Self Refresh, and Low Power operation are supported. Feature • JEDEC standard 3.3V± 0.3V Power Supply • LVTTL compatible inputs and outputs • Four Banks controlled by Bank Selects(A12/A13) • Single Pulsed /RAS Interface • Fully Synchronous to Positive Clock Edge • MRS cycle with address key programmability for : - CAS Latency ( 2, 3 ) - Burst Length ( 1, 2, 4, 8 & Full-page ) - Burst Type ( Sequential or Interleave ) • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command • Data Mask for Read/Write control (x8) • Dual Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh • Suspend Mode and Power Down Mode • Standard Power operation • 4096 refresh cycles/64ms • Random Column Address every CLK (1-N Rule) • Package:54-pin 400 mil TSOP-Type II REV 1.1 June, 2000 5 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Product Family Part NO. Organization NT56V6610C0T-75B Speed ( MHz@CL-tRP-tRCD) 133 MHz @ 3-3-3 NT56V6610C0T-75 Interface Package 100 MHz @ 2-2-2 133 MHz @ 3-3-3 - NT56V6610C0T-8B 125 MHz @ 3-3-3 100MHZ @ 2-2-2 NT56V6610C0T-8A 125 MHz @ 3-3-3 100MHz @ 3-2-2 NT56V6620C0T-7 143 MHz @ 3-3-3 - NT56V6620C0T-75B 133 MHz @ 3-3-3 100 MHz @ 2-2-2 133 MHz @ 3-3-3 - NT56V6620C0T-8B 125 MHz @ 3-3-3 100MHZ @ 2-2-2 NT56V6620C0T-8A 125 MHz @ 3-3-3 100MHz @ 3-2-2 8M x 8 54pin NT56V6620C0T-75 REV 1.1 June, 2000 4M x 16 LVTTL TSOP II 6 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Pin Assignment ( Top View ) 4M x 16 8M x 8 VDD VDD ¡´ 1 54 Vss Vss DQ0 DQ0 2 53 DQ7 DQ15 VDDQ VDDQ 3 52 VssQ VssQ DQ1 NC 4 51 NC DQ14 DQ2 DQ1 5 50 DQ6 DQ13 VSSQ VSSQ 6 49 VDDQ VDDQ DQ3 NC 7 48 NC DQ12 DQ4 DQ2 8 47 DQ5 DQ11 VDDQ VDDQ 9 46 VSSQ VSSQ DQ5 NC 10 45 NC DQ10 DQ6 DQ3 11 44 DQ4 DQ9 VSSQ VSSQ 12 43 VDDQ VDDQ DQ7 NC 13 42 NC DQ8 VDD VDD 14 41 VSS VSS LDQM NC 15 40 NC NC WE WE 16 39 DQM UDQM CAS CAS 17 38 CLK CLK RAS RAS 18 37 CKE CKE CS CS 19 36 NC NC A13/BS0 A13/BS0 20 35 A11 A11 A12/BS1 A12/BS1 21 34 A9 A9 A10/AP A10/AP 22 33 A8 A8 A0 A0 23 32 A7 A7 A1 A1 24 31 A6 A6 A2 A2 25 30 A5 A5 A3 A3 26 29 A4 A4 VDD VDD 27 28 VSS VSS 54-pin Plastic TSOP-II 400 mil REV 1.1 June, 2000 7 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Pin Description CLK Clock Input DQ0-DQ15 Data Input/Output CKE Clock Enable DQM, LDQM, UDQM Data Mask /CS (/CS0, /CS1 ) Chip Select VDD Power (+3.3V) /RAS Row Address Strobe VSS Ground /CAS Column Address Strobe VDDQ Power for DQs (+3.3V) /WE Write Enable VSSQ Ground for DQs BS1, BS0 (A12, A13) Bank Select NC No Connection A0-A11 Address Inputs -- -- Input / Output Functional Description Symbol Type Polarity CLK Input Positive Edge CKE Input Active High Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. /CS enables the command decoder when low and disables the command decoder /CS Input Active Low when high. When the command decoder is disabled, new commands are ignored but previous operations continue. /RAS, /CAS /WE BS1, BS0 (A12, A13) Input Active Low Input -- When sampled at the positive rising edge of the clock, /CAS, /RAS, and /WE define the operation to be executed by the SDRAM. Selects which bank is to be active. During a Bank Activate command cycle, A0-A11 defines the row address (RA0RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0CA9) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write A0 - A11 Input -- cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0-DQ15 InputOutput -- Data Input/Output pins operate in the same manner as on conventional DRAMs The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, LDQM and UDQM control the lower and upper byte DQM LDQM I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and Input Active High UDQM controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. VDD, VSS Supply -- VDDQ, VSSQ Supply -- REV 1.1 June, 2000 Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. 8 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Functional Block Diagram CLK CLK Buffer Column Decoder Column Decoder Row Decoder CKE Buffer Row Decoder CKE Cell Array Memory Bank 0 Sense Amplifiers Cell Array Memory Bank 1 Sense Amplifiers A0 A1 A2 A7 A8 A9 Mode Register A11 A12 A13 A10 Data Input / Output Buffers A6 Data Control Circuitry A5 DQ0 Control Signal Generator A4 Address Buffers ( 14 ) A3 DQX CAS WE Column Decoder Row Decoder Column Decoder Row Decoder RAS Command Decoder CS Column Address Counter Refresh Counter DQM Cell Array Memory Bank 2 Sense Amplifiers Cell Array Memory Bank 3 Sense Amplifiers Cell Array , per bank , for 2Mb x 8 DQ : 4096 Row x 512 Col x 8 DQ (DQ0-DQ7 ). Cell Array , per bank , for 1Mb x 16 DQ : 4096 Row x 256 Col x 16 DQ (DQ0-DQ15). REV 1.1 June, 2000 9 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Part Number Guide NT 56 V 6 6 10 C 0 T - XX NANYA Memory*(1) Speed*(10) Device*(2) Package*(9) Voltage*(3) Interface*(8) Density*(4) Revision*(7) Refresh Time*(5) (1) NANYA Memory Configration*(6) (6) Configuration 10 - - - - - - - - 4 bank, x 8 20 - - - - - - - - 4 bank, x 16 (2) Device (7) Revision 56 - - - - - - - - SDRAM A - - - - - - - - 1st version B - - - - - - - - 2nd version C - - - - - - - - 3rd version D - - - - - - - - 4th version (3) Voltage (8) Interface V - - - - - - - - 3.3V 0 - - - - - - - - LVTTL 1 - - - - - - - - SSTL (4) Density (9) Package 1 - - - - - - - - 16M T - - - - - - - -TSOP II 6 - - - - - - - - 64M F - - - - - - - -TQFP 2 - - - - - - - - 128M Q - - - - - - - -QFP (5) Refresh Time (10) Speed 7 - - - - - - - - 2K/32ms 7 - - - - - - - -143MHz 6 - - - - - - - - 4K/64ms 75 - - - - - - -133MHz 8 - - - - - - - -125MHz 10 - - - - - - -100MHz REV 1.1 June, 2000 10 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM DC Characteristics Absolute Maximum Ratings Rating Units Notes VDD Symbol Power Supply Voltage Parameter -0.3 to +4.6 V 1 VDDQ Power Supply Voltage for Output -0.3 to +4.6 V 1 VIN Input Voltage -0.3 to VDD+0.3 V 1 VOUT Output Voltage -0.3 to VDD+0.3 V 1 TA Operating Temperature (ambient) TSTG Storage Temperature PD Power Dissipation 0 to +70 °C 1 -55 to +125 °C 1 1.0 W 1 IOUT Short Circuit Output Current 50 mA 1.Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1 Recommended DC Operating Conditions (TA = 0 to 70 °C ) Symbol Rating Parameter Min. Typ. Max. Units Notes VDD Power Voltage 3.0 3.3 3.6 V 1 VDDQ Power Voltage for Output 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 - VDD + 0.3 V 1,2 VIL Input Low Voltage -0.3 - 0.8 V 1,3 1. All voltages referenced to VSS and VSSQ. 2. V IH (max) = V DD / V DDQ + 1.2V for pulse width ≤ 5ns 3. VIL (min) = VSS /VSSQ - 1.2V for pulse width ≤ 5ns . Capacitance (TA = 25 °C, f = 1MHz, VDD = 3.3V ± 0.3V) Symbol Parameter Min. Typ. Max. 2.5 3.0 3.8 Input Capacitance (CLK) 2.5 2.8 3.5 Output Capacitance (DQ0 – DQ15) 4.0 4.5 6.5 Input Capacitance CI CO (A0-A11, BS0, BS1, /CS, /RAS, /CAS, /WE, CKE, DQM) Units Notes pF 1 1. Multiply given planar values by 2 for 2-High stacked device except /CS. REV 1.1 June, 2000 11 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM DC Electrical Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V) Symbol II(L) IO(L) VOH VOL Parameter Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ) Output Level (LVTTL ) Output "H" Level Voltage (IOUT = -2.0mA) Output Level (LVTTL ) Output "L" Level Voltage (IOUT = +2.0mA) Min. Max. Units Notes -1 +1 uA 1 -1 +1 uA 1 2.4 - V - - 0.4 V - 1. Multiply given planar values by 2 for 2-High stacked device. DC Output Load Circuit 3.3 V 1200 ohms VOH(DC) = 2.4V,I OH= -2mA Output VOL(DC) = 0.4V,I OL= -2mA 50 pF REV 1.1 June, 2000 870 ohms 12 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Operating, Standby, and Refresh Currents (VDD =3.3V ± 10% , TA =0°C to 70°C) Parameter Symbol Operating current ICC1 Precharge standby current in power-down mode ICC2P Precharge standby current in non power-down mode No Operating current ( Active state : 4 bank) Operating current ( Burst mode ) Auto(CBR) refresh current Self refresh current ICC2PS ICC2N Version Test condition 1 bank operation , tRC = tRC(mim), tCK = min Active-Precharge Command cycling without burst operation CKE <= VIL(max), tCK = min, /CS = VIH(min), CKE <= VIL(max), tCK =oo, /CS = VIH(min) CKE >= VIH(min), /CS = VIH(min), tCK = min Unit Note mA 1,2,3 2 mA 1 2 mA 1 mA 1 -7 - 75(B) - 8B - 8A 75 75 70 70 35 35 25 25 ICC2NS CKE >= VIH(min), tCK =oo 5 mA 1,5 ICC3P CKE<=VIL(max), tCK =min 3 mA 1,7 ICC3N ICC4 ICC5 ICC6 CKE >=VIH(min), /CS = VIH(min), tCK =min t CK =min , Read/ Write command cycling, Multiple banks active, gapless data, BL=4 t RC = tRC(min) ; tCK =min CBR command cycling CKE <= 0.2V 40 40 30 30 mA 1,5 120 120 90 90 mA 1,6 145 145 140 140 mA 1,3,4 mA 1 1 Note : 1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the other deck. 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t and t .Input signals are changed up to three times during t (min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during t (min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. REV 1.1 June, 2000 13 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Characteristics (TA = 0 to +70 °C , VDD = 3.3V ± 0.3V) 1. An initial pause of 200us,with DQM and CKE held high , is required after power-up. A precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation . 2. The Transition time is measured between VIH and VIL (or between VIL and VIH). 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between 4. Load Circuit A : AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A : AC measurements assume tT = 1.0ns. VIL and VIH) in a monotonic manner. 6. Load Circuit B : AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B : AC measurements assume tT = 1.2ns. AC Output Load Circuits tT tCKL Clock tSETUP tCKH VIH 1.4V VIL Vtt = 1.4V 50 ohm Output Zo = 50 ohm 50 pF tHOLD AC Output Load Circuit ( A ) Input 1.4V tAC Output tOH Zo = 50 ohm tLZ Output 1.4V 50 pF AC Output Load Circuit ( B ) REV 1.1 June, 2000 14 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Timing Parameters Clock and Clock Enable Parameters Symbol tCK3 tCK2 tAC3(A) tAC2(A) tAC3(B) tAC2(B) Parameter Clock Cycle Time, /CAS Latency = 3 Clock Cycle Time, /CAS Latency = 2 Clock Access Time, /CAS Latency = 3 Clock Access Time, /CAS Latency = 2 Clock Access Time, /CAS Latency = 3 Clock Access Time, /CAS Latency = 2 -7 - 75B - 75 - 8B - 8A Unit Max. Min. Max. Min. Max. Min. Max. Min. Max. 7 - 7.5 - 7.5 - 8 - 8 - ns - - 10 - - - 10 - 12 - ns - 6 - - - - - - - - ns 1 - - - - - - - - - - ns 1 - - - 5.4 - 5.4 - 6 - 6 ns 2 - - 6 - - - - 6 - 6 ns 2 ns tCKH Clock High Pulse Width 3 - 2.5 - 2.5 - 3 - 3 - tCKL Clock Low Pulse Width 3 - 2.5 - 2.5 - 3 - 3 - ns tCES Clock Enable Set-up Time 2 - 1.5 - 1.5 - 2 - 2 - ns tCEH Clock Enable Hold Time 1 - 0.8 - 0.8 - 1 - 1 - ns 0 7 0 7.5 0 7.5 0 10 0 12 ns 0.5 10 0.5 10 0.5 10 0.5 10 0.5 10 ns tSB tT Power down mode Entry Time Transition Time (Rise and Fall) Note Min. 1.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A 2.Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B. Common Parameters Symbol Parameter -7 - 75B - 75 - 8B - 8A Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tCS Command Setup Time 2 - 1.5 - 1.5 - 2 - 2 - ns tCH Command Hold Time 1 - 0.8 - 0.8 - 1 - 1 - ns 2 - 1.5 - 1.5 - 2 - 2 - ns 1 - 0.8 - 0.8 - 1 - 1 - ns tAS tAH Address and Bank Select Set-up Time Address and Bank Select Hold Time Note tRCD /RAS to /CAS Delay 21 - 20 - 20 - 20 - 20 - ns 1 tRC Bank Cycle Time 70 - 65 - 65 - 70 - 70 - ns 1 tRAS Active Command Period 49 50 - ns 1 tRP Precharge Time 21 - 20 - 20 - 20 - 20 - ns 1 tRRD Bank to Bank Delay Time 14 - 15 - 15 - 20 - 20 - ns 1 tCCD /CAS to /CAS Delay Time 1 - 1 - 1 - 1 - 1 - CLK 45 45 50 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). REV 1.1 June, 2000 15 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Mode Register Set Cycle Symbol tRSC Parameter Mode Register Set Cycle Time -7 - 75B - 75 - 8B - 8A Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 2 - 2 - 2 - 2 - 2 - Unit Note CLK 1 1.These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Read Cycle Symbol tOH tLZ Parameter Data Out Hold Time Data Out to Low Impedance Time -7 - 75B Min. Max. 2.5 - - 75 Min. Max. - 8B - 8A Min. Max. Min. Max. Min. Max. Unit Note - - - - 2.5 - 2.5 - ns 1 2.7 - 2.7 - 3 - 3 - ns 2 0 - 0 - 0 - 0 - 0 - ns tHZ3 Data Out to High 3 6 3 5.4 3 5.4 3 6 3 6 ns 3 tHZ2 Impedance Time - - - - - - 3 6 3 8 ns 3 2 - 2 - 2 - 2 - 2 - CLK tDQZ DQM Data Out Disable Latency 1.AC Output Load Circuit A. 2.AC Output Load Circuit B. 3.Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Refresh Cycle Symbol Parameter tREF Refresh Period tSREX Self Refresh Exit Time -7 - 75B - 75 - 8B - 8A Unit Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. - 64 - 64 - 64 - 64 - 64 ms 10 - 10 - 10 - 10 - 10 - ns Note Write Cycle Symbol Parameter -7 - 75B - 75 - 8B - 8A Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tDS Data In Set-up Time 2 - 1.5 - 1.5 - 2 - 2 - tDH Data In Hold Time 1 - 0.8 - 0.8 - 1 - 1 - ns tDPL Data input to Precharge 14 - 15 - 15 - 15 - 15 - ns 5 - 5 - 5 - 5 - 5 - CLK - - - - - - 4 - 3 - CLK 0 - 0 - 0 - 0 - 0 - ns tDAL3 tDAL2 tDQW Data In to Active Delay /CAS Latency = 3 Data In to Active Delay /CAS Latency = 2 DQM Write Mask Latency REV 1.1 June, 2000 Note ns 16 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Clock Frequency and Latency Symbol Parameter -7 - 75B - 75 - 8B - 8A Units tCK Clock Frequency 143 133 100 133 125 100 125 83 tCK Clock Cycle Time 7 7.5 10 7.5 8 10 8 12 ns tAA /CAS Latency 3 3 2 3 3 2 3 2 CLK tRP Precharge Time 3 3 2 3 3 2 3 2 CLK tRCD /RAS to /CAS Delay 3 3 2 3 3 2 3 2 CLK tRC Bank Cycle Time 10 9 7 9 9 7 9 6 CLK tRAS Minimum Bank Active Time 7 6 5 6 6 5 6 4 CLK tDPL Data In to Precharge 2 2 2 2 2 2 2 2 CLK tDAL Data In to Active/Refresh 5 5 4 5 5 4 5 4 CLK tRRD Bank to Bank Delay Time 2 2 2 2 2 2 2 2 CLK tCCD /CAS to /CAS Delay Time 1 1 1 1 1 1 1 1 CLK tWL Write Latency 0 0 0 0 0 0 0 0 CLK tDQW DQM Write Mask Latency 0 0 0 0 0 0 0 0 CLK tDQZ DQM Data Disable Latency 2 2 2 2 2 2 2 2 CLK tCSL Clock Suspend Latency 1 1 1 1 1 1 1 1 CLK REV 1.1 June, 2000 MHz 17 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Command Truth Table Function Mode Register Set Auto (CBR) Refresh Entry Self Refresh Exit Self Refresh Single Bank Precharge Precharge all Banks Bank Activate Write Write with AutoPrecharge Read Read with AutoPrecharge Burst Termination No Operation Device Deselect Clock Suspend Mode Entry Clock Suspend Mode Exit Data Write/Output Enable Data Mask/Output Disable Power Down Mode Entry Power Down Mode Exit 1 2. 3. 4. 5. 6. 7. 8. Device State CKE Previous Current Cycle Cycle /CS /RAS /CAS /WE DQM A12, A13 A10 A11, A0-A9 Notes Idle H X L L L L X Idle H H L L L H X X X X Idle H L L L L H X X X X L H H L X H X H X H X X X X H X L L H L X BS L X H X L L H L X X H X H H X X L L L H H L H L X X BS BS Row address L Column 2 2 Active H X L H L L X BS H Column 2 Active H X L H L H X BS L Column 2 Active H X L H L H X BS H Column 2 Active H X L H H L X X X X 3,8 Any H X L H H H X X X X Any H X H X X X X X X X Active H L X X X X X X X X Active L H X X X X X X X X Active H X X X X X L X X X Active H X X X X X H X X X Idle/Active H L X H X X X 6,7 H X H X X L X H X X Any (Power Down) H L H L H H H X X X X 6,7 Idle(SelfRefresh) See Current State Table See Current State Table Idle Active OP Code 2 4 5 All of the SDRAM operations are defined by states of /CS, /WE, /RAS, /CAS, and DQM at the positive rising edge of the clock. Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the Current State Truth Table. Bank Select(BS0,BS1):BS0,BS1=0,0 selects bank0; BS0,BS1=0,1 selects bank1; BS0,BS1=1,0 selects bank2; BS0,BS1= 1,1 selects bank 3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the /CAS latency. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high data clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal. REV 1.1 June, 2000 18 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Clock Enable (CKE) Truth Table Current State Self Fresh Power Down All Banks Idle Any State other than listed above 1. 2. 3. 4. 5. Previous Cycle H CKE Current Cycle X Command X X X X A12, A13 X L H H X X X X L H L H H H X X L L L L H H H H L X L L L X X H H L X X H L X X X L X X X X X X X X X X X X X X L H H X X X X X L H L X X X X X L L X X X X X X H H H H H H H H H H L H H H H H L L L L L X H L L L L H L L L L X X H L L L X H L L L X X X H L L X X H L L X X X X H L X X X H L X H H X X X X X X H L X X X X X X L H X X X X X X /CS /RAS /CAS /WE A11– A10 X X X X OP Code X X OP Code X X Action Notes INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle ILLEGAL Maintain Power Down Mode Refer to the Idle State section of the Current State Truth Table CBR Refresh Mode Register Set Refer to the Idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to operations in the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend 1 2 2 2 2 2 1 2 2 3 3 3 4 3 3 3 4 4 5 L L X X X X X X For the given Current State CKE must be low in the previous cycle. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on the first rising clock after CKE goes high . The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. The Precharge Power Down Mode,the Self Refresh Mode,and the Mode Register Set can only be entered from the all banks idle state. Must be a legal command as defined in the Current State Truth Table. REV 1.1 June, 2000 19 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 1 of 3)(See note 1) Current State Idle Row Active Read /CS /RAS /CAS /WE L L L L L L L L H L H L L L H H L L L L H L L L H H H H X L L L L L H H X L L H L H L H X L H L L L H H L H L L L H L L Mode Register Set Auto or Self Refresh Precharge 2 2,3 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active ILLEGAL 4 Bank Active BS Column Write H L H BS Column Read H H X L L H H X L L L H X L H X X X L L H L BS X L L H H BS Row Address Bank Active L H L L BS Column Write L H L H BS Column Read L L H L L H H X L L H H X L L L H X L H X X X L L H L BS X BS Row Address L L H L L L H H H X X X OP Code X X Notes Set the Mode Register Start Auto or Self Refresh No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation No Operation or Power Down ILLEGAL ILLEGAL Precharge L X X X OP Code X X Action Description L L Write Command A12, A11-A0 A13 OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X BS X Row BS Address Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge Bank Active L L BS Column Write H L H BS Column Read H H X H H X L H X X X X X X X Burst Termination No Operation Device Deselect Start Write; Determine if Auto Precharge Start Read; Determine if Auto Precharge No Operation No Operation No Operation ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start the Write cycle Terminate Burst; Start a new Read cycle Terminate the Burst Continue the Burst Continue the Burst ILLEGAL ILLEGAL Terminate Burst; Start the Precharge ILLEGAL Terminate Burst; Start a new Write cycle Terminate Burst; Start the Read cycle Terminate the Burst Continue the Burst Continue the Burst 4 4 5 6 7,8 7,8 4 8,9 8,9 4 8,9 8,9 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 20 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 2 of 3)(See note 1) Current State Read with Auto Precharge Write with Auto Precharge Precharging Row Activating Command A12, A11-A0 A13 OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X BS X Row BS Address BS Column BS Column X X X X X X OP Code X X /CS /RAS /CAS /WE L L L L L L L L H L H L L L H H L L L L H L L L H H H H X L L L L L H H X L L H L H L H X L H L L L H H L L L L H L L H H H H X L L L L H H X L L L H L H X L H L L H L BS L L H H BS L L H H L L L H BS BS Row Address Column Column L H H L X X Burst Termination L H H H X X No Operation H X X X X X L L L L L L L L H L H L L L H H L L H H L L L H L H H L X X Burst Termination L H H H X X No Operation H X X X X X Device Deselect X Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Notes 4 Bank Active ILLEGAL 4 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL ILLEGAL 4 4 Bank Active ILLEGAL 4 Write Read Burst Termination No Operation Device Deselect Mode Register Set Auto or Self Refresh ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP 4 4 Bank Active ILLEGAL 4 Write Read 4 4 Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP No Operation; Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL 4,10 Write Read ILLEGAL ILLEGAL No Operation; Row Active after tRCD No Operation; Row Active after tRCD No Operation; Row Active after tRCD 4 4 Precharge Device Deselect OP Code X X BS X Row BS Address BS Column BS Column Action Description 4 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 21 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Current State Truth Table (Part 3of 3)(See note 1) Current State Write Recovering Write Recovering With Auto Precharge Refreshing Mode Register Accessing Command A12, /WE A13 /CS /RAS /CAS L L L L L L L H X X L L H L BS L L H H BS X Row Address L H L L BS Column Write L H L H BS Column Read L H H L X X Burst Termination L H H H X X No Operation H X X X X X Device Deselect L L L L L L L H X X L L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X X L H H H X X No Operation H X X X X X Device Deselect L L L L L L L H X X L L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X X L H H H X X H X X X X X L L L L A11-A0 OP Code OP Code OP Code Bank Active Mode Register Set Auto or Self Refresh Precharge OP Code L L H X X L H L BS L L H H BS L L H H L L L H BS BS X Row Address Column Column L H H L X X L H H X H X H X X X X X Notes ILLEGAL ILLEGAL ILLEGAL 4 ILLEGAL 4 Start Write; Determine if Auto Precharge Start Write; Determine if Auto Precharge No Operation; Row Active after tDPL No Operation;Row Active after tDPL No Operation; Row Active after tDPL 9 9 ILLEGAL ILLEGAL ILLEGAL 4 Bank Active ILLEGAL 4 Write Read Burst Termination ILLEGAL ILLEGAL No Operation; Precharge Active after tDPL No Operation; Precharge Active after tDPL No Operation; Precharge Active after tDPL 4,9 4,9 Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL Write Read Burst Termination ILLEGAL ILLEGAL No Operation; Idle after tRC No Operation; Idle after tRC No Operation; Idle after tRC Device Deselect L REV 1.1 June, 2000 Mode Register Set Auto or Self Refresh Precharge No Operation L Action Description Mode Register Set Auto or Self Refresh Precharge ILLEGAL ILLEGAL ILLEGAL Bank Active ILLEGAL Write Read Burst Termination No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL 22 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto(CBR) Refresh operation, if CKE is inactive(low) than the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS Delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. REV 1.1 June, 2000 23 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM DEVICE OPERATIONS Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, /CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command. Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set Command is issued. After initial power up, the Mode Register Set Command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of /RAS, /CAS, /CS, and /WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. /CAS Latency The /CAS latency is a parameter that is used to define the delay from when a Read Command is registered on a rising clock edge to when the data from that Read Command becomes available at the outputs. The /CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the /CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the /CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate /CAS latency has been selected it must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section. REV 1.1 June, 2000 24 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Mode Register Definition Mode Register set: (Programming mode) A13 A12 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 CAS Latency CAS Latency A2 BT A1 A0 Burst Length Burst Type Address bus (Ax) Mode Register (Mx) Burst Length M6 M5 M4 Latency M3 Type M2 M1 M0 BT=0 BT=1 0 0 0 Reserved 0 Sequential 0 0 0 1 1 0 0 1 Reserved 1 Interleave 0 0 1 2 2 0 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Operation Mode M13 M12 M11 M10 M9 M8 M7 0 0 0 0 0 0 0 Normal Mode 0 0 0 0 1 0 0 Multiple Burst with Single Write Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). Three parameters define how the burst mode will operate: burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A13. Burst sequence defines the order in which the burst data will be delivered or stored to the SDRAM. The two types of burst sequence supported are sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page (actual page length is dependent on organization: x4, x8, or x16). Full page burst operation is only possible using the sequential burst type. Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. REV 1.1 June, 2000 25 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Length and Sequence Burst Length Starting Bit Interleave Sequential 0-1 0-1 1-0 1-0 A0 0 2 1 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-0-3-2 1-2-3-0 1 0 2-3-0-1 2-3-0-1 1 1 3-2-1-0 3-0-1-2 4 8 Full Page (Note) A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-0 0 1 0 2-3-0-1-6-7-4-5 2-3-4-5-6-7-0-1 0 1 1 3-2-1-0-7-6-5-4 3-4-5-6-7-0-1-2 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-4-7-6-1-0-3-2 5-6-7-0-1-2-3-4 1 1 0 6-7-4-5-2-3-0-1 6-7-0-1-2-3-4-5 1 1 1 7-6-5-4-3-2-1-0 7-0-1-2-3-4-5-6 n n n Not supported Cn, Cn+1,Cn+2….. Note : Page length is a function of I/O organization and column addressing. X 8 organization (CA0-CA8); Page Length = 512 bits X16 organization (CA0-CA7); Page Length = 256 bits Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling /RAS signal. The Bank Activate command is issued by holding /CAS and /WE high with /CS and /RAS low at the rising edge of the clock. The bank select address A12 A13 is used to select the desired bank. The row address A0 - A11 is used to determine which row to activate in the selected bank. Activation of banks within both decks of a 2-high stacked device is allowed. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the /RAS to /CAS delay time (tRCD). Once a bank has been activated, it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). REV 1.1 June, 2000 26 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Bank Activate Command Cycle CAS Latency = 3, tRCD = 3 T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK Bank A Row Addr. ADDRESS Bank A Col. Addr. Bank B Row Addr. RAS-CAS delay(tRCD) Bank A Activate COMMAND NOP Bank A Row Addr. RAS-RAS delay(tRCD) Write A with Aotu Precharge Bank B Activate NOP Bank A Activate NOP RAS Cycle time (tRC) : "H" or "L" Bank Select The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits BS0 BS1 Bank 0 0 Bank 0 0 1 Bank 1 1 0 Bank 2 1 1 Bank 3 Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting /RAS high and /CAS low at the clock's rising edge after the necessary /RAS to /CAS delay (tRCD). /WE must also be defined at this time to determine whether the access cycle is a read operation (/WE high), or a write operation (/WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive clock cycles at data rates of up to 147 MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. If the burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge Command is issued. Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write Command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary, providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column to column interleave operation can be done between different pages. Finally, Read or Write Commands can be issued to the same bank or between active banks on every clock cycle. REV 1.1 June, 2000 27 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Read Command The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the /CAS latency that is set in the Mode Register. Burst Read Operation Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP CAS latency = 2 tCK2, DQs NOP NOP DOU A0 CAS latency = 3 tCK3, DQs NOP NOP DOU A1 DOU A2 DOU A3 DOU A0 DOU A1 DOU A2 NOP NOP NOP DOU A3 Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read Command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read Command continues to appear on the outputs until the /CAS latency from the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command appears. Read Interrupted by a Read Burst Length = 4, CAS Latency = 2, 3 T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs REV 1.1 June, 2000 NOP DOU A0 NOP NOP NOP NOP DOU B0 DOU B1 DOU B2 DOU B3 DOU A0 DOU B0 DOU B1 DOU B2 NOP NOP DOU B3 28 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus. Minimum Read to Write Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITE A NOP NOP NOP NOP NOP NOP CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 CLK DQM COMMAND NOP READ A : "H" or "L" Non-Minimum Read to Write Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP CLK DQM COMMAND NOP READ A NOP WRITE A CL = 2 : DQM needed to mask first, second bit of READ data. CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CL = 3 : DQM needed to mask first, second bit of READ data. CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 REV 1.1 June, 2000 29 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Write Command The Burst Write command is initiated by having /CS, /CAS, and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no /CAS latency required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A DQs NOP NOP DOU A0 NOP DOU A1 NOP DOU A2 NOP DOU A3 The First data elemant and the Write are registered on the same clock edge. NOP NOP Don't care Extra data is masked Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP 1 Clk Interval DQs REV 1.1 June, 2000 DIN A0 DIN B0 DIN B1 DIN B2 DIN B3 30 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read Command is registered, any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is initiated will actually be written to the memory. Minimum Write to Read Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 WRITE A READ B CAS latency = 2 tCK2, DQs DIN A0 don't care CAS latency = 3 tCK3, DQs DIN A0 don't care T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP DOU B0 don't care NOP NOP NOP DOU B1 DOU B2 DOU B3 DOU B0 DOU B1 DOU B2 NOP DOU B3 Input data must be removed from the DQs at least one clock cycle before the data appears on the outputs to avoid data contention. Input data for the write is masked Non-Minimum Write to Read Interval Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A NOP READ B CAS latency = 2 tCK2, DQs DIN A0 DIN A1 don't care CAS latency = 3 tCK3, DQs DIN A0 DIN A1 don't care NOP NOP DOUT B0 don't care NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 NOP DOUT B3 Input data must be removed from the DQs at least one clock cycle before the data appears on the outputs to avoid data contention. Input data for the write is masked REV 1.1 June, 2000 NOP 31 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Stop Command Once a burst read or write operation has been initiated, there exist several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation or using a Precharge Command to interrupt a burst cycle and close the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having /RAS and /CAS high with /CS and /WE low at the rising edge of the clock. When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state after a delay which is equal to the /CAS Latency set in the Mode Register. Termination of a Burst Read Operation Burst Length = Full Page, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP Burst Stop NOP NOP NOP NOP NOP The burst ends after a delay equal to the CAS latency. CAS latency = 2 tCK2, DQs DOUT A0 CAS latency = 3 tCK3, DQs DOUT A1 DOUT A2 DOUT A0 DOUT A1 DOUT A3 DOUT A2 DOUT A3 If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Termination of a Burst Write Operation Burst Length = Full Page, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency=2,3 DQs NOP WRITE A NOP NOP Burst Stop DIN A0 DIN A1 DIN A2 don't care NOP NOP NOP NOP Input data for the Write is masked REV 1.1 June, 2000 32 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the autoprecharge function. When a Read or a Write Command is given to the SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles have been completed. Regardless of burst length, the precharge will begin (/CAS latency - 1) clocks prior to the last data output. Auto-precharge can also be implemented during Write commands. A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge can not be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted that the device will not respond to the Auto-Precharge command if the device is programmed for full page burst read or write cycles, or full page burst read cycles with single write operation. When using the Auto-Precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. Burst Read with Auto-Precharge Burst Length = 1, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP tRP# CAS latency = 2 tCK2, DQs NOP NOP NOP NOP NOP * DOUT A0 * tRP# CAS latency = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge * Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. REV 1.1 June, 2000 33 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Read with Auto-Precharge Burst Length = 2, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP tRP# CAS latency = 2 tCK2, DQs DOUT A0 NOP NOP NOP NOP * DOUT A1 * tRP# CAS latency = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge DOUT A1 * Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. Burst Read with Auto-Precharge Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP NOP NOP tRP# CAS latency = 2 tCK2, DQs DOUT A0 DOUT A1 DOUT A2 NOP NOP * DOUT A3 * tRP# CAS latency = 3 tCK3, DQs DOUT A0 Begin Auto-Precharge DOUT A1 * DOUT A2 DOUT A3 Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. REV 1.1 June, 2000 34 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Although a Read Command with auto-precharge cannot be interrupted by a command to the same bank, it can be interrupted by a Read or Write Command to a different bank. If the interrupting command is issued before auto-precharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP. Burst Read with Auto-Precharge Interrupted by Read Burst Length = 4, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP READ B NOP NOP tRP# CAS latency = 2 tCK2, DQs DOUT A0 NOP NOP NOP * DOUT A1 DOUT B0 tRP# CAS latency = 3 tCK3, DQs NOP DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 * DOUT A0 DOUT A1 * DOUT B3 Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ contention. Burst Read with Auto-Precharge Interrupted by Write Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP WRITE B NOP tRP# CAS latency = 2 tCK2, DQs DOUT A0 DOUT B0 NOP NOP NOP * DOUT B1 DOUT B2 DOUT B3 DOUT B4 DQM * Bank can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank undergoing auto-precharge can not be reactivated until tDAL, Data-in to Active delay , is satisfied. REV 1.1 June, 2000 35 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Write with Auto-Precharge Burst Length = 2, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A AutoPrecharge NOP NOP NOP NOP DIN A0 DIN A0 NOP NOP DIN A1 * tDAL# CAS latency = 3 tCK3, DQs NOP * tDAL# CAS latency = 2 tCK2, DQs NOP DIN A1 * Bank can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The precharge function will begin with the new command. The bank may be reactivated after tRP is satisfied. Burst Write with Auto-Precharge Interrupted by Write Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A AutoPrecharge NOP WRITE B NOP NOP DIN A0 DIN A1 DIN B0 NOP NOP NOP * tDAL# CAS latency = 3 tCK3, DQs NOP DIN B1 DIN B2 * DIN B3 Bank can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. REV 1.1 June, 2000 36 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Write with Auto-Precharge Interrupted by Read Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND WRITE A AutoPrecharge NOP NOP READ B NOP DIN A0 DIN A1 NOP NOP NOP * tDAL# CAS latency = 3 tCK3, DQs NOP DIN A2 DOUT B0 * DOUT B1 DOUT B2 Bank A can be reactivated at completion of tDAL. # Number of clocks required depends on clock cycle time and speed sort. See the clock Frequency and Latency table. Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when /CS, /RAS, and /WE are low and /CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits--A10, A12, and A13--are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank Select Precharged Bank(s) LOW BS0, BS1 Bank defined by BS0, BS1 only HIGH DON'T CARE All Banks For read cycles, the Precharge Command may be applied (/CAS latency - 1) clocks prior to the last data output. For write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command can be issued. This delay is known as tDPL, Datain to Precharge delay. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). REV 1.1 June, 2000 37 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Read followed by the Precharge Command Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP NOP Precharge A NOP NOP * tRP CAS latency = 2 tCK2, DQs DOUT Ax0 DOUT Ax1 * DOUT Ax2 NOP DOUT Ax3 Bank A can be reactivated at completion of tRP. Burst Write followed by the Precharge Command Burst Length = 2, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP Activate Bank Ax NOP WRITE Ax0 NOP NOP tDPL# CAS latency = 2 tCK2, DQs DIN Ax0 Precharge A NOP tRP# NOP * DIN Ax1 * Bank can be reactivated at completion of tRP. # tDPL and tRP are functions of clock cycle time and speed sort.See the clock Frequency and Latency table. REV 1.1 June, 2000 38 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Precharge Termination The Precharge Command may be used to terminate either a burst read or burst write operation. When the Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read operations, valid data will continue to appear on the data bus as a function of /CAS Latency. Burst Read Interrupted by Precharge Burst Length = 8, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP Precharge A NOP DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax0 DOUT Ax1 * NOP DOUT Ax3 * tRP# CAS latency = 3 tCK3, DQs NOP * tRP# CAS latency = 2 tCK2, DQs NOP DOUT Ax2 DOUT Ax3 Bank A can be reactivated at completion of tRP. # tRP is a function of clock cycle time and speed sort. See the clock Frequency and Latency table. Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write Burst Length = 8, CAS Latency = 2, 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP WRITE Ax0 NOP NOP NOP Precharge A NOP NOP DQM tDPL# CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL CAS latency = 3 tCK3, DQs DIN Ax0 DIN Ax1 DIN Ax2 # tDPL is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time . REV 1.1 June, 2000 39 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Automatic Refresh Command ( /CAS before /RAS Refresh) When /CS, /RAS, and /CAS are held low with CKE and /WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device, both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the /RAS cycle time (tRC). Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having /CS, /RAS, /CAS, and CKE held low with /WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the /RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a stacked device may be refreshed at the same time. Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode Command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can't remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or a Device Deselect Command) is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 CLK tCK CKE tCES(min) COMMAND NOP COMMAND NOP NOP NOP NOP NOP : "H" or "L" REV 1.1 June, 2000 40 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two clock delay, independent of /CAS latency. Data Mask Activated During a Read Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP READ A NOP DQs NOP NOP DOUT A0 NOP NOP NOP NOP DOUT A1 A two-clock delay before the DQs become Hi-Z : "H" or "L" No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when /CS is low with /RAS, /CAS, and /WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when /CS is brought high, the /RAS, /CAS, and /WE signals become don't cares. Clock Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or "freezes" any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM's operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. REV 1.1 June, 2000 41 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Clock Suspend During a Read Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operaton starts COMMAND NOP READ A NOP DQs NOP NOP DOUT A0 NOP DOUT A1 : "H" or "L" NOP DOUT A2 DOUT element at the DQs when the suspend operation starts is held valid If Clock Suspend mode is initiated during a burst write operation, then the input data is masked and ignored until the Clock Suspend mode is exited. Clock Suspend During a Write Cycle ( Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK CKE A one clock delay to exit the Suspend command A one clock delay before suspend operaton starts COMMAND NOP DQs WRITE A NOP NOP DIN A0 DIN A1 DIN A2 NOP NOP NOP DIN A3 : "H" or "L" DIN is masked during the Clock Suspend Period REV 1.1 June, 2000 42 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0 = "L" Bank2,3 = idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T1 T3 T9 tDAL# T8 RAy RAy tRP tRRD RBy Precharge Activate Activate Command Command Command Bank0 Bank0 Bank1 tDPL# RAz RBy #tDPL and #tDAL depand on clock time and speed sort. See the Clock Frequncy and Latency Table. Activate Write Command Command Bank0 Bank0 Ay0 Ay1 Ay2 Ay3 tDH tDS CAy RAz tCHE T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 CBx tCK2 T7 Activate Write with Activate Write with Aotu Aotu Command Command Precharge Bank1 Precharge Bank0 Command Command Bank0 Bank1 Hi-Z T6 tRC RBx RAx CAx T5 tCKL T4 RBx tRCD tCH tCS T2 RAx tCKH tCES T0 ( Burst length = 4, CAS latency = 2 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Parameters for Write Timing Timing Waveform Diagram 43 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK tRAS tRC T5 T6 T7 Activate Command Bank 1 Ax0 T8 Ax2 CBx tRP T9 Ax3 T10 Read with Auto Precharge Command Bank 1 Ax1 Begin Auto Precharge Bank 0 RBx CAx T4 RAx tRRD tCK3 T3 RBx tRCD T2 RAx T1 Activate Read with Command Auto Precharge Bank 0 Command Bank 1 Hi-Z T0 T12 Activate Command Bank 0 Bx0 RAy RAy Bx1 Begin Auto Precharge Bank 1 T11 T13 Burst lenght = 4 , ( CAS latency = 3 ; t RCD = 3 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Parameters for Read Timing (3/3/3) 44 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK tAH T1 RAx RAx tRRD tRCD tAS T4 T5 tLZ tAC2 tRAS(min) tRC T6 Ax0 tOH RBx RBx Begin Auto Precharge Bank 0 CAx tCK3 T3 tCH tCS T2 Ax1 tHZ tRP T7 T9 CBx Bx0 Begin Auto Precharge Bank 1 T8 Activate Read with Activate Read with Command Auto Precharge Command Auto Precharge Bank 0 Command Bank 0 Bank 1 Command Bank 1 Hi-Z tCES T0 tHZ RAy RAy tCEH T11 T12 Activate Command Bank 0 Bx1 tRP T10 T13 Burst lenght = 2 , ( CAS latency = 2 ; t RCD ,tRP = 2 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Parameters for Read Timing (2/2/2) 45 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ Hi-Z tRAS T5 tAC3 T6 Activate Command Bank 1 tRC RBx RAx tRRD T4 Begin Auto Precharge Bank 0 CAx tCK3 T3 RBx tRCD T2 Activate Read with Command Auto Precharge Bank 0 Command Bank 0 Nor required for BL>= 4. Extended tRCD 1 clock. T1 RAx Note:Must satisfy tRAS(min) DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T0 Ax0 tOH tRP T7 T9 T10 Read with Auto Precharge Command Bank 1 Ax1 tHZ CBx Begin Auto Precharge Bank 1 T8 Bx1 T12 Activate Command Bank 0 Bx0 tRP RAy RAy T11 T13 Burst lenght = 2 , ( CAS latency = 3 ; t RCD ,tRCD = 2 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Parameters for Read Timing (3/2/2) 46 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T5 Activate Command Bank 0 Read with Auto Precharge Command Bank 0 for BL >= 4 . Extended tRCD not requred Note:Must satisfy tRAS(min). Hi-Z tRAS(min) tRC T6 Ax1 T8 T9 T11 CBx T12 Bx0 tRP T13 Activate Command Bank 0 RAy RAy Begin Auto Precharge Bank 1 T10 Read with Auto Precharge Command Bank 1 tRP T7 tOH Ax0 Activate Command Bank 1 tAC3 RBx tRRD T4 Begin Auto Precharge Bank 0 CAx tCK3 T3 RAx tRCD T2 RBx T1 RAx T0 Burst lenght = 2 , ( CAS latency = 3 ; t RCD = 3 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM AC Parameters for Read Timing (3/3/3) 47 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM T22 T21 T20 T19 REV 1.1 June, 2000 Any Command Mode Register Set Command Precharge Command All Banks tRP DQ DQM A0-A9 A10,A11 BS0,BS1 WE CAS RAS CS CKE CLK T0 T1 Hi-Z T2 T3 T4 address key tRSC T5 T6 T7 tCK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 ( CAS latency = 2 ) Mode Register Set 48 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 DQ DQM A0-A9,A11 A10 BS WE CAS RAS CS CKE CLK T2 Precharge Command All Banks Hi-Z T3 T4 1st Auto Refresh Command tRP High level is required T1 Input must be stable for 200us T0 tCK T5 T6 T8 T9 T10 T11 T12 8th Auto Refresh Command Minimun of 8 Refresh cycles are required T7 T13 tRC T14 T15 T18 Mode Register Set Command T19 Any Command 2 Clock min. T17 address key T16 T20 T21 T22 NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Power On Sequence and Auto Refresh (CBR) 49 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z RAx RAx T1 Activate Command Bank 0 T0 T2 T4 Read Command Bank 0 CAx tCK3 T3 tCES T5 Ax1 tCEH T8 T9 T11 Ax2 T10 T12 Clock Suspend Clock Suspend 1 Cycles 2 Cycles T7 Ax0 T6 Ax3 T14 T15 Clock Suspend 3 Cycles T13 T16 Ax4 T17 T18 RCD tHZ T21 Ax7 T20 Ax6 T19 Burst lenght = 8 , ( CAS latency = 3 ; t T22 =3) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Clock Suspension, DQM during Burst Read 50 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z RAx RAx T1 Activate Command Bank 0 T0 T2 T5 Clock Suspend 1 Cycles T4 Read Command Bank 0 DAx0 CAx tCK3 T3 DAx1 T7 T8 Clock Suspend 2 Cycles T6 DAx2 T9 T11 T13 DAx3 T12 Clock Suspend 3 Cycles T10 T14 T16 DAx5 T15 T19 DAx7 T18 DAx6 T17 T20 RCD T21 Burst lenght = 8 , ( CAS latency = 3 ; t T22 =3) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Clock Suspension, DQM during Burst Write 51 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z RAx RAx tCES T1 Activate Command Bank 0 T0 T2 tSB tCES T4 T5 NOP ACTIVE STANDBY T3 Ax1 T8 T9 T10 Ax2 T11 T12 Clock Suspend Clock Suspend Start End Ax0 tCK2 T7 Read Command Bank 0 CAx T6 tHZ T14 Ax3 T13 T15 T16 T17 tSB T18 tCES T20 T21 NOP Precharge STANDBY T19 Any Command T22 Burst lenght = 4 , ( CAS latency = 2 ) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Power Down Mode and Clock Suspend 52 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM T22 T21 T20 DQ DQM A0-A9,A11 A10 BS WE CAS RAS Precharge Command All Banks Hi-Z tRP REV 1.1 June, 2000 CS CKE CLK T0 T1 tCK2 T2 T3 Auto Refresh Command T4 T5 tRC T6 T7 T8 T9 Auto Refresh Command T10 T11 T12 tRC T13 T14 T15 T16 T17 T18 T19 ( CAS latency = 2 ) Auto Refresh (CBR) 53 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 DQ DQM A0-A9,A11 A10 BS WE CAS RAS CS CKE CLK T1 All Banks must be idle Hi-Z T0 T2 tSB tCES T4 Self Refresh Entry T3 Power Down Entry tCES Tm Self Refresh Exit tSREX Power Down Exit tRC Any Command Tm+1 Tm+2 Tm+3 T m+4 Tm+5 Tm+6 T m+7 T m+8 T m+9 Tm+10 Tm+11 Tm+12 Tm+13 T m+14 T m+15 ( Note : The CLK signal must be reestablished prior to CKE returning high.) NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Self Refresh (Entry and Exit) 54 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z tRCD T1 Activate Command Bank 1 RBx RBx High T0 T2 T4 Read Command Bank 1 CBx tCK3 T3 tAC3 T5 Bx1 RAx RAx T7 Activate Command Bank 0 Bx0 T6 Bx2 T8 Bx3 Bx4 CAx Bx5 T10 T11 Bx6 T12 Read Precharge Command Command Bank 0 Bank 1 T9 Ax0 T13 T15 Activate Command Bank 1 Ax1 RBy RBy T14 T16 Ax5 Read Command Bank 1 Ax4 T18 CBy T17 Ax6 T20 By0 T22 , tRP= 3 ) T21 RCD Read Command Bank 0 DAx7 T19 Burst lenght = 8 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Random Row Read (Interleaving Banks) with Precharge 55 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 RBx RBx High Activate Command Bank 1 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T0 T2 CBx tCK3 T3 Read with Auto Precharge Command Bank 1 Hi-Z tRCD T1 T4 tAC3 T5 Bx0 T6 Bx2 RAx RAx T8 Activate Command Bank 0 Bx1 T7 Bx3 T9 Bx5 Bx6 Read with Auto Precharge Command Bank 0 Bx4 T12 T13 T14 Bx7 Ax0 Start Auto Precharge Bank1 T11 CAx T10 T16 Activate Command Bank 1 Ax1 RBy RBy T15 Ax4 T20 T22 , tRP= 3 ) T21 RCD Ax6 Ax7 By0 Start Auto Precharge Bank 0 T19 Ax5 CBy T18 Read with Auto Precharge Command Bank 1 T17 Burst lenght = 8 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Random Row Read (Interleaving Banks) with Auto Precharge 56 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 RAx RAx High Activate Command Bank 0 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T0 T2 DAx0 CAx DAx1 tCK3 T3 Write with Auto Precharge Command Bank 0 Hi-Z tRCD T1 T4 T5 T6 DAx5 RBx RBx T8 DAx6 Activate Command Bank 1 DAx4 T7 T9 DBx0 T16 T17 T21 By0 Write with Auto Precharge Command Bank 0 DAy0 T22 , tRP= 3 ) tDAL# CAy T20 DBx7 T19 DBx6 T18 RCD # Number of clocks depends on clock cycle time and speed sort. See the clock Frequency and Latency table. Bank may be reactivated the completion of t DAL Activate Command Bank 0 DBx5 RAy RAy T15 DBx4 T14 DBx3 tDAL# T13 DBx2 T12 DBx1 T11 Write with Auto Precharge Command Bank 1 DAx7 CBx T10 Burst lenght = 8 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Random Row Write (Interleaving Banks) with Auto Precharge 57 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 RAx RAx High Activate Command Bank 0 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T0 Hi-Z tRCD T1 DAx0 CAx DAx1 tCK3 T3 Write Command Bank 0 T2 T4 T5 T6 DAx5 RBx RBx T8 DAx6 Activate Command Bank 1 DAx4 T7 T9 DBx0 Precharge Command Bank 0 T16 Activate Command Bank 0 DBx5 RAy RAy T15 DBx4 T14 DBx3 tRP T13 DBx2 T12 DBx1 T11 Write Command Bank 1 DAx7 CBx T10 T17 Write Command Bank 0 DAy0 tDPL Precharge Command Bank 1 DAy1 T22 , tRP= 3 ) T21 RCD CAy T20 DBx7 T19 DBx6 T18 Burst lenght = 8 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Random Row Write (Interleaving Banks) with Precharge 58 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z RAx RAx T1 Activate Command Bank 0 T0 T2 T4 Read Command Bank 0 CAx tCK3 T3 T5 T6 Ax0 T7 Ax2 T9 Ax3 T10 The Read Data is Masked with a Two Clock Latency Ax1 T8 T16 DAy4 T15 DAy3 T14 Write The Write Data Command is Masked with a Bank 0 Zero Clock Latency DAy0 T13 DAy1 T12 CAy T11 T18 Precharge Command Bank 0 T17 T19 T20 Burst lenght = 8 , ( CAS latency = 3 ; t T22 , tRP= 3 ) T21 RCD NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Read-Write Cycle 59 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z RAx RAx T1 Activate Command Bank 0 T0 CAx tCK3 T3 Read Command Bank 0 tRCD T2 T4 Ax0 tAC3 T6 Activate Command Bank 1 RBx RBx T5 Ax1 CBx T8 Ax2 T9 Ax3 CBy T11 Bx1 CBz T12 By0 T14 By1 CAy T13 Bz0 T15 Read Read with Command Auto Precharge Bank 1 Command Bank 0 Bx0 T10 Read Read Command Command Bank 1 Bank 1 T7 Ay0 T17 Precharge Command Bank 1 Bz1 T16 Ay1 T19 T20 Ay2 Ay3 T22 , tRP= 3 ) T21 RCD Start Auto Precharge Bank 0 T18 Burst lenght = 4 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Interleaved Column Read Cycle 60 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Hi-Z T1 T2 CAx Activate Read Command Command Bank 0 Bank 0 RAx RAx High T0 T4 T5 Ax0 T6 Ax1 CBx T7 Ax2 Activate Read with Command Auot Precharge Bank 1 Command Bank 1 RBx RBx tCK3 T3 T8 Ax3 T9 Bx1 Bx2 Read with Auot Precharge Command Bank 0 Bx0 T12 T14 RBy RBx T13 Ay0 Activate Command Bank 1 Bx3 Start Auto precharge Bank 1 T11 CAy T10 CBy T16 T17 Ay1 Ay3 Read with Auto Precharge Command Bank 1 Ay2 T19 T20 By0 By1 T22 , tRP= 3 ) T21 RCD Start Auto precharge Bank 1 T18 Start Auto precharge Bank 0 T15 Burst lenght = 4 , ( CAS latency = 3 ; t NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Auto Precharge after Read Burst 61 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 Hi-Z RAx RAx High T1 DAx0 CAx T2 DAx1 Activate Write *BS0="L" Bank2,3=idle Command Command Bank 0 Bank 0 DQ DQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T0 T4 DAx3 T5 DBx0 CBx T6 DBx1 DBx2 T8 DBx3 DAy0 DBy0 Activate Write with Command Auto Bank 0 Precharge Command Bank 0 T22 tDAL# T21 DAz3 T20 DAz2 T19 DAz1 T18 DAz0 CAz T17 DBy3 T16 DBy2 RAz RAz T15 DBy1 tDAL# CBy T14 Activate Write with Command Auto Bank 1 Precharge Command Bank 1 DAy2 RBy T13 DAy3 T12 RBy T11 DAy1 tDAL# CAy T10 Write with Auot Precharge Command Bank 0 T9 # Number of clocks depends on clock cycle and speed sort. See the Clock Frequency and Latency table. Bank may be reactivated at the completion of t DAL. T7 Activate Write with Command Auot Bank 1 Precharge Command Bank 1 DAx2 RBx RBx tCK2 T3 Burst lenght = 4 , ( CAS latency = 2 NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Auto Precharge after Write Burst 62 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ8- DQ15 DQ0- DQ7 UDQM LDQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK Activate Read Command Command Bank 0 Bank 0 Av0 RBx tCK2 T3 Hi-Z CAv T2 Av0 T1 Hi-Z RAv RAv High T0 T4 Av1 Av1 T5 Av2 Av2 T6 Av3 Av3 T7 CAw T9 T11 Ay0 Ay0 RBx T14 Read Command Bank 0 T16 Ay2 T17 Upper Byte is masked Ay1 RAz T15 Lower Byte is masked T13 CAy T12 Singal Write Command Bank 0 DAx0 CAx T10 Singal Write Command Bank 0 DAw0 T8 Ay3 Ay3 T18 T20 Singal Write Command Bank 0 DAz0 DAz0 CAz T19 T22 Lower Byte is masked T21 Burst lenght = 4 , ( CAS latency = 2 NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Burst Read and Single Write Operation 63 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 *BS0="L" Bank2,3=idle DQ8- DQ15 DQ0- DQ7 UDQM LDQM A0-A9,A11 A10 *BS1 WE CAS RAS CS CKE CLK T4 T5 Activate Command Bank 0 Av0 Read Command Bank 0 CAv tCK3 T3 Hi-Z T2 Av0 T1 Hi-Z RAv RAv High T0 Av1 Av1 T7 Av2 Av2 Burst Stop Command T6 T8 Av3 Av3 CAw T9 T11 T13 T15 T16 Read Command Bank 0 CAy T14 Singal Write Command Bank 0 DAx0 DAx0 CAx T12 Singal Write Command Bank 0 DAw0 DAw0 CAw T10 T17 Ay0 Ay0 T18 Ay2 Ay2 T20 Burst Stop Command Ay1 Ay1 CAz T19 Burst lenght = Full page , ( CAS latency = 3 , t T21 ,t T22 =3 Ay3 Ay3 RCD RP NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Full Page Burst Read and Single Write Operation 64 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. REV 1.1 June, 2000 DQ DQM A0-A9 A10 A11(BS) WE CAS RAS CS CKE CLK Hi-Z Low High T0 RAx RAxRAx T2 Activate Command Bank A T1 tRCD tCK3 T3 T5 Read Command Bank A T4 T7 CAx T6 Ax0 T8 Ax1 T9 Ax2 Ax3 T10 T11 Write Command Bank A T17 T18 Precharge Command Bank A tDPL CAy T16 DAy3 T15 DAy2 T14 DAy1 T13 DAy0 T12 T19 T20 at 100MHz Burst lenght = 4 , ( CAS latency = 3 ; t T22 , tRP= 3 ) T21 RCD NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM /CS Function (Only /CS signal needs to be asserted at minimum rate) 65 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT56V6610C0T NT56V6620C0T 64Mb : x8 x16 PC133 / PC100 Synchronous DRAM Package Dimension ( 400 mil; 54 pin; Thin Small Outline Package ) SYMBOL A A1 A2 B c D HE E e L L1 S θ MIN. 0.05 0.95 0.30 0.12 11.56 10.03 0.80 BSC 0.40 0° MILLIMETER NOM. 0.10 1.00 0.35 22.22 BSC 11.76 10.16 0.50 0.80 REF 0.71 REF - MAX. 1.20 0.15 1.05 0.45 0.21 11.96 10.29 MIN. 0.002 0.037 0.012 0.005 0.60 0.460 0.390 0.031 0.016 8° 0° INCH NOM. 0.004 0.039 0.014 0.875 BSC 0.463 0.400 0.020 0.031 REF 0.028 REF - MAX. 0.047 0.006 0.041 0.018 0.008 0.470 0.410 0.024 8° Note: 1. 2. 3. 4. Dimension D odes not include mold protrusions or gate burrs. Mold protrusion and gate burrs shall exceed 0.15 mm per side. Dimension E1 does not include interlead mold protrusions. Interlead mold protrusions shall not exceed 0.25 mm per side. REV 1.1 June, 2000 66 ©NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.