a Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574 FEATURES Low Offset Voltage: 1 V Input Offset Drift: 0.005 V/ⴗC Rail-to-Rail Input and Output Swing 5 V/2.7 V Single-Supply Operation High Gain, CMRR, PSRR: 130 dB Ultralow Input Bias Current: 20 pA Low Supply Current: 750 A/Op Amp Overload Recovery Time: 50 s No External Capacitors Required PIN CONFIGURATIONS 8-Lead MSOP (RM Suffix) NC 2IN A 1IN A V2 1 8 AD8571 4 5 8-Lead SOIC (R Suffix) NC V+ OUT A NC NC 1 2IN A 2 +IN A 3 NC = NO CONNECT 8 NC AD8571 V2 4 7 V+ 6 OUT A 5 NC NC = NO CONNECT APPLICATIONS Temperature Sensors Pressure Sensors Precision Current Sensing Strain Gage Amplifiers Medical Instrumentation Thermocouple Amplifiers OUT A 2IN A +IN A V2 1 8 AD8572 4 5 V+ OUT B 2IN B +IN B 2IN A 2 8 V+ AD8572 V2 4 This new family of amplifiers has ultralow offset, drift and bias current. The AD8571, AD8572 and AD8574 are single, dual and quad amplifiers featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V single supply. With an offset voltage of only 1 µV and drift of 0.005 µV/°C, the AD8571 is perfectly suited for applications where error sources cannot be tolerated. Position, and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD857x family. OUT A 1 +IN A 3 GENERAL DESCRIPTION The AD857x family provides the benefits previously found only in expensive autozeroing or chopper-stabilized amplifiers. Using Analog Devices’ new topology these new zero-drift amplifiers combine low cost with high accuracy. (No external capacitors are required.) In addition, using a patented spread-spectrum autozero technique, the AD857x family virtually eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. 8-Lead SOIC (R Suffix) 8-Lead TSSOP (RU Suffix) 1 14 AD8574 7 8 OUT D 2IN D 1IN D V2 1IN C 2IN C OUT C 6 2IN B 5 +IN B 14-Lead SOIC (R Suffix) 14-Lead TSSOP (RU Suffix) OUT A 2IN A 1IN A V1 1N B 2IN B OUT B 7 OUT B OUT A 1 14 OUT D 2IN A 2 13 2IN D +IN A 3 12 +IN D 11 V2 V+ 4 AD8574 +IN B 5 10 +IN C 2IN B 6 9 2IN C 8 OUT C OUT B 7 The AD857x family is specified for the extended industrial/automotive (–40°C to +125°C) temperature range. The AD8571 single is available in 8-lead MSOP and narrow 8-lead SOIC packages. The AD8572 dual amplifier is available in 8-lead narrow SO and 8-lead TSSOP surface mount packages. The AD8574 quad is available in narrow 14-lead SOIC and 14-lead TSSOP packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD8571/AD8572/AD8574–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V S Parameter Symbol INPUT CHARACTERISTICS␣ Offset Voltage VOS Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain1 AVO Offset Voltage Drift ∆VOS /∆T OUTPUT CHARACTERISTICS Output Voltage High VOH Output Voltage Low VOL Short Circuit Limit ISC = 5 V, VCM = 2.5 V, V O = 2.5 V, T A = 25ⴗC unless otherwise noted) Conditions Min –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND –40°C to +125°C RL = 10 kΩ to GND –40°C to +125°C RL = 100 kΩ to V+ –40°C to +125°C RL = 10 kΩ to V+ –40°C to +125°C 0 120 115 125 120 4.99 4.99 4.95 4.95 ± 25 –40°C to +125°C Output Current IO –40°C to +125°C POWER SUPPLY␣ Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE␣ Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE␣ Voltage Noise Voltage Noise Density Current Noise Density PSRR ISY SR VS = 2.7 V to 5.5 V –40°C ≤ TA ≤ +125°C VO = 0 V –40°C ≤ TA ≤ +125°C RL = 10 kΩ GBP en p–p en p–p en in 0 Hz to 10 Hz 0 Hz to 1 Hz f = 1 kHz f = 10 Hz Max Unit 1 5 10 50 1.5 70 200 5 140 130 145 135 0.005 0.04 µV µV pA nA pA pA V dB dB dB dB µV/°C 4.998 4.997 4.98 4.975 1 2 10 15 ± 50 ± 40 ± 30 ± 15 V V V V mV mV mV mV mA mA mA mA 10 1.0 20 150 –40°C ≤ TA ≤ +125°C VCM = 0 V to 5 V –40°C ≤ TA ≤ +125°C RL = 10 kΩ , VO = 0.3 V to 4.7 V –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C Typ 120 115 10 10 30 30 130 130 850 975 1,000 1,075 dB dB µA µA 0.4 0.05 1.5 V/µs ms MHz 1.3 0.41 51 2 0.3 µV p–p µV p–p nV/√Hz fA/√Hz NOTE 1 Gain testing is highly dependent upon test bandwidth. Specifications subject to change without notice. –2– REV. 0 AD8571/AD8572/AD8574 ELECTRICAL CHARACTERISTICS (V S Parameter Symbol INPUT CHARACTERISTICS␣ Offset Voltage VOS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25ⴗC unless otherwise noted) Input Bias Current IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain1 AVO Offset Voltage Drift ∆VOS /∆T OUTPUT CHARACTERISTICS Output Voltage High VOH Output Voltage Low VOL Short Circuit Limit ISC Conditions Min –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND –40°C to +125°C RL = 10 kΩ to GND –40°C to +125°C RL = 100 kΩ to V+ –40°C to +125°C RL = 10 kΩ to V+ –40°C to +125°C 0 115 110 110 105 2.685 2.685 2.67 2.67 ± 10 –40°C to +125°C Output Current IO –40°C to +125°C POWER SUPPLY␣ Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE␣ Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE␣ Voltage Noise Voltage Noise Density Current Noise Density PSRR ISY SR VS = 2.7 V to 5.5 V –40°C ≤ TA ≤ +125°C VO = 0 V –40°C ≤ TA ≤ +125°C 1 5 10 50 1.5 50 200 2.7 130 130 140 130 0.005 0.04 µV µV pA nA pA pA V dB dB dB dB µV/°C 2.697 2.696 2.68 2.675 1 2 10 15 ± 15 ± 10 ± 10 ±5 V V V V mV mV mV mV mA mA mA mA 120 115 130 130 750 950 10 10 20 20 900 1,000 dB dB µA µA 0.5 0.05 1 V/µs ms MHz 0 Hz to 10 Hz f = 1 kHz f = 10 Hz 2.0 94 2 µV p–p nV/√Hz fA/√Hz NOTE 1 Gain testing is highly dependent upon test bandwidth. Specifications subject to change without notice. REV. 0 Unit RL = 10 kΩ GBP en p–p en in Max 10 1.0 10 150 –40°C ≤ TA ≤ +125°C VCM = 0 V to 2.7 V –40°C ≤ TA ≤ +125°C RL = 10 kΩ , VO = 0.3 V to 2.4 V –40°C ≤ TA ≤ +125°C –40°C ≤ TA ≤ +125°C Typ –3– AD8571/AD8572/AD8574 ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltage . . . . . . . . .2. . . . . . . . . . . . . GND to VS + 0.3 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 5.0 V ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V Output Short-Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range AD8571A/AD8572A/AD8574A . . . . . . . . –40°C to +125°C Junction Temperature Range RM, RU and R Packages . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C Package Type JA1 JC Unit 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 8-Lead SOIC (R) 14-Lead TSSOP (RU) 14-Lead SOIC (R) 190 240 158 180 120 44 43 43 36 36 °C/W °C/W °C/W °C/W °C/W NOTE 1 θ JA is specified for worst-case conditions, i.e., θ JA is specified for device in socket for P-DIP packages, θ JA is specified for device soldered in circuit board for SOIC and TSSOP packages. NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less. ORDERING GUIDE Model Temperature Range Package Description Package Option AD8571ARM2 AD8571AR AD8572ARU3 AD8572AR AD8574ARU3 AD8574AR –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C 8-Lead MSOP 8-Lead SOIC 8-Lead TSSOP 8-Lead SOIC 14-Lead TSSOP 14-Lead SOIC RM-8 SO-8 RU-8 SO-8 RU-14 SO-14 Brand1 AJA NOTES 1 Due to package size limitations, these characters represent the part number. 2 Available in reels only. 1,000 or 2,500 pieces per reel. 3 Available in reels only. 2,500 pieces per reel. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8571/AD8572/AD8574 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics– AD8571/AD8572/AD8574 120 100 80 60 40 30 +858C 20 10 +258C 0 210 2408C 220 0 22.5 230 21.5 20.5 1.5 0.5 OFFSET VOLTAGE – mV 2.5 Figure 1. Input Offset Voltage Distribution at 2.7 V 180 500 0 2500 21,000 21,500 5 1 2 3 4 INPUT COMMON-MODE VOLTAGE – V 22,000 NUMBER OF AMPLIFIERS 100 80 60 40 5 VS = 5V TA = 258C VS = 5V VCM = 2.5V TA = 2408C TO +1258C 10 120 1 2 3 4 COMMON-MODE VOLTAGE – V 10k 12 140 0 Figure 3. Input Bias Current vs. Common-Mode Voltage Figure 2. Input Bias Current vs. Common-Mode Voltage VS = 5V VCM = 2.5V TA = 258C 160 0 VS = 5V TA = 1258C 1,000 INPUT BIAS CURRENT – pA 140 20 NUMBER OF AMPLIFIERS 1,500 VS = 5V TA = 2408C, +258C, +858C 40 INPUT BIAS CURRENT – pA NUMBER OF AMPLIFIERS 50 VS = 2.7V VCM = 1.35V TA = 258C OUTPUT VOLTAGE – mV 180 160 8 6 4 1k 100 SOURCE 10 SINK 1 2 20 0 22.5 21.5 20.5 0.5 1.5 OFFSET VOLTAGE – mV 0 Figure 4. Input Offset Voltage Distribution at 5 V 6 100 SOURCE SINK 10 1 0.1 0.0001 0.001 1 0.01 0.1 LOAD CURRENT – mA 10 100 Figure 7. Output Voltage to Supply Rail vs. Output Current at 2.7 V 10 100 1.0 VCM = 2.5V VS = 5V 5V SUPPLY CURRENT – mA INPUT BIAS CURRENT – pA 1k 1 0.01 0.1 LOAD CURRENT – mA Figure 6. Output Voltage to Supply Rail vs. Output Current at 5 V 1,000 VS = 2.7V TA = 258C OUTPUT VOLTAGE – mV 2 3 4 5 1 INPUT OFFSET DRIFT – nV/8C Figure 5. Input Offset Voltage Drift Distribution at 5 V 10k REV. 0 0.1 0.0001 0.001 0 2.5 750 500 250 0.8 2.7V 0.6 0.4 0.2 0 275 250 225 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 8. Bias Current vs. Temperature –5– 0 275 250 225 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 9. Supply Current vs. Temperature 600 500 400 300 200 40 50 0 30 45 20 90 10 135 0 180 210 225 220 270 OPEN-LOOP GAIN – dB 700 40 45 90 10 135 0 180 210 225 220 270 230 230 240 240 10k 2 3 4 SUPPLY VOLTAGE – V 6 5 VS = 2.7V CL = 0pF RL = 2kV 20 AV = 210 10 0 210 AV = +1 220 40 10 230 230 240 100 10k 100k FREQUENCY – Hz 1M 10M Figure 13. Closed Loop Gain vs. Frequency at 2.7 V AV = 210 AV = +1 220 240 100 1k AV = 2100 0 210 VS = 2.7V 240 210 180 150 120 AV = 100 90 AV = 10 60 30 1k 10k 100k FREQUENCY – Hz 1M 100M Figure 12. Open-Loop Gain and Phase Shift vs. Frequency at 5 V 270 30 20 100k 1M 10M FREQUENCY – Hz 300 VS = 5V CL = 0pF RL = 2kV 50 AV = 2100 100M Figure 11. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V CLOSED-LOOP GAIN – dB 50 30 100k 1M 10M FREQUENCY – Hz 60 60 40 10k OUTPUT IMPEDANCE – V 1 0 20 0 0 VS = 5V CL = 0pF RL = 30 100 Figure 10. Supply Current vs. Supply Voltage CLOSED-LOOP GAIN – dB 60 VS = 2.7V CL = 0pF RL = 50 PHASE SHIFT – Degrees TA = 258C 10M Figure 14. Closed Loop Gain vs. Frequency at 5 V AV = 1 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 15. Output Impedance vs. Frequency at 2.7 V 300 OUTPUT IMPEDANCE – V 270 VS = 2.7V CL = 300pF RL = 2kV AV = 1 VS = 5V 240 210 VS = +5V CL = 300pF RL = 2kV AV = 1 180 150 120 AV = 100 90 60 AV = 10 30 0 100 500mV 2ms 5ms 1V AV = 1 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 16. Output Impedance vs. Frequency at 5 V Figure 17. Large Signal Transient Response at 2.7 V –6– Figure 18. Large Signal Transient Response at 5 V REV. 0 PHASE SHIFT – Degrees 60 800 OPEN-LOOP GAIN – dB SUPPLY CURRENT PER AMPLIFIER – mA AD8571/AD8572/AD8574 AD8571/AD8572/AD8574 50 VS = 61.35V CL = 50pF RL = AV = 1 50mV 5ms SMALL SIGNAL OVERSHOOT – % VS = 62.5V CL = 50pF RL = AV = 1 50mV 5ms VS = 61.35V RL = 2kV 40 TA = 258C 45 35 30 +OS 25 2OS 20 15 10 5 0 Figure 19. Small Signal Transient Response at 2.7 V 10 100 1k CAPACITANCE – pF 10k Figure 21. Small Signal Overshoot vs. Load Capacitance at 2.7 V Figure 20. Small Signal Transient Response at 5 V VS = 62.5V RL = 2kV TA = 258C 40 35 VIN 0V VIN 30 25 +OS 2OS VOUT 20 0V VS = 62.5V VIN = 2200mV p-p (RET TO GND) CL = 0pF RL = 10kV AV = 2100 VS = 62.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10kV AV = 2100 0V 15 VOUT 10 0V 20ms 5 0 10 100 1k CAPACITANCE – pF 140 140 VS = 5V CMRR – dB VS = 2.7V 1V 120 120 100 100 80 60 Figure 25. No Phase Reversal 80 60 40 40 20 20 0 100 REV. 0 Figure 24. Negative Overvoltage Recovery Figure 23. Positive Overvoltage Recovery VS = 62.5V RL = 2kV AV = 2100 VIN = 60mV p-p 1V BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV 10k Figure 22. Small Signal Overshoot vs. Load Capacitance at 5 V 200ms 20ms 1V CMRR – dB SMALL SIGNAL OVERSHOOT – % 45 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 26. CMRR vs. Frequency at 2.7 V –7– 0 100 1k 10k 100k FREQUENCY – Hz 1M 10M Figure 27. CMRR vs. Frequency at 5 V AD8571/AD8572/AD8574 140 140 3.0 VS = 62.5V 120 100 100 80 60 2PSRR 40 80 +PSRR 60 +PSRR 2PSRR 40 20 1k 10k 100k FREQUENCY – Hz 1M 0 100 10M Figure 28. PSRR vs. Frequency at ± 1.35 V 5.5 1k 10k 100k FREQUENCY – Hz 4.5 4.0 2.0 1.5 1.0 0 100 10M 1M Figure 29. PSRR vs. Frequency at ± 2.5 V VS = 62.5V RL = 2kV AV = 1 THD+N < 1% TA = 258C 5.0 VS = 61.35V RL = 2kV AV = 1 THD+N < 1% TA = 258C 0.5 20 0 100 OUTPUT SWING – V p-p 2.5 OUTPUT SWING – V p-p 120 PSRR – dB PSRR – dB VS = 61.35V 1k 10k 100k FREQUENCY – Hz 1M Figure 30. Maximum Output Swing vs. Frequency at 2.7 V VS = 62.5V AV = 120,000 VS = 61.35V AV = 120,000 3.5 0V 3.0 2.5 2.0 1.5 1.0 50mV 1s 50mV 1s 0.5 0 100 1k 10k 100k FREQUENCY – Hz 1M Figure 31. Maximum Output Swing vs. Frequency at 5 V Figure 32. 0.1 Hz to 10 Hz Noise at 2.7 V VS = 2.7V RS = 0V 364 VS = 2.7V RS = 0V 112 156 208 156 en – nV/ Hz en – nV/ Hz 260 130 80 104 64 48 78 104 32 52 52 16 26 0 0.5 1.0 1.5 FREQUENCY – kHz 2.0 Figure 34. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz 2.5 VS = 5V RS = 0V 182 96 312 en – nV/ Hz Figure 33. 0.1 Hz to 10 Hz Noise at 5 V 0 5 10 15 FREQUENCY – kHz 20 Figure 35. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz –8– 25 0 0.5 1.0 1.5 FREQUENCY – kHz 2.0 Figure 36. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz REV. 0 2.5 AD8571/AD8572/AD8574 150 180 en – nV/ Hz 80 64 48 150 120 90 32 60 16 30 0 5 10 15 FREQUENCY – kHz 20 25 0 Figure 37. Voltage Noise Density at 5 V from 0 Hz to 25 kHz ISC2 20 10 0 210 220 ISC+ 230 240 SHORT-CIRCUIT CURRENT – mA 30 80 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 40. Output Short-Circuit Current vs. Temperature 60 ISC2 40 20 0 220 ISC+ 240 260 2100 275 250 225 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 41. Output Short-Circuit Current vs. Temperature OUTPUT VOLTAGE SWING – mV VS = 5V 200 175 RL = 1kV 150 125 100 75 50 25 0 275 250 225 RL = 10kV RL = 100kV 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 43. Output Voltage to Supply Rail vs. Temperature REV. 0 130 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 39. Power-Supply Rejection vs. Temperature 225 VS = 5V 200 175 150 125 –9– RL = 1kV 100 75 50 25 250 225 135 250 VS = 5V 280 250 275 250 225 140 125 275 250 225 100 VS = 2.7V VS = 2.7V TO 5.5V 145 10 Figure 38. Voltage Noise Density at 5 V from 0 Hz to 10 Hz 50 40 5 FREQUENCY – Hz OUTPUT VOLTAGE SWING – mV en – nV/ Hz 96 SHORT-CIRCUIT CURRENT – mA VS = 5V RS = 0V 210 POWER SUPPLY REJECTION – dB VS = 5V RS = 0V 112 0 275 250 225 RL = 10kV RL = 100kV 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 42. Output Voltage to Supply Rail vs. Temperature AD8571/AD8572/AD8574 FUNCTIONAL DESCRIPTION The AD857x family are CMOS amplifiers that achieve their high degree of precision through random frequency autozero stabilization. The autocorrection topology allows the AD857x to maintain its low offset voltage over a wide temperature range, and the randomized autozero clock eliminates any intermodulation distortion (IMD) errors at the amplifier’s output. The AD857x can be run from a single supply voltage as low as 2.7 V. The extremely low offset voltage of 1 µV and no IMD products allows the amplifier to be easily configured for high gains without risk of excessive output voltage errors. This makes the AD857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/°C ensures a minimum of offset voltage error over its entire temperature range of –40°C to +125°C. These combined features make the AD857x an excellent choice for a variety of sensitive measurement and automotive applications. Amplifier Architecture Each AD857x op amp consists of two amplifiers, a main amplifier and a secondary amplifier, used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their rds. Simply put, the output voltage will not swing as close to the rail under heavy output current conditions as it will with light output current. This is a characteristic of all rail-to-rail output amplifiers. Figures 6 and 7 show how close the output voltage can get to the rails with a given output current. The output of the AD857x is short circuit protected to approximately 50 mA of current. As noted in the previous section on amplifier architecture, each AD857x op amp contains two internal amplifiers. One is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figures 44 and 45 these are labeled as VOSX, where x denotes the amplifier associated with the offset; A for the nulling amplifier, B for the primary amplifier. The openloop gain for the +IN and –IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX . There are two modes of operation determined by the action of two sets of switches in the amplifier: An autozero phase and an amplification phase. Autozero Phase In this phase, all φA switches are closed and all φB switches are opened. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier, which maintains a potential difference between the +IN and –IN inputs. The nulling amplifier feedback loop is closed through φA2 and VOSA appears at the output of the nulling amp and on CM1, an internal capacitor in the AD857x. Mathematically, we can express this in the time domain as: [] Autocorrection amplifiers are not a new technology. Various IC implementations have been available for over 15 years and some improvements have been made over time. The AD857x design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD857x is able to offer extremely low offset voltages and high open-loop gains. [] (1) which can be expressed as, [] VOA t = [] AAVOSA t (2) 1 + BA This shows us that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the CM1 capacitor. VIN+ AB VIN2 FA VOUT BB FB The AD857x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. Open-loop gain will decrease with smaller load resistances. This is another characteristic of rail-to-rail output amplifiers. Basic Autozero Amplifier Theory [] VOA t = AAVOSA t − BAVOA t VOA VOSA + CM2 FB AA VNB 2BA FA CM1 VNA Figure 44. Autozero Phase of the AD857x Amplification Phase When the φB switches close and the φA switches open for the amplification phase, this offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier. The voltage across CM1 is designated as VNA. Let us also designate VIN as the potential difference between the two inputs to the primary amplifier, or VIN = (VIN+ – VIN–). Now the output of the nulling amplifier can be expressed as: [] ( [] [ ]) [] VOA t = AA VIN t − VOSA t − BAVNA t –10– (3) REV. 0 AD8571/AD8572/AD8574 The AD857x architecture is optimized in such a way that AA = AB and B A = BB and BA >> 1. Also, the gain product to AABB is much greater than AB . These allow Equation 10 to be simplified to: VIN+ AB VIN2 VOUT BB FB FA VOSA + FB VOA CM2 [] 2BA FA VNA Figure 45. Output Phase of the Amplifier ( VOUT = k × VIN + VOS , Because φA is now open and there is no place for CM1 to discharge, the voltage VNA at the present time t is equal to the voltage at the output of the nulling amp VOA at the time when φA was closed. If we call the period of the autocorrection switching frequency TS , then the amplifier switches between phases every 0.5␣ ⫻␣ TS. Therefore, in the amplification phase: [] [] [] [] [] [] [] AA (1 + BA ) VOSA − AABAVOSA 1 + BA (5) (6) or, V VOA t = AA VIN t + OSA 1 + BA [] [] (7) ( [] ) VOUT t = AB VIN t + VOSB + BBVNB (8) In the amplification phase, VOA = VNB, so this can be rewritten as: V VOUT t = ABVIN t + ABVOSB + BB AA VIN t + OSA (9) 1 + BA [] [] [] Combining terms, [] [] VOUT t = VIN t ( AB + AABB ) + REV. 0 (12) EFF AA BA (13) EFF ≈ VOSA + VOSB BA (14) Thus, the offset voltages of both the primary and nulling amplifiers are reduced by the gain factor BA. This takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. This autocorrection scheme is what makes the AD857x family of amplifiers among the most precise amplifiers in the world. High Gain, CMRR, PSRR Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the previous section, the autocorrection architecture of the AD857x allows it to quite effectively minimize offset voltages. The technique also corrects for offset errors caused by common-mode voltage swings and power supply variations. This results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the device’s entire temperature range, from –40°C to +125°C. Maximizing Performance Through Proper Layout We can already get a feel for the autozeroing in action. Note the VOS term is reduced by a 1 + BA factor. This shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Now the primary amplifier output voltage is the voltage at the output of the AD857x amplifier. It is equal to: [] ) And from here, it is easy to see that: VOS , For the sake of simplification, let us assume that the autocorrection frequency is much faster than any potential change in VOSA or VOSB. This is a good assumption since changes in offset voltage are a function of temperature variation or long-term wear time, both of which are much slower than the auto-zero clock frequency of the AD857x. This effectively makes VOS time invariant and we can rearrange Equation 5 and rewrite it as: VOA t = AAVIN t + [] VOUT t ≈ VIN t AABA + VOS , And substituting Equation 4 and Equation 2 into Equation 3 yields: VOA t = AAVIN t + AAVOSA EFF Where k is the open-loop gain of an amplifier and VOS, EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives us: (4) 1 AABAVOSA t − TS 2 t − 1 + BA (11) Most obvious is the gain product of both the primary and nulling amplifiers. This AABA term is what gives the AD857x its extremely high open-loop gain. To understand how VOSA and VOSB relate to the overall effective input offset voltage of the complete amplifier, we should set up the generic amplifier equation of: CM1 1 VNA t = VNA t − TS 2 [] VOUT t ≈ VIN t AABA + AA (VOSA + VOSB ) VNB AA AABBVOSA + ABVOSB 1 + BA To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD857x, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 46 shows how the guard ring should be configured and Figure 47 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the noninverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. (10) –11– AD8571/AD8572/AD8574 RF R1 VOUT VIN VOUT VIN AD8572 AD8572 VOUT VIN R S = R1 AD857x A V = 1 + (RF /R1) NOTE: RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES VIN VOUT AD8572 Figure 49. Using Dummy Components to Cancel Thermoelectric Voltage Errors Figure 46. Guard Ring Layout and Connections to Reduce PC Board Leakage Currents 1/f Noise Characteristics Another advantage of autozero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for subHertz frequencies or dc precision applications. V+ R2 R1 AD8572 VIN1 R2 R1 VIN2 GUARD RING GUARD RING VREF VREF V2 Figure 47. Top View of AD8572 SOIC Layout with Guard Rings Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the temperature of the junction. The most common metallic junctions on a circuit board are solder-to-board trace and solderto-component lead. Figure 48 shows a cross-section diagram view of the thermal voltage error sources. If the temperature of the PC board at one end of the component (TA1) is different from the temperature at the other end (TA2), the Seebeck voltages will not be equal, resulting in a thermal voltage error. This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner will ensure both Seebeck voltages are equal, thus canceling the thermocouple error. Maintaining a constant ambient temperature on the circuit board will further reduce this error. The use of a ground plane will help distribute heat throughout the board and will also reduce EMI noise pickup. COMPONENT LEAD VSC1 VTS1 2 2 SURFACE MOUNT COMPONENT + + + VSC2 2 + Because the AD857x amplifiers are self-correcting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced as a result of autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases. This allows the AD857x to have lower noise near dc than standard low-noise amplifiers that are susceptible to 1/f noise. Random Autozero Correction Eliminates Intermodulation Distortion The AD857x can be used as a conventional op amp for gains up to 1 MHz. The autozero correction frequency of the device continuously varies, based on a pseudo-random generator with a uniform distribution from 2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization of intermodulation distortion (IMD) products, which show up as simple broadband noise at the output of the amplifier. This noise naturally combines with the amplifier’s voltage noise in a root-squared-sum fashion, resulting in an output free of IMD. Figure 50a shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded. Figure 50b shows the spectral output with the amplifier configured for a gain of 60 dB. SOLDER VTS2 2 PC BOARD TA1 COPPER TRACE TA2 IF TA1 = TA2, THEN VTS1 + VSC1 = VTS2 + VSC2 Figure 48. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error –12– REV. 0 AD8571/AD8572/AD8574 Broadband and External Resistor Noise Considerations 0 The total broadband noise output from any amplifier is primarily a function of three types of noise: Input voltage noise from the amplifier, input current noise from the amplifier and Johnson noise from the external resistors used around the amplifier. Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a root-squared-sum fashion. The full equation is given as: VS = 5V AV = 0dB 220 OUTPUT SIGNAL 240 260 280 2100 2120 2140 2160 0 1 2 3 4 5 6 7 FREQUENCY – kHz 8 9 2 2 e n, TOTAL = e n + 4kTrs + (inrs ) 10 0 VS = 5V AV = 60dB The input voltage noise density, en, of the AD857x is 51 nV/√Hz, and the input noise, in , is 2 fA/√Hz. The en, TOTAL will be dominated by input voltage noise provided the source resistance is less than 172 kΩ. With source resistance greater than 172 kΩ, the overall noise of the system will be dominated by the Johnson noise of the resistor itself. OUTPUT SIGNAL 240 260 280 Because the input current noise of the AD857x is very small, in does not become a dominant term unless rs is greater than 4 GΩ, which is an impractical value of source resistance. 2100 2120 0 1 2 3 4 5 6 7 FREQUENCY – kHz 8 9 The total noise, en, TOTAL, is expressed in volts-per-square-root Hertz, and the equivalent rms noise over a certain bandwidth can be found as: 10 Figure 50b. Spectral Analysis of AD857x Output with 60 dB Gain e n = e n, Figure 51 shows the spectral output of an AD8572 configured in a high gain (60 dB) with a 1 mV input signal applied. Note the absence of any IMD products in the spectrum. The signalto-noise (SNR) ratio of the output signal is better than 60 dB, or 0.1%. The AD857x amplifiers have an excellent overdrive recovery of only 200 µs from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers, as the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output. Figure 23 and Figure 24 show the positive and negative overdrive recovery time for the AD857x. OUTPUT SIGNAL 260 280 2100 1 2 3 4 5 6 7 FREQUENCY – kHz 8 9 10 Figure 51. Spectral Analysis of AD857x in High Gain with an Input Signal REV. 0 (16) Output Overdrive Recovery 240 0 × BW For a complete treatise on circuit noise analysis, please refer to the 1995 Linear Design Seminar book available from Analog Devices. VS = 5V AV = 60dB 220 TOTAL Where BW is the bandwidth of interest in Hertz. 0 2120 (15) Where, en = The input voltage noise of the amplifier, in = The input current noise of the amplifier, rs = Source resistance connected to the noninverting terminal, k = Boltzmann’s constant (1.38 ⫻ 10-23 J/K) T = Ambient temperature in Kelvin (K = 273.15 + °C) Figure 50a. Spectral Analysis of AD857x Output in Unity Gain Configuration 220 1 2 The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to half-way between the supplies. The time from the input signal step-down to the output settling to within 100 µV of its final value is the overdrive recovery time. Most competitors’ autocorrection amplifiers require a number of autozero clock cycles to recover from output overdrive and some can take several milliseconds for the output to settle properly. –13– AD8571/AD8572/AD8574 Input Overvoltage Protection Although the AD857x is a rail-to-rail input amplifier, care should be taken to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier will correct its output to ensure the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials. This could cause excessive current to flow through internal diodes in the AD857x used to protect the input stage against overvoltage. Although the snubber will not recover the loss of amplifier bandwidth from the load capacitance, it will allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 53 shows the output of an AD857x driving a 1 nF capacitor with and without a snubber network. 10ms WITH SNUBBER If either input exceeds either supply rail by more than 0.3 V, large amounts of current will begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes will become forward-biased. Without current-limiting, excessive amounts of current could flow through these diodes causing permanent damage to the device. If inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA maximum. Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage is moved outside of the common-mode range, the outputs of these amplifiers will suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down, causing a radical shifting of internal voltages which results in the erratic output behavior. 100mV Figure 53. Overshoot and Ringing are Substantially Reduced Using a Snubber Network Table I. Snubber Network Values for Driving Capacitive Loads The AD857x amplifier has been carefully designed to prevent any output phase reversal, provided both inputs are maintained within the supply voltages. If one or both inputs could exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 mA. This will ensure the output will not reverse its phase. The AD857x has excellent capacitive load-driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading will limit the bandwidth of the amplifier. Capacitive loads will also increase the amount of overshoot and ringing at the output. An R-C snubber network, Figure 52, can be used to compensate the amplifier against capacitive load ringing and overshoot. VS = 5V CLOAD = 4.7nF The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically since actual CLOAD will include stray capacitances and may differ substantially from the nominal capacitive load. Table I shows some snubber network values that can be used as starting points. Output Phase Reversal Capacitive Load Drive WITHOUT SNUBBER CLOAD RX CX 1 nF 4.7 nF 10 nF 200 Ω 60 Ω 20 Ω 1 nF 0.47 µF 10 µF Power-Up Behavior On power-up, the AD857x will settle to a valid output within 5 µs. Figure 54a shows an oscilloscope photo of the output of the amplifier along with the power supply voltage, and Figure 54b shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 µs to settle to its final output voltage. This turn-on response time is much faster than most other autocorrection amplifiers, which can take hundreds of microseconds or longer for their output to settle. 5V VOUT VOUT AD857x VIN 200mV p-p RX 60V CX 0.47mF 0V CL 4.7nF V+ 0V Figure 52. Snubber Network Configuration for Driving Capacitive Loads 5ms 1V BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV Figure 54a. AD857x Output Behavior on Power-Up –14– REV. 0 AD8571/AD8572/AD8574 R2 VSY = 0V TO 5V R1 V2 100kV VOUT R3 V1 VOUT 100kV R4 AD857x IF Figure 54b. AD857x Test Circuit for Turn-On Time A REF192 provides a 2.5 V precision reference voltage for A2. The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain-gage resistor bridge. Q1 provides the current drive for the 350 Ω bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to: 2 × (R1 + R2 ) = R2 R1 , THEN VOUT = AV = R2 R1 2 2.5V 6 1kV REF192 3 40mV FULL-SCALE CMRRMIN = 20kV A1 AD8572-A R3 17.4kV NOTE: USE 0.1% TOLERANCE RESISTORS. AD8574-A V2 R2 100V R1 17.4kV VOUT 0V TO 4V RG R4 100V V1 R R R R AD8574-B VOUT = 1 + Figure 55. A 5 V Precision Strain-Gage Amplifier 3 V Instrumentation Amplifier 1 2δ (22) R VOUT R AD8574-C RTRIM 2R (V1 2 V2) RG Figure 57. A Discrete Instrumentation Amplifier Configuration The high common-mode rejection, high open-loop gain, and operation down to 3 V of supply voltage makes the AD857x an excellent choice of op amp for discrete single supply instrumentation amplifiers. The common-mode rejection ratio of the AD857x is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 56 is given as: R4 R2 R1 VOUT = V 1 1 + − V 2 R2 R3 + R4 R1 (21) In the 3 op amp instrumentation amplifier configuration shown in Figure 57, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as δ, the worst-case CMRR of the instrumentation amplifier will be: 4 4.0V (20) R1R4 + 2R2R4 + R2R3 2R1R4 − 2R2R3 A2 AD8572-B (19) Due to finite component tolerance the ratio between the four resistors will not be exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring to Figure 56, the exact common-mode rejection ratio can be expressed as: Where R B is the resistance of the load cell. Using the values given in Figure 55, the output voltage will linearly vary from 0 V with no strain to 4 V under full strain. 5V R2 R4 = R1 R3 VOUT = AV (V 1 − V 2) CMRR = 12kV 3 (V1 2 V2) Which sets the output voltage of the system to: (17) RB 350V LOAD CELL R3 In an ideal difference amplifier, the ratio of the resistors are set exactly equal to: The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain-gage. Figure 55 shows a configuration for a single supply, precision strain-gage measurement system. Q1 2N2222 OR EQUIVALENT R4 Figure 56. Using the AD857x as a Difference Amplifier APPLICATIONS A 5 V Precision Strain-Gage Circuit REV. 0 AD857x Thus, using 1% tolerance resistors would result in a worst-case system CMRR of 0.02, or 34 dB. Therefore either high precision resistors or an additional trimming resistor, as shown in Figure 57, should be used to achieve high common-mode rejection. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance would require a series trimming resistor equal to 100 Ω. (18) –15– AD8571/AD8572/AD8574 A High Accuracy Thermocouple Amplifier Figure 58 shows a K-type thermocouple amplifier configuration with cold-junction compensation. Even from a 5 V supply, the AD8571 can provide enough accuracy to achieve a resolution of better than 0.02°C from 0°C to 500°C. D1 is used as a temperature measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring tip immersed in a zero-degree ice bath, R6 should be adjusted until the output is at 0 V. Figure 60 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8572 will be at or near ground. Again, a 0.1 Ω resistor provides a voltage drop proportional to the return current. The output voltage is given as: R VOUT = V + − 2 × RSENSE × I L R1 For the component values shown in Figure 60, the output transfer function decreases from V at –2.5 V/A. Using the values shown in Figure 58, the output voltage will track temperature at 10 mV/°C. For a wider range of temperature measurement, R 9 can be decreased to 62 kΩ. This will create a 5 mV/°C change at the output, allowing measurements of up to 1000°C. 6 2 12V V+ 0.1mF R1 100V 3 4 R5 40.2kV R9 124kV 5V 1N4148 D1 – + R2 2.74kV R8 453V 2 R4 5.62kV D MONITOR OUTPUT R2 2.49kV 10mF + Figure 59. A High-Side Load Current Monitor 0.1mF 8 V+ 1 R6 200V 1 G M1 Si9433 R1 10.7kV – 8 1/2 AD8572 5V 4 + IL 3V S 0.1mF K-TYPE THERMOCOUPLE 40.7mV/8C RSENSE 0.1V 3V 2 REF02EZ (24) 3 R3 53.6V 4 AD8571 R2 2.49kV 0V TO 5V (08C TO 5008C) VOUT Q1 V+ Figure 58. A Precision K-Type Thermocouple Amplifier with Cold-Junction Compensation Precision Current Meter Because of its low input bias current and superb offset voltage at single supply voltages, the AD857x is an excellent amplifier for precision current monitoring. Its rail-to-rail input allows the amplifier to be used as either a high-side or low-side current monitor. Using both amplifiers in the AD8572 provides a simple method to monitor both current supply and return paths for load or fault detection. Figure 59 shows a high-side current monitor configuration. Here, the input common-mode voltage of the amplifier will be at or near the positive supply voltage. The amplifier’s rail-to-rail input provides a precise measurement, even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error. The 0.1 Ω resistor creates a voltage drop to the noninverting input of the AD857x. The amplifier’s output is corrected until this voltage appears at the inverting input. This creates a current through R1, which in turn flows through R2. The Monitor Output is given by: R Monitor Output = R2 × SENSE × I L R1 R1 100V 1/2 AD8572 RSENSE 0.1V RETURN TO GROUND Figure 60. A Low-Side Load Current Monitor Precision Voltage Comparator The AD857x can be operated open-loop and used as a precision comparator. The AD857x has less than 50 µV of offset voltage when run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 µs on the rising edge and 8 µs on the falling edge. Care should be taken to ensure the maximum differential voltage of the device is not exceeded. For more information, please refer to the section on Input Overvoltage Protection. (23) Using the components shown in Figure 59, the Monitor Output transfer function is 2.5␣ V/A. –16– REV. 0 AD8571/AD8572/AD8574 The network around ECM1 creates the common-mode voltage error, with CCM1 setting the corner frequency for the CMRR roll-off. The power supply rejection error is created by the network around EPS1, with CPS3 establishing the corner frequency for the PSRR roll-off. The two current loops around nodes 80 and 81 are used to create a 51 nV/√Hz noise figure across RN2. All three of these error sources are reflected to the input of the op amp model through EOS. Finally, GSY is used to accurately model the supply current versus supply voltage increase in the AD857x. SPICE Model The SPICE macro-model for the AD857x amplifier is given in Listing 1. This model simulates the typical specifications for the AD857x, and it can be downloaded from the Analog Devices website at http://www.analog.com. The schematic of the macro-model is shown in Figure 61. Transistors M1 through M4 simulate the rail-to-rail input differential pairs in the AD857x amplifier. The EOS voltage source in series with the noninverting input establishes not only the 1 µV offset voltage, but is also used to establish common-mode and power supply rejection ratios and input voltage noise. The differential voltages from nodes 14 to 16 and nodes 17 to 18 are reflected to E1, which is used to simulate a secondary pole-zero combination in the open-loop gain of the amplifier. This macro-model has been designed to accurately simulate a number of specifications exhibited by the AD857x amplifier, and is one of the most true-to-life macro-models available for any op amp. It is optimized for operation at 27°C. Although the model will function at different temperatures, it may lose accuracy with respect to the actual behavior of the AD857x. The voltage at node 32 is then reflected to G1, which adds an additional gain stage and, in conjunction with CF, establishes the slew rate of the model at 0.5 V/µs. M5 and M6 are in a common-source configuration, similar to the output stage of the AD857x amplifier. EG1 and EG2 fix the quiescent current in these two transistors at 100 µA, and also help accurately simulate the VOUT vs. IOUT characteristic of the amplifier. CCM1 99 RCM1 21 D1 2 99 RC7 98 RC8 C2 + M1 81 VN1 RC4 11 2 + EOS RN2 M2 12 M3 HN RN1 2 RC3 7 80 18 17 1 RCM2 ECM1 V1 8 22 + I1 9 M4 2 98 10 99 RC1 D2 I2 13 V1 CPS3 RC2 99 CPS1 70 RPS1 50 C1 16 RC5 RC6 2 0 GSY 14 EPS1 + RPS2 71 50 RPS3 72 73 RPS4 98 CPS2 50 99 50 + 98 C2 2 R2 45 D4 51 EVN 98 98 2 47 98 2 R1 G1 CF + EREF D3 30 R3 97 2 + 32 M5 46 M6 + 31 + E1 2 EG1 2 EVP + EG2 50 0 Figure 61. Schematic of the AD857x SPICE Macro-Model REV. 0 –17– AD8571/AD8572/AD8574 SPICE macro-model for the AD857x * AD8572 SPICE Macro-model * Typical Values * 7/99, Ver. 1.0 * TAM / ADSC * * Copyright 1999 by Analog Devices * * Refer to “README.DOC” file for License * Statement. Use of this model indicates * your acceptance of the terms and * provisions in the License Statement. * * Node Assignments * noninverting input * | inverting input * | | positive supply * | | | negative supply * | | | | output * | | | | | * | | | | | .SUBCKT AD8572 1 2 99 50 45 * * INPUT STAGE * M1 4 7 8 8 PIX L=1E-6 W=355.3E-6 M2 6 2 8 8 PIX L=1E-6 W=355.3E-6 M3 11 7 10 10 NIX L=1E-6 W=355.3E-6 M4 12 2 10 10 NIX L=1E-6 W=355.3E-6 RC1 4 14 9E+3 RC2 6 16 9E+3 RC3 17 11 9E+3 RC4 18 12 9E+3 RC5 14 50 1E+3 RC6 16 50 1E+3 RC7 99 17 1E+3 RC8 99 18 1E+3 C1 14 16 30E-12 C2 17 18 30E-12 I1 99 8 100E-6 I2 10 50 100E-6 V1 99 9 0.3 V2 13 50 0.3 D1 8 9 DX D2 13 10 DX EOS 7 1 POLY(3) (22,98) (73,98) (81,98) + 1E-6 1 1 1 IOS 1 2 2.5E-12 * * CMRR 120dB, ZERO AT 20Hz * ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5 RCM1 21 22 50E+6 CCM1 21 22 159E-12 RCM2 22 98 50 * * PSRR=120dB, ZERO AT 1Hz * RPS1 70 0 1E+6 RPS2 71 0 1E+6 CPS1 99 70 1E-5 CPS2 50 71 1E-5 EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1 RPS3 72 73 15.9E+6 CPS3 72 73 10E-9 RPS4 73 98 16 * VOLTAGE NOISE REFERENCE OF 51nV/rt(Hz) * VN1 80 98 0 RN1 80 98 16.45E-3 HN 81 98 VN1 51 RN2 81 98 1 * * INTERNAL VOLTAGE REFERENCE * EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5 GSY 99 50 (99,50) 48E-6 EVP 97 98 (99,50) 0.5 EVN 51 98 (50,99) 0.5 * * LHP ZERO AT 7MHz, POLE AT 50MHz * E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814 R2 32 33 3.7E+3 R3 33 98 22.74E+3 C3 32 33 1E-12 * * GAIN STAGE * G1 98 30 (33,98) 22.7E-6 R1 30 98 259.1E+6 CF 45 30 45.4E-12 D3 30 97 DX D4 51 30 DX * * OUTPUT STAGE * M5 45 46 99 99 POX L=1E-6 W=1.111E-3 M6 45 47 50 50 NOX L=1E-6 W=1.6E-3 EG1 99 46 POLY(1) (98,30) 1.1936 1 EG2 47 50 POLY(1) (30,98) 1.2324 1 * * MODELS * .MODEL POX PMOS (LEVEL=2,KP=10E-6, + VTO=-1,LAMBDA=0.001,RD=8) .MODEL NOX NMOS (LEVEL=2,KP=10E-6, + VTO=1,LAMBDA=0.001,RD=5) .MODEL PIX PMOS (LEVEL=2,KP=100E-6, + VTO=-1,LAMBDA=0.01) .MODEL NIX NMOS (LEVEL=2,KP=100E-6, + VTO=1,LAMBDA=0.01) .MODEL DX D(IS=1E-14,RS=5) .ENDS AD8572 –18– REV. 0 AD8571/AD8572/AD8574 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (R Suffix) 0.1968 (5.00) 0.1890 (4.80) 0.122 (3.10) 0.114 (2.90) 8 8 0.199 (5.05) 0.187 (4.75) 1 4 4 PIN 1 0.0098 (0.25) 0.0040 (0.10) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.006 (0.15) 0.002 (0.05) 5 0.1574 (4.00) 0.1497 (3.80) 1 5 0.122 (3.10) 0.114 (2.90) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.011 (0.28) 0.003 (0.08) 338 278 8° 0° 0.0500 (1.27) 0.0160 (0.41) 0.028 (0.71) 0.016 (0.41) 14-Lead TSSOP (RU Suffix) 0.201 (5.10) 0.193 (4.90) 14 8 1 7 4 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 5 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) 0.122 (3.10) 0.114 (2.90) 1 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 8-Lead TSSOP (RU Suffix) 8 C3734–2.5–10/99 8-Lead MSOP (RM Suffix) PIN 1 0.006 (0.15) 0.002 (0.05) PIN 1 0.0256 (0.65) BSC 0.0118 (0.30) SEATING PLANE 0.0075 (0.19) 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.006 (0.15) 0.002 (0.05) 88 08 0.028 (0.70) 0.020 (0.50) SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) 0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80) 14 8 1 7 PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0500 SEATING (1.27) PLANE BSC REV. 0 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 0.0099 (0.25) 0.0075 (0.19) –19– 0.0196 (0.50) x 458 0.0099 (0.25) 88 08 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 14-Lead SOIC (R Suffix)