ETC UPD703106AGJ(A)-XXX-UEN

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703103A, 703105A, 703106A,
703106A(A), 703107A, 703107A(A)
TM
V850E/MA1
32-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703103A, 703105A, 703106A, 703106A(A), 703107A, and 703107A(A) are products of the V850 Series
TM
of 32-bit single-chip microcontroller for real-time control applications. These microcontrollers integrate a 32-bit CPU,
ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a DMA controller, and
other functions on a single chip.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MA1 Hardware User's Manual:
U14359E
V850E1 Architecture User's Manual:
U14559E
FEATURES
{ Number of instructions: 83
{ Minimum instruction execution time: 20 ns (50 MHz internal operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set optimized for control applications
Internal memory
ROM: None (µPD703103A)
128 KB (µPD703105A, 703106A, 703106A(A))
256 KB (µPD703107A, 703107A(A))
RAM: 4 KB (µPD703103A, 703105A)
10 KB (µPD703106A, 703106A(A), 703107A, 703107A(A))
{ Memory access control (supporting EDO DRAM, SDRAM, and page ROM)
{ Advanced internal interrupt controller
{ Real-time pulse unit suitable for control operations
{ Powerful serial interface (with dedicated internal baud rate generator)
{ On-chip clock generator
{ 10-bit resolution A/D converter: 8 channels
{ DMA controller: 4 channels
{ Power saving functions
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15578EJ1V0DS00 (1st edition)
Date Published January 2002 N CP(K)
Printed in Japan
©
2002
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
APPLICATIONS
{ Office machines (such as ink jet printers, facsimiles, and PPCs)
{ Multimedia systems (such as digital still cameras, DVD players, and video printers)
ORDERING INFORMATION
Part Number
Package
Quality Grade
µPD703103AGJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Standard
µPD703105AGJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Standard
µPD703106AGJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Standard
µPD703107AGJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Standard
µPD703106AF1-×××-EN4
161-pin plastic FBGA (13 × 13)
Standard
161-pin plastic FBGA (13 × 13)
Standard
µPD703106AGJ(A)-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Special
µPD703107AGJ(A)-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Special
µPD703107AF1-×××-EN4
Note
Note
Note
Under development
Remark ××× indicates ROM code suffix.
The µPD703106A, 703107A and µPD703106A(A), 703107A(A) differ in the quality grade only.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
PIN CONFIGURATION (TOP VIEW)
• 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703106AGJ(A)-×××-UEN
µPD703105AGJ-×××-UEN
µPD703107AGJ-×××-UEN
µPD703106AGJ-×××-UEN
µPD703107AGJ(A)-x×××-UEN
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PDL15/D15
PAL0/A0
PAL1/A1
PAL2/A2
PAL3/A3
PAL4/A4
PAL5/A5
PAL6/A6
PAL7/A7
VSS
VDD
PAL8/A8
PAL9/A9
PAL10/A10
PAL11/A11
PAL12/A12
PAL13/A13
PAL14/A14
PAL15/A15
VSS
VDD
PAH0/A16
PAH1/A17
PAH2/A18
PAH3/A19
PAH4/A20
PAH5/A21
PAH6/A22
PAH7/A23
PAH8/A24
PAH9/A25
VSS
VDD
PCD0/SDCKE
PCD1/SDCLK
PCD2/LBE/SDCAS
µPD703103AGJ-UEN
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PCD3/UBE/SDRAS
PCS0/CS0
PCS1/CS1/RAS1
PCS2/CS2/IOWR
PCS3/CS3/RAS3
PCS4/CS4/RAS4
PCS5/CS5/IORD
PCS6/CS6/RAS6
PCS7/CS7
VSS
VDD
PCT0/LCAS/LWR/LDQM
PCT1/UCAS/UWR/UDQM
PCT4/RD
PCT5/WE
PCT6/OE
PCT7/BCYST
PCM0/WAIT
PCM1/CLKOUT/BUSCLK
PCM2/HLDAK
PCM3/HLDRQ
PCM4/REFRQ
PCM5/SELFREF
P50/INTP030/TI030
P51/INTP031
P52/TO03
VSS
VDD
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDD
VSS
TC3/INTP113/P27
TC2/INTP112/P26
TC1/INTP111/P25
TC0/INTP110/P24
TO02/P23
INTP021/P22
TI020/INTP020/P21
NMI/P20
VDD
VSS
ADTRG/INTP123/P37
INTP122/P36
INTP121/P35
RXD2/INTP120/P34
TXD2/INTP133/P33
SCK2/INTP132/P32
SI2/INTP131/P31
SO2/INTP130/P30
MODE1
MODE0
RESET
CKSEL
CVDD
X2
X1
CVSS
SCK1/P45
RXD1/SI1/P44
TXD1/SO1/P43
SCK0/P42
RXD0/SI0/P41
TXD0/SO0/P40
AVDD/AVREF
AVSS
D14/PDL14
D13/PDL13
D12/PDL12
D11/PDL11
D10/PDL10
D9/PDL9
D8/PDL8
VDD
VSS
D7/PDL7
D6/PDL6
D5/PDL5
D4/PDL4
D3/PDL3
D2/PDL2
D1/PDL1
D0/PDL0
MODE2
DMARQ3/INTP103/P07
DMARQ2/INTP102/P06
DMARQ1/INTP101/P05
DMARQ0/INTP100/P04
TO00/P03
INTP001/P02
TI000/INTP000/P01
PWM0/P00
VDD
VSS
DMAAK3/PBD3
DMAAK2/PBD2
DMAAK1/PBD1
DMAAK0/PBD0
TO01/P13
INTP011/P12
TI010/INTP010/P11
PWM1/P10
Data Shee U15578EJ1V0DS
3
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
• 161-pin plastic FBGA (13 × 13)
µPD703106AF1-×××-EN4
µPD703107AF1-×××-EN4
Top view
Bottom view
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A BCDE FGH J K LMNP
PNML K J HGF EDCB A
Index mark
Index mark
(1/2)
Pin No.
Pin Name
−
A1
Pin No.
Pin Name
Pin No.
Pin Name
B10
A21/PAH5
D5
A6/PAL6
A2
D15/PDL15
B11
A25/PAH9
D6
A10/PAL10
A3
A2/PAL2
B12
SDCLK/PCD1
D7
A14/PAL14
A4
A5/PAL5
B13
CS1/RAS1/PCS1
D8
A16/PAH0
B14
−
D9
A20/PAH4
A6
A9/PAL9
−
C1
−
D10
A23/PAH7
A7
A12/PAL12
C2
D9/PDL9
D11
SDCKE/PCD0
A8
A15/PAL15
C3
D13/PDL13
D12
CS0/PCS0
A9
A17/PAH1
C4
A1/PAL1
D13
CS5/IORD/PCS5
C5
A7/PAL7
D14
A5
−
A10
−
A11
A24/PAH8
C6
VDD
E1
D5/PDL5
A12
VDD
C7
A11/PAL11
E2
D7/PDL7
A13
LBE/SDCAS/PCD2
C8
VDD
E3
D8/PDL8
A14
UBE/SDRAS/PCD3
C9
A19/PAH3
E4
D11/PDL11
C10
A22/PAH6
E5
−
B1
−
B2
D12/PDL12
C11
VSS
E11
CS6/RAS6/PCS6
B3
A0/PAL0
C12
CS3/RAS3/PCS3
E12
CS4/RAS4/PCS4
B4
A4/PAL4
C13
CS2/IOWR/PCS2
E13
CS7/PCS7
B5
VSS
C14
E14
VSS
B6
A8/PAL8
D1
F1
D2/PDL2
B7
A13/PAL13
D2
D10/PDL10
F2
D3/PDL3
B8
VSS
D3
D14/PDL14
F3
D4/PDL4
B9
A18/PAH2
D4
A3/PAL3
F4
VDD
4
−
VSS
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(2/2)
Pin No.
F11
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
−
RD/PCT4
L6
VDD
P5
F12
VDD
L7
INTP122/P36
P6
INTP121/P35
F13
LCAS/LWR/LDQM/PCT0
L8
SI2/INTP131/P31
P7
SCK2/INTP132/P32
F14
UCAS/UWR/UDQM/PCT1
L9
RESET
P8
MODE1
G1
MODE2
L10
TXD1/SO1/P43
P9
CVDD
G2
DMARQ3/INTP103/P07
L11
ANI7/P77
P10
X1
G3
D0/PDL0
L12
ANI4/P74
P11
−
G4
D6/PDL6
L13
ANI3/P73
P12
RXD1/SI1/P44
ANI2/P72
P13
RXD0/SI0/P41
P14
−
G11
WAIT/PCM0
L14
G12
WE/PCT5
M1
G13
BCYST/PCT7
M2
INTP011/P12
G14
OE/PCT6
M3
TO01/P13
H1
DMARQ2/INTP102/P06
M4
TC2/INTP112/P26
−
H2
DMARQ1/INTP101/P05
M5
TI020/INTP020/P21
H3
DMARQ0/INTP100/P04
M6
VSS
H4
D1/PDL1
M7
RXD2/INTP120/P34
H11
REFRQ/PCM4
M8
MODE0
H12
HLDRQ/PCM3
M9
CKSEL
H13
HLDAK/PCM2
M10
SCK1/P45
H14
CLKOUT/BUSCLK/PCM1
M11
TXD0/SO0/P40
J1
TO00/P03
M12
ANI6/P76
J2
TI000/INTP000/P01
M13
ANI5/P75
J3
VDD
M14
J4
INTP001/P02
N1
J11
TO03/P52
N2
PWM1/P10
J12
TI030/INTP030/P50
N3
TC3/INTP113/P27
J13
SELFREF/PCM5
N4
TC0/INTP110/P24
J14
INTP031/P51
N5
NMI/P20
K1
PWM0/P00
N6
ADTRG/INTP123/P37
K2
VSS
N7
TXD2/INTP133/P33
K3
DMAAK1/PBD1
N8
SO2/INTP130/P30
K4
DMAAK3/PBD3
N9
X2
K11
ANI1/P71
N10
CVSS
K12
ANI0/P70
N11
SCK0/P42
K13
VSS
N12
AVDD/AVREF
K14
VDD
N13
AVSS
−
−
L1
−
L2
DMAAK2/PBD2
−
L3
TI010/INTP010/P11
P2
VSS
L4
DMAAK0/PBD0
P3
TC1/INTP111/P25
L5
TO02/P23
P4
INTP021/P22
N14
P1
VDD
Remark Leave the A1, A5, A10, B1, B14, C1, C14, D14, E5, L1, M1, M14, N1, N14, P5, P11, and P14 pins open.
Data Shee U15578EJ1V0DS
5
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
PIN IDENTIFICATION
A0 to A25:
Address bus
P50 to P52:
Port 5
ADTRG:
A/D trigger input
P70 to P77:
Port 7
ANI0 to ANI7:
Analog input
PAH0 to PAH9:
Port AH
AVDD:
Analog power supply
PAL0 to PAL15:
Port AL
AVREF:
Analog reference voltage
PBD0 to PBD3:
Port BD
AVSS:
Analog ground
PCD0 to PCD3:
Port CD
BCYST:
Bus cycle start timing
PCM0 to PCM5:
Port CM
BUSCLK:
Bus clock output
PCS0 to PCS7:
Port CS
CKSEL:
Clock generator operating mode select
PCT0, PCT1,
CLKOUT:
Clock output
PCT4 to PCT7:
Port CT
CS0 to CS7:
Chip select
PDL0 to PDL15:
Port DL
CVDD:
Clock generator power supply
PWM0, PWM1:
Pulse width modulation
CVSS:
Clock generator ground
RAS1, RAS3,
D0 to D15:
Data bus
RAS4, RAS6:
Row address strobe
DMAAK0 to DMAAK3:
DMA acknowledge
RD:
Read
DMARQ0 to DMARQ3:
DMA request
REFRQ:
Refresh request
HLDAK:
Hold acknowledge
RESET:
Reset
HLDRQ:
Hold request
RXD0 to RXD2:
Receive data
INTP000, INTP001,
SCK0 to SCK2:
Serial clock
INTP010, INTP011,
SDCAS:
SDRAM column address strobe
INTP020, INTP021,
SDCKE:
SDRAM clock enable
INTP030, INTP031,
SDCLK:
SDRAM clock output
INTP100 to INTP103,
SDRAS:
SDRAM row address strobe
INTP110 to INTP113,
SELFREF:
Self-refresh request
INTP120 to INTP123,
SI0 to SI2:
Serial input
INTP130 to INTP133:
Interrupt request from peripherals
SO0 to SO2:
Serial output
IORD:
I/O read strobe
TC0 to TC3:
Terminal count signal
IOWR:
I/O write strobe
TI000, TI010,
LBE:
Lower byte enable
TI020, TI030:
Timer input
LCAS:
Lower column address strobe
TO00 to TO03:
Timer output
LDQM:
Lower DQ mask enable
TXD0 to TXD2:
Transmit data
LWR:
Lower write strobe
UBE:
Upper byte enable
MODE0 to MODE2:
Mode
UCAS:
Upper column address strobe
NMI:
Non-maskable interrupt request
UDQM:
Upper DQ mask enable
OE:
Output enable
UWR:
Upper write strobe
P00 to P07:
Port 0
VDD:
Power supply
P10 to P13:
Port 1
VSS:
Ground
P20 to P27:
Port 2
WAIT:
Wait
P30 to P37:
Port 3
WE:
Write enable
P40 to P45:
Port 4
X1, X2:
Crystal
6
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
INTERNAL BLOCK DIAGRAM
NMI
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133
INTP000, INTP001,
INTP010, INTP011,
INTP020, INTP021,
INTP030, INTP031
CPU
INTC
BCU
MEMC
Instruction
queue
DRAMC
ROM
PC
Note 1
32-bit barrel
shifter
RPU
Multiplier
(32 × 32 → 64)
TO00 to TO03
TI000, TI010,
TI020, TI030
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
SO1/TXD1
SI1/RXD1
SCK1
UART1/CSI1
RAM
System
registers
ALU
Note 2
TXD2
DMAC
UART2
SO2
SI2
SCK2
CSI2
PWM0
PWM0
Ports
PWM1
PWM1
PDL0 to PDL15
PAL0 to PAL15
PAH0 to PAH9
PCS0 to PCS7
PCT0, PCT1, PCT4 to PCT7
PCM0 to PCM5
PCD0 to PCD3
PBD0 to PBD3
P70 to P77
P50 to P52
P40 to P45
P30 to P37
P21 to P27
P20
P10 to P13
P00 to P07
RXD2
ANI0 to ANI7
AVREF/AVDD
AVSS
ADTRG
Notes 1.
ADC
ROMC
Generalpurpose
registers
(32 bits × 32)
CG
System
controller
HLDRQ
HLDAK
CS0, CS7
CS1/RAS1, CS3/RAS3
CS4/RAS4, CS6/RAS6
CS2/IORD
CS5/IOWR
SELFREF
REFRQ
BCYST
LBE/SDCAS
UBE/SDRAS
SDCLK
SDCKE
WE
RD
OE
UWR/UCAS/UDQM
LWR/LCAS/LDQM
WAIT
A0 to A25
D0 to D15
BUSCLK
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
CKSEL
CLKOUT
X1
X2
CVDD
CVSS
MODE0 to MODE2
RESET
VDD
VSS
µPD703103A: ROMless
µPD703105A, 703106A, 703106A(A): 128 KB
µPD703107A, 703107A(A): 256 KB
2.
µPD703103A, 703105A: 4 KB
µPD703106A, 703106A(A), 703107A, 703107A(A): 10 KB
Data Shee U15578EJ1V0DS
7
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
CONTENTS
1. CHANGES FROM µPD703106, 703107 DATA SHEET (U14792E) ......................................................9
2. DIFFERENCES BETWEEN PRODUCTS...............................................................................................9
3. PIN FUNCTIONS ..................................................................................................................................10
3.1
Port Pins .......................................................................................................................................................10
3.2
Non-Port Pins ...............................................................................................................................................12
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins ...........................................................15
4. ELECTRICAL SPECIFICATIONS ........................................................................................................18
5. PACKAGE DRAWING..........................................................................................................................72
6. RECOMMENDED SOLDERING CONDITIONS ...................................................................................74
APPENDIX NOTES ON TARGET SYSTEM DESIGN ...............................................................................75
8
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
1. CHANGES FROM µPD703106, 703107 DATA SHEET (U14792E)
Page
Description
Throughout
Addition of 161-pin plastic FBGA (13 × 13) package
p.4
Addition of 161-pin plastic FBGA (13 × 13) pin configuration diagram
p.18
Addition of storage temperature (Tstg) specification for FBGA package
p.20
Deletion of TDK recommended oscillator constant
p.24
Addition of PLL mode specifications (other than x10) to X1 input cycle (<1> tCYX)
pp.28, 30, 31, 34, 36
Addition of description on UBE, LBE signals in timing chart
p.29
Relaxing of data input setup time (to address) (<39> tSAID) and data input setup time (to RD) (<40>
tSRDID) specifications
p.31
Addition of data output setup time (to UWR, LWR, IOWR ↑) (<56> tSODWR) specifications
pp.37 to 41
Addition of (5) SRAM, external ROM, and external I/O access timing (vis-à-vis BUSCLK signal)
(when BCP bit of BCP register = 1)
p.68
Addition of SIn setup time (to SCKn ↓) (<167> tSSISK), SIn hold time (from SCKn ↓) (<168> tHSKSI),
SOn output delay time (from SCKn ↑) (<169> tDSKSO), and SOn output hold time (from SCKn ↓)
(<170> tHSKSO) specifications
pp.69, 70
Addition of (d) Timing when CKPn, DAPn bits of CSICn register = 01, (e) Timing when CKPn,
DAPn bits of CSICn register = 10, and (f) Timing when CKPn, DAPn bits of CSICn register = 11
p.71
Change of specification unit for overall error, zero-scale error, and full-scale error
Addition of integral linearity error and differential linearity error specifications
p.73
Addition of 161-pin plastic FBGA (13 × 13) package drawing
p.74
Addition of 6. RECOMMENDED SOLDERING CONDITIONS
p.75
Addition of APPENDIX NOTES ON TARGET SYSTEM DESIGN
2. DIFFERENCES BETWEEN PRODUCTS
ROM
Product
Type
µPD703103A
Mask ROM
µPD703105A
RAM
Size
Size
None
4 KB
Flash Memory
Programming Pin
None
Package
144-pin LQFP
Quality
Grade
Standard
128 KB
µPD703106A
10 KB
µPD703107A
256 KB
144-pin LQFP
161-pin FBGA
µPD703106A(A)
128 KB
144-pin LQFP
Special
µPD703107A(A)
256 KB
144-pin LQFP
Standard
µPD70F3107A
Flash memory
256 KB
Provided (VPP)
161-pin FBGA
µPD70F3107A(A)
144-pin LQFP
Special
Cautions 1. There are differences in noise immunity and noise radiation between the flash memory
version and mask ROM version.
When pre-producing an application set with the flash
memory version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluation for commercial samples (not engineering samples) of the mask ROM
version.
2. When switching from the flash memory version to the mask ROM version, write the same
code to the free area of the internal ROM.
Data Shee U15578EJ1V0DS
9
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
3. PIN FUNCTIONS
3.1
Port Pins
(1/2)
Pin Name
P00
I/O
I/O
P01
P02
Function
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
PWM0
TI000/INTP000
INTP001
P03
TO00
P04
DMARQ0/INTP100
P05
DMARQ1/INTP101
P06
DMARQ2/INTP102
P07
DMARQ3/INTP103
P10
I/O
P11
P12
Port 1
4-bit I/O port
Input/output can be specified in 1-bit units.
PWM1
INTP010/TI010
INTP011
TO01
P13
P20
Input
P21
I/O
P22
P23
P24
Port 2
P20 is an input-only port.
If a valid edge is input, it operates as an NMI input. Also, the
status of the NMI input is shown by bit 0 of the P2 register.
P21 to P27 are 7-bit I/O port.
Input/output can be specified in 1-bit units.
NMI
INTP020/TI020
INTP021
TO02
TC0/INTP110
P25
TC1/INTP111
P26
TC2/INTP112
TC3/INTP113
P27
P30
I/O
P31
P32
Port 3
8-bit I/O port
Input/output can be specified in 1-bit units.
SO2/INTP130
SI2/INTP131
SCK2/INTP132
P33
TXD2/INTP133
P34
RXD2/INTP120
P35
INTP121
P36
INTP122
P37
ADTRG/INTP123
P40
I/O
P41
P42
Port 4
6-bit I/O port
Input/output can be specified in 1-bit units.
TXD0/SO0
RXD0/SI0
SCK0
P43
TXD1/SO1
P44
RXD1/SI1
P45
SCK1
P50
P51
P52
10
I/O
Port 5
3-bit I/O port
Input/output can be specified in 1-bit units.
Data Sheet U15578EJ1V0DS
INTP030/TI030
INTP031
TO03
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(2/2)
Pin Name
I/O
Function
Alternate Function
P70 to P77
Input
Port 7
8-bit input-only port
ANI0 to ANI7
PBD0 to PBD3
I/O
Port BD
4-bit I/O port
Input/output can be specified in 1-bit units.
DMAAK0 to DMAAK3
PCM0
I/O
Port CM
6-bit I/O port
Input/output can be specified in 1-bit units.
WAIT
PCM1
PCM2
CLKOUT/BUSCLK
HLDAK
PCM3
HLDRQ
PCM4
REFRQ
PCM5
SELFREF
PCT0
I/O
PCT1
PCT4
Port CT
6-bit I/O port
Input/output can be specified in 1-bit units.
LCAS/LWR/LDQM
UCAS/UWR/UDQM
RD
PCT5
WE
PCT6
OE
PCT7
BCYST
PCS0
I/O
PCS1
PCS2
Port CS
8-bit I/O port
Input/output can be specified in 1-bit units.
CS0
CS1/RAS1
CS2/IOWR
PCS3
CS3/RAS3
PCS4
CS4/RAS4
PCS5
CS5/IORD
PCS6
CS6/RAS6
PCS7
CS7
PCD0
I/O
PCD1
PCD2
Port CD
4-bit I/O port
Input/output can be specified in 1-bit units.
SDCKE
SDCLK
LBE/SDCAS
UBE/SDRAS
PCD3
PAH0 to PAH9
I/O
Port AH
8-/10-bit I/O port
Input/output can be specified in 1-bit units.
A16 to A25
PAL0 to PAL15
I/O
Port AL
8-/16-bit I/O port
Input/output can be specified in 1-bit units.
A0 to A15
PDL0 to PDL15
I/O
Port DL
8-/16-bit I/O port
Input/output can be specified in 1-bit units.
D0 to D15
Data Shee U15578EJ1V0DS
11
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
3.2
Non-Port Pins
(1/3)
Pin Name
TO00
I/O
Output
Function
Pulse signal output of timer C0 to C3
Alternate Function
P03
TO01
P13
TO02
P23
TO03
P52
TI000
Input
External count clock input of timer C0 to C3
P01/INTP000
TI010
P11/INTP010
TI020
P21/INTP020
TI030
INTP000
P50/INTP030
Input
INTP001
INTP010
Input
INTP011
INTP020
Input
INTP021
INTP030
External maskable interrupt request input, or timer C1 external
capture trigger input
External maskable interrupt request input, or timer C2 external
capture trigger input
P01/TI000
P02
P11/TI010
P12
P21/TI020
P22
Input
External maskable interrupt request input, or timer C3 external
capture trigger input
P51
Input
External maskable interrupt request input
P04/DMARQ0
INTP031
INTP100
External maskable interrupt request input, or timer C0 external
capture trigger input
P50/TI030
INTP101
P05/DMARQ1
INTP102
P06/DMARQ2
INTP103
P07/DMARQ3
INTP110
P24/TC0
INTP111
P25/TC1
INTP112
P26/TC2
INTP113
P27/TC3
INTP120
P34/RXD2
INTP121
P35
INTP122
P36
INTP123
P37/ADTRG
INTP130
P30/SO2
INTP131
P31/SI2
INTP132
P32/SCK2
INTP133
P33/TXD2
SO0
Output
CSI0 to SCI2 serial transmission data output (3-wire)
P40/TXD0
SO1
P43/TXD1
SO2
P30/INTP130
SI0
Input
CSI0 to CSI2 serial reception data input (3-wire)
P41/RXD0
SI1
P44/RXD1
SI2
P31/INTP131
12
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(2/3)
Pin Name
SCK0
I/O
I/O
Function
CSI0 to CSI2 serial clock I/O (3-wire)
Alternate Function
P42
SCK1
P45
SCK2
P32/INTP132
TXD0
Output
UART0 to UART2 serial transmission data output
P40/SO0
TXD1
P43/SO1
TXD2
P33/INTP133
RXD0
Input
UART0 to UART2 serial reception data input
P41/SI0
RXD1
P44/SI1
RXD2
P34/INTP120
PWM0
Output
PWM pulse signal output
PWM1
P00
P10
ANI0 to ANI7
Input
Analog inputs to the A/D converter
P70 to P77
ADTRG
Input
A/D converter external trigger input
P37/INTP123
DMARQ0
Input
DMA request signal input
P04/INTP100
DMARQ1
P05/INTP101
DMARQ2
P06/INTP102
DMARQ3
P07/INTP103
DMAAK0
Output
DMA acknowledge signal output
PBD0
DMAAK1
PBD1
DMAAK2
PBD2
DMAAK3
PBD3
TC0
Output
DMA transfer termination (terminal count) signal output
P24/INTP110
TC1
P25/INTP111
TC2
P26/INTP112
TC3
P27/INTP113
NMI
Input
Non-maskable interrupt request signal input
MODE0
Input
V850E/MA1 operating mode specification
P20
−
MODE1
−
MODE2
−
WAIT
Input
Control signal input that inserts a wait in the bus cycle
PCM0
HLDAK
Output
Bus hold acknowledge output
PCM2
HLDRQ
Input
Bus hold request input
PCM3
REFRQ
Output
Refresh request signal output for DRAM
PCM4
SELFREF
Input
Self refresh request input for DRAM
PCM5
LCAS
Output
Column address strobe signal output for DRAM lower data
PCT0/LWR/LDQM
UCAS
Output
Column address strobe signal output for DRAM higher data
PCT1/UWR/UDQM
LWR
Output
External data lower byte write strobe signal output
PCT0/LCAS/LDQM
UWR
Output
External data higher byte write strobe signal output
PCT1/UCAS/UDQM
Data Shee U15578EJ1V0DS
13
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(3/3)
Pin Name
I/O
Function
Alternate Function
LDQM
Output
Output disable/write mask signal output for SDRAM lower data
PCT0/LCAS/LWR
UDQM
Output
Output disable/write mask signal output for SDRAM higher data
PCT1/UCAS/UWR
RD
Output
External data bus read strobe signal output
PCT4
WE
Output
Write enable signal output for DRAM
PCT5
OE
Output
Output enable signal output for DRAM
PCT6
BCYST
Output
Strobe signal output that shows the start of the bus cycle
PCT7
CS0
Output
Chip select signal output
PCS0
CS1
PCS1/RAS1
CS2
PCS2/IOWR
CS3
PCS3/RAS3
CS4
PCS4/RAS4
CS5
PCS5/IORD
CS6
PCS6/RAS6
CS7
PCS7
RAS1
Output
Row address strobe signal output for DRAM
RAS3
PCS1/CS1
PCS3/CS3
RAS4
PCS4/CS4
RAS6
PCS6/CS6
IOWR
Output
DMA write strobe signal output
PCS2/CS2
IORD
Output
DMA read strobe signal output
PCS5/CS5
SDCKE
Output
SDRAM clock enable signal output
PCD0
SDCLK
Output
SDRAM clock signal output
PCD1
SDCAS
Output
Column address strobe signal output for SDRAM
PCD2/LBE
SDRAS
Output
Row address strobe signal output for SDRAM
PCD3/UBE
LBE
Output
External data bus lower byte enable signal output
PCD2/SDCAS
UBE
Output
External data bus higher byte enable signal output
PCD3/SDRAS
D0 to D15
I/O
16-bit data bus for external memory
PDL0 to PDL15
A0 to A15
Output
26-bit address bus for external memory
PAL0 to PAL15
RESET
Input
System reset input
−
X1
Input
Connects the crystal resonator for system clock oscillation. In the
case of an external source supplying the clock, it is input to X1 pin.
−
A16 to A25
X2
PAH0 to PAH9
−
−
CLKOUT
Output
System clock output
PCM1/BUSCLK
BUSCLK
Output
Bus clock output
PCM1/CLKOUT
CKSEL
Input
Input which specifies the clock generator's operating mode
AVREF
Input
Reference voltage applied to A/D converter
AVDD
AVREF
−
AVDD
−
Positive power supply for A/D converter
AVSS
−
Ground potential for A/D converter
−
CVDD
−
Positive power supply for the dedicated clock generator
−
CVSS
−
Ground potential for the dedicated clock generator
−
VDD
−
Positive power supply
−
VSS
−
Ground potential
−
14
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
The input/output circuit configuration of each type is schematically shown in Figure 3-1.
It is recommended that 1 to 10 kΩ resistors be used when connecting to VDD or VSS via a resistor.
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name
P00/PWM0
P01/INTP000/TI000
I/O Circuit Type
5
5-AC
P04/DMARQ0/INTP100 to P07/DMARQ3/INTP103
P10/PWM1
P11/INTP010/TI010
Input: Independently connect to VDD or VSS via
a resistor.
Output: Leave open.
P02/INTP001
P03/TO00
Recommended Connection
5
5-AC
5
5-AC
P12/INTP011
P13/TO01
5
P20/NMI
2
P21/INTP020/TI020
5-AC
P22/INTP021
P23/TO02
P24/TC0/INTP110 to P27/TC3/INTP113
5
Connect directly to VSS.
Input: Independently connect to VDD or VSS via
a resistor.
Output: Leave open.
5-AC
P30/SO2/INTP130
P31/SI2/INTP131
P32/SCK2/INTP132
P33/TXD2/INTP133
P34/RXD2/INTP120
P35/INTP121
P36/INTP122
P37/ADTRG/INTP123
P40/TXD0/SO0
5
P41/RXD0/SI0
5-AC
P42/SCK0
P43/TXD1/SO1
5
P44/RXD1/SI1
5-AC
P45/SCK1
P50/INTP030/TI030
P51/INTP031
P52/TO03
5
P70/ANI0 to P77/ANI7
9
Connect directly to VSS.
PBD0/DMAAK0 to PBD3/DMAAK3
5
Input: Independently connect to VDD or VSS via
a resistor.
Output: Leave open.
Data Shee U15578EJ1V0DS
15
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
Pin Name
I/O Circuit Type
Recommended Connection
PCM0/WAIT
5
Input: Independently connect to VDD via a resistor.
PCM1/CLKOUT/BUSCLK
5
Input: Independently connect to VDD or VSS via a
resistor.
PCM2/HLDAK
Output: Leave open.
PCM3/HLDRQ
5
Input: Independently connect to VDD via a resistor.
PCM4/REFRQ
5
Input: Independently connect to VDD or VSS via a
resistor.
Output: Leave open.
PCM5/SELFREF
5
Input: Independently connect to VSS via a resistor.
PCT0/LCAS/LWR/LDQM
5
PCT1/UCAS/UWR/UDQM
Input: Independently connect to VDD or VSS via a
resistor.
PCT4/RD
Output: Leave open.
PCT5/WE
PCT6/OE
PCT7/BCYST
PCS0/CS0
PCS1/CS1/RAS1
PCS2/CS2/IOWR
PCS3/CS3/RAS3
PCS4/CS4/RAS4
PCS5/CS5/IORD
PCS6/CS6/RAS6
PCS7/CS7
PCD0/SDCKE
PCD1/SDCLK
PCD2/LBE/SDCAS
PCD3/UBE/SDRAS
PAH0/A16 to PAH9/A25
PAL0/A0 to PAL15/A15
PDL0/D0 to PDL15/D15
MODE0 to MODE2
−
2
RESET
CKSEL
1
AVSS
−
Connect to VSS.
AVDD/AVREF
−
Connect to VDD.
16
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Figure 3-1. Pin I/O Circuits
Type 1
Type 5-AC
VDD
VDD
Data
P-ch
IN/OUT
P-ch
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 9
P-ch
IN
IN
+
Comparator
N-ch
VREF (threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Input enable
Type 5
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
Data Shee U15578EJ1V0DS
17
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Symbol
Conditions
Ratings
Unit
VDD
VDD pin
−0.5 to +4.6
V
CVDD
CVDD pin
−0.5 to +4.6
V
CVSS
CVSS pin
−0.5 to +0.5
V
AVDD
AVDD pin
−0.5 to +4.6
V
AVSS
AVSS pin
−0.5 to +0.5
V
Input voltage
VI
Except X1 pin
−0.5 to +6.0
V
Clock input voltage
VK
X1, VDD = 3.3 V ±0.3 V
−0.5 to VDD + 1.0
V
Output current, low
IOL
Per pin
4.0
mA
Total of all pins
100
mA
Per pin
−4.0
mA
Total of all pins
−100
mA
Power supply voltage
Output current, high
IOH
Output voltage
VO
VDD = 3.3 V ±0.3 V
Analog input voltage
VWASN
ANI0 to ANI7, VDD = 3.3 V ±0.3 V
Operating ambient temperature
TA
Storage temperature
−0.5 to VDD + 0.5
V
−0.3 to AVDD + 0.3
V
−40 to +85
°C
LQFP package
−60 to +150
°C
FBGA package
−40 to +125
°C
Tstg
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC
and GND.
However, direct connections among open-drain and open-collector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output conflict with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded. The ratings
and conditions shown below for DC characteristics and AC characteristics are within the
range for normal operation and quality assurance.
Capacitance (TA = 25°°C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
CI
fC = 1 MHz
15
pF
I/O capacitance
CIO
Unmeasured pins returned to 0 V.
15
pF
Output capacitance
CO
15
pF
18
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Operating Conditions
Operation Mode
Internal Operation Clock
Frequency (fXX)
Operating Ambient
Temperature (TA)
Power Supply Voltage (VDD)
Direct mode
4 to 25 MHz
−40 to +85°C
VDD = 3.3 V ±0.3 V
PLL mode
4 to 50 MHz
−40 to +85°C
VDD = 3.3 V ±0.3 V
Recommended Oscillator
Caution
For the resonator selection and oscillator constant of the µPD703106A(A) and 703107A(A),
customers are requested to apply to the resonator manufacturer for evaluation.
(a) Ceramic resonator
(i) Murata Mfg. Co., Ltd. (TA = –40 to +85°°C)
X1
X2
Rd
C1
Type
Product
C2
Oscillation
Frequency
Recommended Circuit Constant
Oscillation Voltage
Range
Oscillation
Stabilization
Time (MAX.)
fX (MHz)
C1 (pF)
C2 (pF)
Rd (kΩ)
MIN. (V)
MAX. (V)
TOST (ms)
Surface
mount
CSTCC4.00MG0H6
4.0
On-chip
On-chip
0
3.0
3.6
0.09
CSTCC5.00MG0H6
5.0
On-chip
On-chip
0
3.0
3.6
0.09
Lead
CSA4.00MG
4.0
30
30
0
3.0
3.6
0.05
CST4.00MGW
4.0
On-chip
On-chip
0
3.0
3.6
0.05
CSTS0400MG06
4.0
On-chip
On-chip
0
3.0
3.6
0.11
CSA5.00MG
5.0
30
30
0
3.0
3.6
0.05
CST5.00MGW
5.0
On-chip
On-chip
0
3.0
3.6
0.05
CSTS0500MG06
5.0
On-chip
On-chip
0
3.0
3.6
0.11
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD703103A, 303105A, 703106A,
703107A and the resonator.
Data Sheet U15578EJ1V0DS
19
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(ii) Kyocera Corporation (TA = –20 to +80°°C)
X1
X2
Rd
C1
Type
Surface
mount
Lead
Product
C2
Oscillation
Frequency
Recommended Circuit Constant
Oscillation Voltage
Range
Oscillation
Stabilization
Time (MAX.)
fX (MHz)
C1 (pF)
C2 (pF)
Rd (kΩ)
MIN. (V)
MAX. (V)
TOST (ms)
PBRC4.00AR-A
4.0
33
33
0
3.0
3.6
0.11
PBRC4.00BR-A
4.0
On-chip
On-chip
0
3.0
3.6
0.11
PBRC5.00AR-A
5.0
33
33
0
3.0
3.6
0.08
PBRC5.00BR-A
5.0
On-chip
On-chip
0
3.0
3.6
0.08
KBR-4.0MSB
4.0
33
33
0
3.0
3.6
0.11
KBR-4.0MKC
4.0
On-chip
On-chip
0
3.0
3.6
0.11
KBR-5.0MSB
5.0
33
33
0
3.0
3.6
0.08
KBR-5.0MKC
5.0
On-chip
On-chip
0
3.0
3.6
0.08
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. Thoroughly evaluate the matching between the µPD703103A, 703105A, 703106A,
703107A and the resonator.
(b) External clock input (TA = –40 to +85°°C)
X1
External clock
20
X2
Open
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
DC Characteristics (TA = –40 to +85°°C, VDD = 3.3 V ±0.3 V, VSS = 0 V)
Parameter
Symbol
Input voltage, high
VIH
Input voltage, low
VIL
Conditions
MIN.
Except for Note 1
2.0
Clock input voltage, low
Schmitt-triggered input
threshold voltage
Schmitt-triggered input
hysteresis width
Output voltage, high
VXH
VXL
VT+
MAX.
Unit
5.5
V
0.75VDD
5.5
V
Except for Note 1
–0.5
0.8
V
Note 1
–0.5
0.2VDD
V
Direct mode
0.8VDD
VDD + 0.3
V
PLL mode
0.8VDD
VDD + 0.3
V
Direct mode
–0.5
0.15VDD
V
PLL mode
–0.5
0.15VDD
V
Note 1
Clock input voltage, high
TYP.
X1 pin
X1 pin
Note 1, rising edge
2.0
V
VT−
Note 1, falling edge
1.0
V
VT+ –
Note 1
0.3
V
IOH = –2.5 mA
0.8VDD
V
IOH = –100 µA
VDD – 0.4
V
VT−
VOH
Output voltage, low
VOL
IOL = 2.5 mA
0.45
V
Input leakage current, high
ILIH
VI = VDD, except for Note 2
10
µA
Input leakage current, low
ILIL
VI = 0 V, except for Note 2
−10
µA
Output leakage current, high
ILOH
VO = VDD
10
µA
Output leakage current, low
ILOL
VO = 0 V
−10
µA
Analog pin input leakage
current
ILWASN
Note 2
±10
µA
Power supply
current
During
normal
operation
IDD1
In HALT
mode
IDD2
In IDLE
mode
IDD3
In STOP
mode
IDD4
Direct mode
2.6 × fXX + 30
3.9 × fXX + 45
mA
PLL mode
2.6 × fXX + 30
3.9 × fXX + 45
mA
Direct mode
1.6 × fXX + 20
2.4 × fXX + 30
mA
PLL mode
1.6 × fXX + 20
2.4 × fXX + 30
mA
Direct mode
10
30
mA
PLL mode
10
30
mA
–40°C ≤ TA ≤ +40°C
10
60
µA
250
µA
40°C < TA ≤ 85°C
Notes 1. P01/TI000/INTP000, P02/INTP001, P04/DMARQ0/INTP100 to P07/DMARQ3/INTP103,
P11/TI010/INTP010, P12/INTP011, P21/TI020/INTP020, P22/INTP021, P24/TC0/INTP110 to
P27/TC3/INTP113, P30/SO2/INTP130, P31/SI2/INTP131, P32/SCK2/INTP132, P33/TXD2/INTP133,
P34/RXD2/INTP120, P35/INTP121, P36/INTP122, P37/ADTRG/INTP123, P41/RXD0/SI0, P42/SCK0,
P44/RXD1/SI1, P45/SCK1, P50/TI030/INTP030, P51/INTP031
2. P70/ANI0 to P77/ANI7
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = 3.3 V. The current does not include
the current flowing through pull-up resistors.
2. fXX: CPU operation frequency
Data Sheet U15578EJ1V0DS
21
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Data Retention Characteristics (TA = –40 to +85°°C)
Parameter
Symbol
Conditions
MIN.
Data retention voltage
VDDDR
STOP mode and VDD = VDDDR
1.5
Data retention current
IDDDR
VDD =
VDDDR
–40°C ≤ TA ≤ +40°C
TYP.
10
40°C < TA ≤ 85°C
MAX.
Unit
3.6
V
60
µA
250
µA
Power supply voltage rise time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold time
(from STOP mode setting)
tHVD
0
ms
STOP release signal input time
tDREL
0
ns
Data retention high-level input
voltage
VIHDR
Note
0.8VDDDR
VDDDR
V
Data retention low-level input
voltage
VILDR
Note
−0.5
0.2VDDDR
V
Note P01/TI000/INTP000, P02/INTP001, P04/DMARQ0/INTP100 to P07/DMARQ3/INTP103, P11/TI010/INTP010,
P12/INTP011, P21/TI020/INTP020, P22/INTP021, P24/TC0/INTP110 to P27/TC3/INTP113,
P30/SO2/INTP130, P31/SI2/INTP131, P32/SCK2/INTP132, P33/TXD2/INTP133, P34/RXD2/INTP120,
P35/INTP121, P36/INTP122, P37/ADTRG/INTP123, P41/RXD0/SI0, P42/SCK0, P44/RXD1/SI1, P45/SCK1,
P50/TI030/INTP030, P51/INTP031
Remark
TYP. values are reference values for when TA = 25°C.
STOP mode setup
VDDDR
VDD
tFVD
tRVD
tHVD
RESET (input)
NMI (input)
(Released at falling edge)
tDREL
VIHDR
VIHDR
NMI (input)
(Released at rising edge)
VILDR
22
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
AC Characteristics
(TA = –40 to +85°°C, VDD = 3.3 V ±0.3 V, VSS = 0 V, output pin load capacitance: CL = 50 pF)
AC test input points
(a)
P01/TI000/INTP000, P02/INTP001, P04/DMARQ0/INTP100 to P07/DMARQ3/INTP103, P11/TI010/INTP010,
P12/INTP011, P21/TI020/INTP020, P22/INTP021, P24/TC0/INTP110 to P27/TC3/INTP113, P30/SO2/INTP130,
P31/SI2/INTP131, P32/SCK2/INTP132, P33/TXD2/INTP133, P34/RXD2/INTP120, P35/INTP121, P36/INTP122,
P37/ADTRG/INTP123, P41/RXD0/SI0, P42/SCK0, P44/RXD1/SI1, P45/SCK1, P50/TI030/INTP030,
P51/INTP031
VDD
0.75VDD
Input signal
0.2VDD
0V
(b)
Test
points
0.75VDD
0.2VDD
Other than (a) above
VDD
2.0 V
Input signal
0.8 V
0V
Test
points
2.0 V
0.8 V
AC test output test points
0.7VDD
Output signal
0.2VDD
Test
points
0.7VDD
0.2VDD
Load condition
DUT
(Device under test)
C L = 50 pF
Caution
In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device’s load capacitance to 50 pF or lower.
Data Sheet U15578EJ1V0DS
23
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(1) Clock timing (1/2)
Parameter
X1 input cycle
Symbol
<1>
Conditions
tCYX
Direct mode
PLL mode
X1 input high-level width
X1 input low-level width
X1 input rise time
X1 input fall time
<2>
<3>
<4>
<5>
tWXH
tWXL
tXR
tXF
MIN.
MAX.
Unit
20
125
ns
×10
200
250
ns
Other than ×10
150
250
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
4
ns
PLL mode
10
ns
Direct mode
4
ns
PLL mode
10
ns
250
ns
CLKOUT output cycle
<6>
tCYK1
20
CLKOUT high-level width
<7>
tWKH1
0.5T – 5
ns
CLKOUT low-level width
<8>
tWKL1
0.5T – 6
ns
CLKOUT rise time
<9>
tKR1
5
ns
CLKOUT fall time
<10>
tKF1
4
ns
Delay time from X1↓ to CLKOUT
<11>
tDKX
40
ns
Delay time from X1↓ to SDCLK
<12>
tDSX
SDCLK output cycle
<13>
tCYK2
20
40
ns
250
ns
SDCLK high-level width
<14>
tWKH2
0.5T – 5
ns
SDCLK low-level width
<15>
tWKL2
0.5T – 6
ns
SDCLK rise time
<16>
tKR2
5
ns
SDCLK fall time
<17>
tKF2
4
ns
BUSCLK rise time
<18>
tKR3
5
ns
BUSCLK fall time
<19>
tKF3
4
ns
Remarks 1. T = tCYK
2. The phase difference between CLKOUT and SDCLK, and between CLKOUT and BUSCLK cannot
be defined.
24
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(1) Clock timing (2/2)
<1>
<3>
<5>
<4>
<2>
X1
(PLL mode)
<1>
<2>
<3>
<4>
X1
(direct mode)
<5>
<11>
<11>
CLKOUT (output)
<9>
<10>
<7>
<8>
<6>
<12>
SDCLK (output)
<16>
<17>
<14>
<15>
<13>
BUSCLK (output)
<18>
<19>
Remark The cycle of BUSCLK varies depending on the bus cycle.
(2) Output waveform (other than X1 and CLKOUT)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
<20>
tOR
5
ns
Output fall time
<21>
tOF
4
ns
<20>
<21>
Signals other than
X1 and CLKOUT
Data Sheet U15578EJ1V0DS
25
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(3) Reset timing
Parameter
Symbol
Conditions
RESET pin high-level width
<22>
tWRSH
RESET pin low-level width
<23>
tWRSL
MAX.
Unit
500
ns
At power-on and at STOP mode
release
500 + TOS
ns
Except at power-on and at STOP
mode release
500
ns
Remark
TOS: Oscillation stabilization time
Caution
Thoroughly evaluate the oscillation stabilization time.
<22>
RESET (input)
26
MIN.
Data Sheet U15578EJ1V0DS
<23>
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(4) SRAM, external ROM, and external I/O access timing (When BCP bit of BCP register = 0)
(a) Access timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Address, CSn output delay time (from CLKOUT↑)
<24>
Conditions
tDKA
Address, CSn output delay time (from SDCLK↑)
Address, CSn output hold time (from CLKOUT↑)
<25>
tHKA
Address, CSn output hold time (from SDCLK↑)
RD, IORD↓ delay time (from CLKOUT↓)
<26>
tDKRDL
RD, IORD↓ delay time (from SDCLK↓)
RD, IORD↑ delay time (from CLKOUT↑)
<27>
tHKRDH
RD, IORD↑ delay time (from SDCLK↑)
UWR, LWR, IOWR↓ delay time (from CLKOUT↓)
<28>
tDKWRL
UWR, LWR, IOWR↓ delay time (from SDCLK↓)
UWR, LWR, IOWR↑ delay time (from CLKOUT↓)
<29>
tHKWRH
UWR, LWR, IOWR↑ delay time (from SDCLK↓)
BCYST↓ delay time (from CLKOUT↑)
<30>
tDKBSL
BCYST↓ delay time (from SDCLK↑)
BCYST↑ delay time (from CLKOUT↑)
<31>
tHKBSH
BCYST↑ delay time (from SDCLK↑)
WAIT setup time (to CLKOUT↑)
<32>
tSWK
WAIT setup time (to SDCLK↑)
WAIT hold time (from CLKOUT↑)
<33>
tHKW
WAIT hold time (from SDCLK↑)
Data input setup time (to CLKOUT↑)
<34>
tSKID
Data input setup time (to SDCLK↑)
Data input hold time (from CLKOUT↑)
<35>
tHKID
Data input hold time (from SDCLK↑)
Data output delay time (from CLKOUT↓)
<36>
tDKOD1
Data output delay time (from SDCLK↓)
Data output delay time (from CLKOUT↑)
<37>
tDKOD2
Data output delay time (from SDCLK↑)
Data float delay time (from CLKOUT↑)
<38>
tHKOD
Data float delay time (from SDCLK↑)
MIN.
MAX.
Unit
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
8
ns
10
ns
2
ns
2
ns
8
ns
10
ns
2
ns
2
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
2
13
ns
0
13
ns
Remarks 1. Maintain at least one of the data input hold times, tHRDID or tHKID.
2. n = 0 to 7
Data Sheet U15578EJ1V0DS
27
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(a) Access timing (SRAM, external ROM, external I/O) (2/2)
T1
TW
T2
CLKOUT (output)
SDCLK (output)
<25>
<24>
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
<30>
<30>
<31>
BCYST (output)
<27>
<27>
<26>
<26>
RD, IORD (output)
[when read]
<29>
<28>
<29>
<28>
UWR, LWR, IOWR (output)
[when written]
<34>
<38>
<35>
D0 to D15 (I/O)
[when read]
<36>
<36>
<38>
<37>
D0 to D15 (I/O)
[when written]
<33>
<32>
<33>
<32>
WAIT (input)
Remarks 1. This is the timing when the number of waits based on the DWC0 and DWC1 registers is zero.
2. Broken lines indicate high impedance.
3. n = 0 to 7
28
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Read timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Data input setup time (to address)
<39>
tSAID
(2 + w + wD + wAS)T − 19
ns
Data input setup time (to RD)
<40>
tSRDID
(1.5 + w + wD)T − 19
ns
RD, IORD low-level width
<41>
tWRDL
(1.5 + w + wD)T − 10
ns
RD, IORD high-level width
<42>
tWRDH
(0.5 + wAS + i)T − 10
ns
Delay time from address, CSn,
to RD, IORD↓
<43>
tDARD
(0.5 + wAS)T − 10
ns
Delay time from RD, IORD↑ to address
<44>
tDRDA
iT
ns
Data input hold time (from RD, IORD↑)
<45>
tHRDID
0
ns
Delay time from RD, IORD↑ to data
output
<46>
tDRDOD
(0.5 + i)T − 10
ns
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
WAIT high-level width
<50>
tWWH
Data output hold time (from UWR,
LWR, IOWR↑)
<57>
tHWROD
Note
T − 10
ns
T − 10
ns
(0.5 + i)T − 8
ns
For the first WAIT sampling when the wait count based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. Maintain at least one of the data input hold times tHRDID or tHKID
5. n = 0 to 7
6. i: Idle state count
7. wAS: Address setup wait count based on the ASC register
Data Sheet U15578EJ1V0DS
29
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Read timing (SRAM, external ROM, external I/O) (2/2)
TASW
T1
TW
T2
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
UWR, LWR, IOWR
(output)
<42>
<41>
<44>
RD, IORD (output)
<43>
<57>
<40>
<39>
<46>
<45>
D0 to D15 (I/O)
<50>
<47>
WAIT (input)
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7
30
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) Write timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
WAIT high-level width
<50>
Delay time from address, CSn to
UWR, LWR, IOWR↓
T − 10
ns
tWWH
T − 10
ns
<51>
tDAWR
(0.5 + wAS)T − 10
ns
Address setup time (to UWR, LWR,
IOWR↑)
<52>
tSAWR
(1.5 + w + wD + wAS)T − 10
ns
Delay time from UWR, LWR, IOWR↑
to address
<53>
tDWRA
(0.5 + i)T − 10
ns
UWR, LWR, IOWR high-level width
<54>
tWWRH
(0.5 + i + wAS)T − 10
ns
UWR, LWR, IOWR low-level width
<55>
tWWRL
(1 + w + wD)T − 10
ns
Data output setup time (to UWR,
LWR, IOWR↑)
<56>
tSODWR
(0.5 + w + wD)T − 10
ns
Data output hold time (from UWR,
LWR, IOWR↑)
<57>
tHWROD
(0.5 + i)T − 8
ns
Note
For the first WAIT sampling when the wait count based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. n = 0 to 7
5. i: Idle state count
6. wAS: Address setup wait count based on the ASC register
Data Sheet U15578EJ1V0DS
31
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) Write timing (SRAM, external ROM, external I/O) (2/2)
TASW
T1
TW
T2
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
RD, IORD (output)
<52>
<51>
<54>
<53>
<55>
UWR, LWR, IOWR
(output)
<56>
<57>
D0 to D15 (I/O)
write → write
D0 to D15 (I/O)
read → write
<50>
<47>
WAIT (input)
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7
32
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
Conditions
MIN.
tSWK
MAX.
8
Unit
WAIT setup time (to CLKOUT↑)
<32>
ns
WAIT hold time (from CLKOUT↑)
<33>
tHKW
0
ns
RD low-level width
<41>
tWRDL
(1.5 + w + wD)T − 10
ns
RD high-level width
<42>
tWRDH
(0.5 + wAS + i)T − 10
ns
Delay time from address, CSn to RD↓
<43>
tDARD
(0.5 + wAS)T − 10
ns
Delay time from RD↑ to address
<44>
tDRDA
iT
ns
Delay time from RD↑ to data output
<46>
tDRDOD
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
WAIT high-level width
<50>
tWWH
Delay time from address to IOWR↓
<51>
Address setup time (to IOWR↑)
<52>
Delay time from IOWR↑ to address
(0.5 + i)T − 10
ns
T − 10
ns
T − 10
ns
tDAWR
(0.5 + wAS)T − 10
ns
tSAWR
(1.5 + w + wD + wAS)T − 10
ns
<53>
tDWRA
(1.5 + i)T − 10
ns
IOWR high-level width
<54>
tWWRH
(0.5 + i + wAS)T − 10
ns
IOWR low-level width
<55>
tWWRL
(1 + w + wD)T − 10
ns
Delay time from IOWR↑ to RD↑
<58>
tDIWRRD
1.5T − 10
ns
Delay time from DMAAKm↓ to IOWR↓
<59>
tDDAWR
(0.5 + wAS)T − 10
ns
Delay time from IOWR↑ to DMAAKm↑
<60>
tDWRDA
(1.5 + i)T − 10
ns
Note
For the first WAIT sampling when the number of waits based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. n = 0 to 7, m = 0 to 3
5. i: Idle state count
6. wAS: Address setup wait count based on the ASC register
Data Sheet U15578EJ1V0DS
33
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
TASW
T1
TW
T2
TF
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
<42>
<41>
<44>
RD (output)
<43>
<58>
UWR, LWR (output)
DMAAKm (output)
<59>
<60>
IORD (output)
<52>
<51>
<54>
<53>
<55>
IOWR (output)
<46>
D0 to D15 (I/O)
<47>
<33>
<32>
<33>
<32>
WAIT (input)
<50>
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
34
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
8
Unit
WAIT setup time (to CLKOUT↑)
<32>
tSWK
ns
WAIT hold time (from CLKOUT↑)
<33>
tHKW
0
ns
IORD low-level width
<41>
tWRDL
(2 + w + wD)T − 10
ns
IORD high-level width
<42>
tWRDH
(1 + i + wAS)T − 10
ns
Delay time from address, CSn to IORD↓
<43>
tDARD
(0.5 + wAS)T − 10
ns
Delay time from IORD↑ to address
<44>
tDRDA
(0.5 + i)T − 10
ns
Delay time from IORD↑ to data output
<46>
tDRDOD
(1 + i)T − 10
ns
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
T − 10
ns
WAIT high-level width
<50>
tWWH
T − 10
ns
Delay time from address to UWR, LWR↓
<51>
tDAWR
(0.5 + wAS)T − 10
ns
Address setup time (to UWR, LWR↑)
<52>
tSAWR
(1.5 + w + wD + wAS)T − 10
ns
Delay time from UWR, LWR↑ to address
<53>
tDWRA
(0.5 + i)T − 10
ns
UWR, LWR high-level width
<54>
tWWRH
(0.5 + i + wAS)T − 10
ns
UWR, LWR low-level width
<55>
tWWRL
(1 + w + wD)T − 10
ns
Delay time from UWR, LWR↑ to IORD↑
<61>
tDWRIRD
T − 10
ns
Delay time from DMAAKm↓ to IORD↓
<62>
tDDARD
(0.5 + wAS)T − 10
ns
Delay time from IORD↑ to DMAAKm↑
<63>
tDRDDA
(0.5 + i)T − 10
ns
Note For first WAIT sampling when wait count based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. n = 0 to 7, m = 0 to 3
5. i: Count of idle states inserted when a write cycle follows a read cycle
6. wAS: Address setup wait count based on the ASC register
Data Sheet U15578EJ1V0DS
35
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
TASW
T1
TW
T2
TF
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
<52>
<51>
<53>
<55>
<54>
UWR, LWR (output)
<61>
RD (output)
<62>
<63>
DMAAKm (output)
IOWR (output)
<43>
<42>
<41>
<44>
IORD (output)
<46>
D0 to D15 (I/O)
<47>
<33>
<32>
<33>
<32>
WAIT (input)
<50>
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
36
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(5) SRAM, external ROM, and external I/O access timing (vis-à-vis BUSCLK signal) (when BCP bit of BCP
register = 1)
(a) Access timing (SRAM, external ROM, external I/O)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to BUSCLK ↓)
<32>
tSWK
8
ns
WAIT hold time (from BUSCLK ↓)
<33>
tHKW
0.5T − 4
ns
WAIT hold time (from BUSCLK ↓)
<172> tHKW1
T+2
ns
Data input setup time (to BUSCLK ↓)
<34>
tSKID
8
ns
Data input hold time (from BUSCLK ↓)
<35>
tHKID
0.5T − 4
ns
Data output delay time (from BUSCLK ↓)
<36>
tDKOD1
T−5
T+8
ns
Data output delay time (from BUSCLK ↓)
<37>
tDKOD2
−5
+8
ns
Data float delay time (from BUSCLK ↓)
<38>
tHKOD
0.5T − 4
0.5T + 8
ns
Remarks 1. Maintain at least one of the data input hold times, tHRDID or tHKID.
2. T = Internal system clock cycle (this does not mean x2 bus cycle).
TW
T1
T2
T1
TW
T2
Internal system clock
BUSCLK (output)
<34>
<36>
<35>
<37>
D0 to D15 (I/O)
[when read]
<37>
<38>
D0 to D15 (I/O)
[when written]
<32> <33>
<32>
<172>
WAIT (input)
Remarks 1. This is the timing when the number of waits based on the DWC0 and DWC1 registers is zero.
2. Broken lines indicate high impedance.
Data Sheet U15578EJ1V0DS
37
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Read timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Data input setup time (to address)
<39>
tSAID
(2 + w + wD + wAS)T − 19
ns
Data input setup time (to RD)
<40>
tSRDID
(1.5 + w + wD)T − 19
ns
RD, IORD low-level width
<41>
tWRDL
(1.25 + w + wD)T − 10
ns
RD, IORD high-level width
<42>
tWRDH
(0.75 + wAS + i)T − 10
ns
Delay time from address, CSn,
to RD, IORD↓
<43>
tDARD
(0.75 + wAS)T − 10
ns
Delay time from RD, IORD↑ to address
<44>
tDRDA
iT
ns
Data input hold time (from RD, IORD↑)
<45>
tHRDID
0
ns
Delay time from RD, IORD↑ to data
output
<46>
tDRDOD
(0.25 + i)T − 10
ns
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
WAIT high-level width
<50>
tWWH
Data output hold time (from UWR,
LWR, IOWR↑)
<57>
tHWROD
Note
0.5T − 10
ns
T − 10
ns
(0.25 + i)T − 8
ns
For the first WAIT sampling when the wait count based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = BUSCLK cycle (internal system clock/2)
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. Maintain at least one of the data input hold times tHRDID or tHKID
5. n = 0 to 7
6. i: Idle state count
7. wAS: Address setup wait count based on the ASC register
38
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Read timing (SRAM, external ROM, external I/O) (2/2)
TASW
T1
TW
T2
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
UWR, LWR, IOWR
(output)
<42>
<41>
<44>
RD, IORD (output)
<43>
<57>
<40>
<39>
<46>
<45>
D0 to D15 (I/O)
<50>
<47>
WAIT (input)
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7
Data Sheet U15578EJ1V0DS
39
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) Write timing (SRAM, external ROM, external I/O) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to address)
<47>
tSAW
Note
(1 + wAS)T − 21
ns
WAIT setup time (to BCYST↓)
<48>
tSBSW
Note
(1 + wAS)T − 21
ns
WAIT hold time (from BCYST↑)
<49>
tHBSW
Note
WAIT high-level width
<50>
Delay time from address, CSn to
UWR, LWR, IOWR↓
0.5T − 10
ns
tWWH
T − 10
ns
<51>
tDAWR
(0.75 + wAS)T − 10
ns
Address setup time (to UWR, LWR,
IOWR↑)
<52>
tSAWR
(1.75 + w + wD + wAS)T − 10
ns
Delay time from UWR, LWR, IOWR↑
to address
<53>
tDWRA
(0.25 + i)T − 10
ns
UWR, LWR, IOWR high-level width
<54>
tWWRH
(1 + i + wAS)T − 10
ns
UWR, LWR, IOWR low-level width
<55>
tWWRL
(1 + w + wD)T − 10
ns
Data output setup time (to UWR,
LWR, IOWR↑)
<56>
tSODWR
(1.25 + w + wD)T − 10
ns
Data output hold time (from UWR,
LWR, IOWR↑)
<57>
tHWROD
(0.25 + i)T − 8
ns
Note
For the first WAIT sampling when the wait count based on the DWC0 and DWC1 registers is zero.
Remarks 1. T = BUSCLK cycle (internal system clock/2)
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. n = 0 to 7
5. i: Idle state count
6. wAS: Address setup wait count based on the ASC register
40
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) Write timing (SRAM, external ROM, external I/O) (2/2)
TASW
T1
TW
T2
TI
CLKOUT (output)
A0 to A25 (output)
CSn (output)
UBE, LBE (output)
RD, IORD (output)
<52>
<51>
<54>
<53>
<55>
UWR, LWR, IOWR
(output)
<56>
<57>
D0 to D15 (I/O)
write → write
D0 to D15 (I/O)
read → write
<50>
<47>
WAIT (input)
<48>
<49>
BCYST (output)
Remarks 1. This is the timing when the wait count based on the DWC0 and DWC1 registers is zero, the idle
state count based on the BCC register is 1, and the wait count based on the ASC register is 1.
2. Broken lines indicate high impedance.
3. n = 0 to 7
Data Sheet U15578EJ1V0DS
41
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(6) Page ROM access timing
(a) 8-bit bus width (halfword/word access), 16-bit bus width (word access) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT↑)
<32> tSWK
8
ns
WAIT hold time (from CLKOUT↑)
<33> tHKW
0
ns
Data input setup time (to CLKOUT↑)
<34> tSKID
8
ns
Data input hold time (from CLKOUT↑)
<35> tHKID
0
ns
Off-page data input setup time (to address)
<39> tSAID
(2 + w + wD + wAS)T − 21
ns
Off-page data input setup time (to RD)
<40> tSRDID
(1.5 + w + wD)T − 21
ns
Data input hold time (from RD↑)
<45> tHRDID
0
ns
Delay time from RD↑ to data output
<46> tDRDOD
(0.5 + i)T − 10
ns
On-page data input setup time (to address)
<64> tSOAID
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. wPR: Wait count based on the PRC register
5. i: Count of idle states inserted when a write cycle follows a read cycle
6. wAS: Address setup wait count based on the ASC register
7. Maintain at least one of the data input hold times tHKID or tHRDID
42
Data Sheet U15578EJ1V0DS
(2 + w + wPR + wAS)T − 21
ns
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(a) 8-bit bus width (halfword/word access), 16-bit bus width (word access) (2/2)
TASW
T1
TDW
TW
T2
TASW
TO1
TPRW
TW
TO2
CLKOUT (output)
CSn (output)
AddressNote
(output)
<34>
<39>
<64>
UWR, LWR (output)
<40>
RD (output)
<45>
<34>
<35>
<35>
D0 to D15 (I/O)
<33>
<33>
<32>
<33>
<32>
<32>
<32>
<33>
<46>
WAIT (input)
BCYST (output)
Note
On-page and off-page addresses are as follows.
PRC Register
MA6
MA5
MA4
MA3
On-Page
Address
Off-Page
Address
0
0
0
0
A0 to A2
A3 to A25
0
0
0
1
A0 to A3
A4 to A25
0
0
1
1
A0 to A4
A5 to A25
0
1
1
1
A0 to A5
A6 to A25
1
1
1
1
A0 to A6
A7 to A25
Remarks 1. This is the timing for the following case.
Wait count based on the DWC0 and DWC1 registers (TDW): 1
Wait count based on the PRC register (TPRW): 1
Wait count based on the ASC register (TASW): 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
Data Sheet U15578EJ1V0DS
43
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) 8-bit bus width (byte access), 16-bit bus width (byte/halfword access) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT↑)
<32>
tSWK
8
ns
WAIT hold time (from CLKOUT↑)
<33>
tHKW
0
ns
Data input setup time (to CLKOUT↑)
<34>
tSKID
8
ns
Data input hold time (from CLKOUT↑)
<35>
tHKID
0
ns
Off-page data input setup time (to address)
<39>
tSAID
(2 + w + wD + wAS)T − 21
ns
Off-page data input setup time (to RD)
<40>
tSRDID
(1.5 + w + wD)T − 21
ns
Off-page RD low-level width
<171> tWRDL
(1.5 + w + wD)T − 10
ns
RD high-level width
<172> tWRDH
(0.5 + wAS)T − 10
ns
Data input hold time (from RD↑)
<45>
tHRDID
0
ns
Delay time from RD↑ to data output
<46>
tDRDOD
(0.5 + i)T − 10
ns
On-page RD low-level width
<173> tWORDL
(1.5 + w + wPR)T − 10
ns
On-page data input setup time (to address)
<64>
On-page data input setup time (to RD)
<174> tSORDID
tSOAID
Remarks 1. T = tCYK
2. w: Wait count based on WAIT
3. wD: Wait count based on the DWC0 and DWC1 registers
4. wPR: Wait count based on the PRC register
5. i: Count of idle states inserted when a write cycle follows a read cycle
6. wAS: Address setup wait count based on the ASC register
7. Maintain at least one of the data input hold times tHKID or tHRDID
44
Data Sheet U15578EJ1V0DS
(2 + w + wPR + wAS)T − 21
ns
(1.5 + w + wPR)T − 21
ns
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) 8-bit bus width (byte access), 16-bit bus width (byte/halfword access) (2/2)
TASW
T1
TDW
TW
T2
TASW
TO1
TPRW
TW
TO2
CLKOUT (output)
CSn (output)
AddressNote
(output)
<34>
<39>
<64>
UWR, LWR (output)
<174>
<40>
<171>
<172>
<173>
RD (output)
<45>
<34>
<35>
<35>
D0 to D15 (I/O)
<33>
<33>
<32>
<33>
<32>
<32>
<32>
<33>
<46>
WAIT (input)
BCYST (output)
Note
On-page and off-page addresses are as follows.
PRC Register
MA6
MA5
MA4
MA3
On-Page
Address
Off-Page
Address
0
0
0
0
A0 to A2
A3 to A25
0
0
0
1
A0 to A3
A4 to A25
0
0
1
1
A0 to A4
A5 to A25
0
1
1
1
A0 to A5
A6 to A25
1
1
1
1
A0 to A6
A7 to A25
Remarks 1. This is the timing for the following case.
Wait count based on the DWC0 and DWC1 registers (TDW): 1
Wait count based on the PRC register (TPRW): 1
Wait count based on the ASC register (TASW): 1
2. Broken lines indicate high impedance.
3. n = 0 to 7
Data Sheet U15578EJ1V0DS
45
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(7) DRAM access timing
(a) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Conditions
MIN.
MAX.
8
Unit
Data input setup time (to CLKOUT↓)
<34>
tSKID
ns
Data input hold time (from CLKOUT↓)
<35>
tHKID
0
ns
Delay time from OE↑ to data output
<46>
tDRDOD
(1 + i)T − 10
ns
Read/write cycle time
<65>
tHPC
(1 + wDA + wCP)T − 10
ns
Row address setup time
<66>
tASR
0.5T − 10
ns
Row address hold time
<67>
tRAH
(0.5 + wRH)T − 10
ns
Column address setup time
<68>
tASC
0.5T − 10
ns
Column address hold time
<69>
tCAH
(0.5 + wDA)T − 10
ns
RAS precharge time
<70>
tRP
wRP = 0
T − 10
ns
wRP ≥ 1
wRPT − 10
ns
Column address read time (from
RAS↑)
<71>
tRAL
(1.5 + wCP + wDA)T − 10
ns
CAS hold time
<72>
tCSH
(1.5 + wRH + wDA)T − 10
ns
Delay time from RAS to column
address
<73>
tRAD
(0.5 + wRH)T − 10
ns
RAS to CAS delay time
<74>
tRCD
(1 + wRH)T − 10
ns
CAS to RAS precharge time
<75>
tCRP
wRP = 0
1.5T − 10
ns
wRP ≥ 1
(0.5 + wRP)T − 10
ns
(1.5 + wCP + wDA)T − 10
ns
wRP = 0
(3 + wRH)T − 10
ns
wRP ≥ 1
RAS hold time from CAS precharge
<76>
tRHCP
WE setup time (to CAS↓)
<77>
tRCS
(2 + wRP + wRH)T − 10
ns
WE hold time (from RAS↑)
<78>
tRRH
(1 + i)T − 10
ns
WE hold time (from CAS↑)
<79>
tRCH
(1.5 + i)T − 10
ns
RAS pulse width
<80>
tRASP
(2 + wRH + wDA)T − 10
ns
<81>
tHCAS
(0.5 + wDA)T − 10
ns
Off-page
CAS pulse width
CAS precharge time
CAS hold time from OE
Off-page
On-page
Access time to CAS precharge
<82>
tCP
<83>
tOCH1
<84>
tOCH2
<85>
tACP
(0.5 + wCP)T − 10
ns
wRP = 0
(2.5 + wRH + wDA)T − 10
ns
wRP ≥ 1
(1.5 + wRP + wRH + wDA)T − 10
ns
(0.5 + wCP + wDA)T − 10
ns
(1.5 + wCP + wDA)T − 21
ns
Data input hold time (from CAS↓)
<86>
tDHC
CAS access time
<87>
tCAC
(1 + wDA)T − 21
ns
Access time from column address
<88>
tAA
(1.5 + wDA)T − 21
ns
46
0
Data Sheet U15578EJ1V0DS
ns
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(a) Read timing (EDO DRAM) (2/3)
Parameter
Output enable access
time
Symbol
Off-page
<89>
tOEA1
Conditions
MIN.
MAX.
Unit
wRP = 0
(3 + wRP + wRH + wDA)T − 21
ns
wRP ≥ 1
(2 + wRP + wRH + wDA)T − 21
ns
<90>
tOEA2
(1 + wCP + wDA)T − 21
ns
RAS access time
<91>
tRAC
(2 + wRH + wDA)T − 21
ns
Output buffer turn-off delay time (from OE)
<92>
tOEZ
Off-page
0
ns
Cautions 1. At least one clock is inserted in wRP by default regardless of the setting of the RPC1n and
RPC0n bits in the SCRn register (n = 1, 3, 4, or 6)
2. The WAIT signal cannot be controlled using the BCYST signal when using EDO DRAM.
Remarks 1. T = tCYK
2. wDA: Wait count based on the DAC1n and DAC0n bits of the SCRn register (n = 1, 3, 4, 6)
3. wCP: Wait count based on the CPC1n and CPC0n bits of the SCRn register (n = 1, 3, 4, 6)
4. wRP: Wait count based on the RPC1n and RPC0n bits of the SCRn register (n = 1, 3, 4, 6)
5. wRH: Wait count based on the RHC1n and RHC0n bits of the SCRn register (n = 1, 3, 4, 6)
6. i: Idle state counts
Data Sheet U15578EJ1V0DS
47
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(a) Read timing (EDO DRAM) (3/3)
TRPW
Note 1
T1
TRHW
T2
TDAW
TCPW
TB
TDAW
TE
CLKOUT (output)
<68>
<66>
<67>
<69>
Row address
A0 to A25 (output)
Column address
Column address
<71>
<73>
<88>
<70>
<80>
RASn (output)
<72>
<75>
<76>
<74>
<81>
<82>
<87>
UCAS (output)
LCAS (output)
<77>
<65>
<81>
<78>
<85>
<79>
WE (output)
<84>
<83>
<90>
<34>
<46>
Note 2
OE (output)
<86>
<87>
<88>
<34>
<35>
Data
D0 to D15 (I/O)
<92>
<35>
Data
<91>
<89>
BCYST (output)
WAIT (input)
Notes
1. At least one clock is inserted in TRPW cycle.
2. During on-page access from other cycles while RAS is low level.
Remarks 1. This is the timing for the following case.
Wait count based on the RPC1n and RPC0n bits of the SCRn register (TRPW): 1
Wait count based on the RHC1n and RHC0n bits of the SCRn register (TRHW): 1
Wait count based on the DAC1n and DAC0n bits of the SCRn register (TDAW): 1
Wait count based on the CPC1n and CPC0n bits of the SCRn register (TCPW): 1
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6
48
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Write timing (EDO DRAM) (1/2)
Parameter
Symbol
Conditions
MIN.
wCP = 0
(2 + wDA)T − 10
wCP ≥ 1
MAX.
Unit
Read/write cycle time
<65>
tHPC
(1 + wDA + wCP)T − 10
ns
Row address setup time
<66>
tASR
0.5T − 10
ns
Row address hold time
<67>
tRAH
(0.5 + wRH)T − 10
ns
Column address setup time
<68>
tASC
0.5T − 10
ns
Column address hold time
<69>
tCAH
(0.5 + wDA)T − 10
ns
RAS precharge time
<70>
tRP
Column address read time (from RAS↓)
<71>
tRAL
ns
wRP = 0
T − 10
ns
wRP ≥ 1
wRPT − 10
ns
wCP = 0
(2.5 + wDA)T − 10
ns
wCP ≥ 1
(1.5 + wCP + wDA)T − 10
ns
CAS hold time
<72>
tCSH
(1.5 + wRH + wDA)T − 10
ns
Delay time from RAS to column address
<73>
tRAD
(0.5 + wRH)T − 10
ns
RAS to CAS delay time
<74>
tRCD
(1 + wRH)T − 10
ns
CAS to RAS precharge time
<75>
tCRP
wRP = 0
1.5T − 10
ns
wRP ≥ 1
(0.5 + wRP)T − 10
ns
wCP = 0
(2.5 + wDA)T − 10
ns
wCP ≥ 1
(1.5 + wCP + wDA)T − 10
ns
(2 + wRH + wDA)T − 10
ns
RAS hold time from CAS precharge
RAS pulse width
Off-page
<76>
tRHCP
<80>
tRASP
CAS pulse width
<81>
tHCAS
CAS precharge time
<82>
tCP
RAS hold time
WE setup time (to CAS↓)
Off-page
On-page
tRSH
<94>
tWCS1
<95>
tWCS2
ns
1.5T − 10
ns
wCP ≥ 1
(0.5 + wCP)T − 10
ns
(1 + wDA)T − 10
ns
wRP = 0
(2 + wRH)T − 10
ns
wRP ≥ 1
(1 + wRP + wRH)T − 10
ns
wCP = 0
T − 10
ns
wCP ≥ 1
wCPT − 10
ns
<96>
tWCH
(1 + wDA)T − 10
ns
Off-page
<97>
tDS1
(1.5 + wRH)T − 10
ns
On-page
<98>
tDS2
1.5T − 10
ns
<99>
tDH
<100>
tWP
WE hold time (from CAS↓)
Data setup time (to CAS↓)
<93>
(0.5 + wDA)T − 10
wCP = 0
wCP = 0
wCP ≥ 1
Data hold time (from CAS↓)
WE pulse width
On-page
(0.5 + wCP)T − 10
ns
(0.5 + wDA)T − 10
ns
wCP = 0
(2 + wDA)T − 10
ns
wCP ≥ 1
(1 + wDA + wCP)T − 10
ns
WE read time (from RAS↑)
On-page
<101>
tRWL
wCP = 0
(2 + wDA)T − 10
ns
wCP ≥ 1
(1 + wDA + wCP)T − 10
ns
WE read time (from CAS↑)
On-page
<102>
tCWL
wCP = 0
(1.5 + wDA)T − 10
ns
wCP ≥ 1
(0.5 + wDA + wCP)T − 10
ns
Data Sheet U15578EJ1V0DS
49
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Cautions 1. At least one clock is inserted in wRP by default regardless of the setting of the RPC1n and
RPC0n bits in the SCRn register (n = 1, 3, 4, 6).
2. At least one clock is inserted in wCP by default regardless of the setting of the CPC1n and
CPC0n bits in the SCRn register (n = 1, 3, 4, 6).
3. The WAIT signal cannot be controlled using the BCYST signal when using EDO DRAM.
Remarks 1. T = tCYK
2. wDA: Wait count based on the DAC1n and DAC0n bits of the SCRn register (n = 1, 3, 4, 6)
3. wCP: Wait count based on the CPC1n and CPC0n bits of the SCRn register (n = 1, 3, 4, 6)
4. wRP: Wait count based on the RPC1n and RPC0n bits of the SCRn register (n = 1, 3, 4, 6)
5. wRH: Wait count based on the RHC1n and RHC0n bits of the SCRn register (n = 1, 3, 4, 6)
50
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Write timing (EDO DRAM) (2/2)
Note 1
TRPW
Note 1
T1
TRHW
T2
TDAW
TCPW
TB
TDAW
TE
CLKOUT (output)
<66>
<68>
<67>
A0 to A25 (output)
<69>
Row address
<68>
Column address
<69>
Column address
<73>
<71>
<70>
<80>
RASn (output)
<72>
<75>
<74>
<76>
<81>
<82>
<93>
UCAS (output)
LCAS (output)
<65>
<81>
<102>
<101>
RD (output)
OE (output)
<95>
<94>
<96>
<100>
<96>
Note 2
WE (output)
<97>
D0 to D15 (I/O)
Read → Write
D0 to D15 (I/O)
Write → Write
<99>
<98>
Data
Data
<99>
Data
Data
BCYST (output)
WAIT (input)
Notes 1. At least one clock is inserted in TRPW and TCPW cycles.
2. During on-page access from other cycles while RAS is low level.
Remarks 1. This is the timing for the following case.
Wait count based on the RPC1n and RPC0n bits of the SCRn register (TRPW): 1
Wait count based on the RHC1n and RHC0n bits of the SCRn register (TRHW): 1
Wait count based on the DAC1n and DAC0n bits of the SCRn register (TDAW): 1
Wait count based on the CPC1n and CPC0n bits of the SCRn register (TCPW): 1
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6
Data Sheet U15578EJ1V0DS
51
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) DMA flyby transfer timing (EDO DRAM → external I/O transfer) (1/3)
Parameter
Symbol
Conditions
MIN.
tSWK
8
MAX.
Unit
WAIT setup time (to CLKOUT↑)
<32>
ns
WAIT hold time (from CLKOUT↑)
<33>
tHKW
0
ns
Delay time from OE↑ to data output
<46>
tDRDOD
(1 + i)T − 10
ns
Delay time from IOWR↑ to address
<53>
tDWRA
1.5T − 10
ns
IOWR low-level width
<55>
tWWRL
wRP = 0
(3 + wRH + wDA + w)T − 10
ns
wRP ≥ 1
(2 + wRP + wDA + wRH + w)T − 10
ns
Delay time from IOWR↑ to OE↑
<58>
tDWRRD
T − 10
ns
Row address setup time
<66>
tASR
0.5T − 10
ns
Row address hold time
<67>
tRAH
(0.5 + wRH)T − 10
ns
Column address setup time
<68>
tASC
0.5T − 10
ns
Column address hold time
<69>
tCAH
(2.5 + wDA + w)T − 10
ns
RAS precharge time
<70>
tRP
wRP = 0
T − 10
ns
wRP ≥ 1
wRPT − 10
ns
Column address read time (to RAS)
<71>
tRAL
(3.5 + wCP + wDA + w)T − 10
ns
CAS hold time
<72>
tCSH
(3 + wRH + wDA + w)T − 10
ns
RAS to column address delay time
<73>
tRAD
(0.5 + wRH)T − 10
ns
RAS to CAS delay time
<74>
tRCD
CAS to RAS precharge time
<75>
tCRP
RAS hold time from CAS precharge
<76>
tRHCP
WE setup time (to CAS↓)
<77>
tRCS
(1 + wRH)T − 10
ns
wRP = 0
2T − 10
ns
wRP ≥ 1
(1 + wRP)T − 10
ns
(4 + wCP + wDA + w)T − 10
ns
wRP = 0
(3 + wRH)T − 10
ns
wRP ≥ 1
(2 + wRP + wRH)T − 10
ns
WE hold time (from RAS↑)
<78>
tRRH
0
ns
WE hold time (from CAS↑)
<79>
tRCH
T − 10
ns
RAS pulse width
<80>
tRASP
(4 + wRH + wDA + w)T − 10
ns
<82>
tCP
(1 + wCP)T − 10
ns
Off-page
<83>
tOCH1
wRP = 0
(4 + wRH + wDA + w)T − 10
ns
wRP ≥ 1
(3 + wRP + wRH + wDA + w)T − 10
ns
On-page
<84>
tOCH2
(2 + wCP + wDA + w)T − 10
ns
Output buffer turn-off delay time
(from OE↑)
<92>
tOEZ
0
ns
RAS hold time
<93>
tRSH
(3 + wDA + w)T − 10
ns
Read/write cycle time
<103>
tRC
wRP = 0
(5.5 + wRH + wDA + w)T − 10
ns
wRP ≥ 1
(4.5 + wRP + wRH + wDA + w)T − 10
ns
CAS pulse width
<104>
tCAS
(2 + wDA + w)T − 10
ns
CAS precharge time
<105>
tCPN
WRP = 0
(3 + wRH)T − 10
ns
WRP ≥ 1
(2 + wRP + wRH)T − 10
ns
(3 + wCP + wDA + w)T − 10
ns
Off-page
CAS precharge time
OE → CAS hold time
High-speed page mode cycle time
52
<106>
tPC
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) DMA flyby transfer timing (EDO DRAM → external I/O transfer) (2/3)
Parameter
Symbol
Delay time from DMAAKm↓ to CAS↓
<107>
tDDACS
Delay time from IOWR↓ to CAS↓
<108>
tDRDCS
Output buffer turn-off delay time (from
CAS↑)
Cautions
<109>
Conditions
MIN.
MAX.
Unit
wRP = 0
(2.5 + wRH)T − 10
wRP ≥ 1
(1.5 + wRP + wRH)T − 10
ns
wRP = 0
(2 + wRH)T − 10
ns
wRP ≥ 1
(1 + wRP + wRH)T − 10
ns
0
ns
tOFF
ns
1. At least one clock is inserted in wRP by default regardless of the setting of the RPC1n and
RPC0n bits in the SCRn register (n = 1, 3, 4, 6).
2. The WAIT signal cannot be controlled using the BCYST signal when using EDO DRAM.
Remarks
1. T = tCYK
2. w: Wait count based on WAIT
3. wDA: Wait count based on the DAC1n and DAC0n bits of the SCRn register (n = 1, 3, 4, 6)
4. wCP: Wait count based on the CPC1n and CPC0n bits of the SCRn register (n = 1, 3, 4, 6)
5. wRP: Wait count based on the RPC1n and RPC0n bits of the SCRn register (n = 1, 3, 4, 6)
6. wRH: Wait count based on the RHC1n and RHC0n bits of the SCRn register (n = 1, 3, 4, 6)
7. i: Idle state count
8. m = 0 to 3
Data Sheet U15578EJ1V0DS
53
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(c) DMA flyby transfer timing (EDO DRAM → external I/O transfer) (3/3)
Note
TRPW
T1
TRHW
<66>
<68>
<67>
T2
TDAW
TW
TF
TE
TCPW
TB
TDAW
TW
TF
TE
CLKOUT (output)
<69>
Row address
A0 to A23 (output)
<70>
Column address
<73>
Column address
<71>
<80>
<103>
RASn (output)
<74>
<75>
UCAS (output)
LCAS (output)
<104>
<72>
<105>
<83>
<82>
<76>
<106>
<78>
<93>
<79>
<84>
<109>
OE (output)
<107>
<58>
DMAAKm (output)
<77>
WE (output)
IORD (output)
<108>
<46>
<53>
<55>
<92>
IOWR (output)
<32>
Data
D0 to D15 (I/O)
<33>
<32>
Data
<32>
<33>
<33>
WAIT (input)
BCYST (output)
Note At least one clock is inserted in TRPW cycle.
Remarks 1. This is the timing for the following case.
Wait count based on the RPC1n and RPC0n bits of the SCRn register (TRPW): 1
Wait count based on the RHC1n and RHC0n bits of the SCRn register (TRHW): 1
Wait count based on the DAC1n and DAC0n bits of the SCRn register (TDAW): 1
Wait count based on the CPC1n and CPC0n bits of the SCRn register (TCPW): 1
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6, m = 0 to 3
54
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(d) DMA flyby transfer timing (external I/O → EDO DRAM transfer) (1/3)
Parameter
Symbol
Conditions
MIN.
8
MAX.
Unit
WAIT setup time (to CLKOUT↑)
<32>
tSWK
ns
WAIT hold time (from CLKOUT↑)
<33>
tHKW
0
ns
IORD low-level width
<41>
tWRDL
(2 + wRH + wDA + w)T − 10
ns
IORD high-level width
<42>
tWRDH
T − 10
ns
Delay time from IORD↑ to address
<44>
tDRDA
(0.5 + i)T − 10
ns
Row address setup time
<66>
tASR
0.5T − 10
ns
Row address hold time
<67>
tRAH
(0.5 + wRH)T − 10
ns
Column address setup time
<68>
tASC
0.5T − 10
ns
Column address hold time
<69>
tCAH
(1.5 + wDA)T − 10
ns
RAS precharge time
<70>
tRP
wRP = 0
T − 10
ns
wRP ≥ 1
wRPT − 10
ns
Column address read time (from RAS)
<71>
tRAL
(2.5 + wCP + wDA + w)T − 10
ns
CAS hold time
<72>
tCSH
(2 + wRH + wDA + w)T − 10
ns
RAS to column address delay time
<73>
tRAD
(0.5 + wRH)T−10
ns
RAS to CAS delay time
<74>
tRCD
(1 + wRH + w)T − 10
ns
CAS to RAS precharge time
<75>
tCRP
wRP = 0
2T − 10
ns
wRP ≥ 1
(1 + wRP)T − 10
ns
RAS hold time from CAS precharge
<76>
tRHCP
(4 + wCP + wDA + w)T − 10
ns
RAS pulse width
<80>
tRASP
(3 + wRH + wDA + w)T − 10
ns
CAS precharge time
<82>
tCP
(1 + wCP + w)T − 10
ns
RAS hold time
<93>
tRSH
(2 + wDA)T − 10
ns
Read/write cycle time
<103>
tRC
wRP = 0
(4.5 + wRH + wDA + w)T − 10
ns
wRP ≥ 1
(3.5 + wRP + wRH + wDA + w)T − 10
ns
(1 + wDA)T − 10
ns
wRP = 0
(3 + wRH + w)T − 10
ns
wRP ≥ 1
(2 + wRP + wRH + w)T − 10
ns
(2 + wCP + wDA + w)T − 10
ns
wRP = 0
(2.5 + wRH + w)T − 10
ns
wRP ≥ 1
(1.5 + wRP + wRH + w)T − 10
ns
wRP = 0
(2 + wRH + w)T − 10
ns
wRP ≥ 1
(1 + wRP + wRH + w)T − 10
ns
tRWL
(3 + wDA + w)T − 10
ns
Off-page
CAS pulse width
<104>
tCAS
CAS precharge time
<105>
tCPN
High-speed page mode cycle time
<106>
tPC
Delay time from DMAAKm↓ to CAS↓
<107>
tDDACS
Delay time from IORD↓ to CAS↓
<108>
tDRDCS
WE read time (from RAS↑)
<110>
WE read time (from CAS↑)
<111>
tCWL
(2 + wDA + w)T − 10
ns
WE pulse width
<112>
tWP
(2 + wDA + w)T − 10
ns
Off-page
<113>
tWCS1
(2 + wRH + w)T − 10
ns
On-page
<114>
tWCS2
T − 10
ns
WE setup time (to
CAS↓)
Data Sheet U15578EJ1V0DS
55
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(d) DMA flyby transfer timing (external I/O → EDO DRAM transfer) (2/3)
Parameter
Symbol
WE hold time (from CAS↓)
<115>
tWCH
Delay time from WE↑ to IORD↑
<116>
tDWERD
Conditions
MIN.
MAX.
Unit
(1 + wDA)T − 10
ns
0
ns
Cautions 1. At least one clock is inserted in wRP by default regardless of the setting of the RPC1n and
RPC0n bits in the SCRn register (n = 1, 3, 4, 6).
2. At least one clock is inserted in wCP by default regardless of the setting of the CPC1n and
CPC0n bits in the SCRn register (n = 1, 3, 4, 6).
3. The WAIT signal cannot be controlled using the BCYST signal when using EDO DRAM.
Remarks
56
1.
2.
3.
4.
5.
6.
7.
8.
T = tCYK
w: Wait counts based on WAIT
wDA: Wait count based on the DAC1n and DAC0n bits of the SCRn register (n = 1, 3, 4, 6)
wCP: Wait count based on the CPC1n and CPC0n bits of the SCRn register (n = 1, 3, 4, 6)
wRP: Wait count based on the RPC1n and RPC0n bits of the SCRn register (n = 1, 3, 4, 6)
wRH: Wait count based on the RHC1n and RHC0n bits of the SCRn register (n = 1, 3, 4, 6)
i: Idle state count
m = 0 to 3
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(d) DMA flyby transfer timing (external I/O → EDO DRAM transfer) (3/3)
Note
TRPW
Note
T1
TRHW
TW
T2
TDAW
TE
TCPW
TW
TB
TDAW
TE
CLKOUT (output)
<66>
A0 to A23 (output)
<68>
<67>
<69>
Column address
Row address
<73>
<70>
Column address
<71>
<80>
<103>
RASn (output)
<74>
<75>
UCAS (output)
LCAS (output)
<104>
<93>
<82>
<72>
<105>
<106>
<76>
RD (output)
OE (output)
<114>
<110>
<111>
<115>
<113>
WE (output)
<112>
<107>
DMAAKm (output)
IOWR (output)
<108>
<116>
<44>
IORD (output)
<41>
<42>
<33>
Data
D0 to D15 (I/O)
<32>
<32>
<33>
<32>
Data
<33>
WAIT (input)
BCYST (output)
Note At least one clock is inserted in TRPW and TCPW cycles.
Remarks 1. This is the timing for the following case.
Wait count based on the RPC1n and RPC0n bits of the SCRn register (TRPW):
Wait count based on the RHC1n and RHC0n bits of the SCRn register (TRHW):
Wait count based on the DAC1n and DAC0n bits of the SCRn register (TDAW):
Wait count based on the CPC1n and CPC0n bits of the SCRn register (TCPW):
1
1
1
1
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6, m = 0 to 3
Data Sheet U15578EJ1V0DS
57
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(e) CBR refresh timing
Parameter
Symbol
RAS precharge time
<70>
Conditions
MIN.
MAX.
Unit
(1.5 + wRRW)T − 10
tRP
ns
RAS pulse width
<117>
tRAS
(1.5 + wRCW
)T − 10
ns
CAS hold time
<118>
tCHR
(0.5 + wRCWNote)T − 10
ns
Note
(3 + wRRW + wRCW
)T − 10
Note
REFRQ pulse width
<119>
tWRFL
ns
RAS precharge CAS hold time
<120>
tRPC
(2.5 + wRRW)T − 10
REFRQ active delay time (from CLKOUT↑)
<121>
tDKRF
2
13
ns
REFRQ inactive delay time (from
CLKOUT↑)
<122>
tHKRF
2
13
ns
CAS setup time
<123>
tCSR
T − 10
ns
ns
Note At least one clock is inserted in wRCW by default, regardless of the settings of the RCW0 to RCW2 bits of the
RWC register.
Remarks 1. T = tCYK
2. wRRW: Wait count based on the RRW0 and RRW1 bits of the RWC register
3. wRCW: Wait count based on the RCW0 to RCW2 bits of the RWC register
Note 1
TRRW
T1
T2
TRCW
Note 2
TRCW
T3
T4
TI
Note 2
TI
CLKOUT (output)
<122>
<121>
<119>
REFRQ (output)
<70>
<117>
RASn (output)
<120>
<123>
<118>
<120>
UCAS (output)
LCAS (output)
Notes 1.
At least one clock is inserted in TRCW, regardless of the settings of the RCW0 to RCW2 bits of the
RWC register.
2.
Idle state (TI) independent of the setting of the BCC register
Remarks 1. This is the timing for the following case.
Wait count based on the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Wait count based on the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 0 to 7
58
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(f) CBR self-refresh timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
REFRQ active delay time (from
CLKOUT↑)
<121>
tDKRF
2
13
ns
REFRQ inactive delay time (from
CLKOUT↑)
<122>
tHKRF
2
13
ns
CAS hold time
<124>
tCHS
−(wRCWT − 10)
ns
RAS precharge time
<125>
tRPS
wRP = 0
(3 + 2wSRW)T − 10
ns
wRP ≥ 1
(2 + 2wSRW + wRPW)T − 10
ns
Remarks 1. T = tCYK
2. wSRW: Wait count based on the SRW0 to SRW2 bits of the RWC register
3. wRCW: Wait count based on the RCW0 to RCW2 bits of the RWC register
4. wRPW: Wait count based on the RRW0 and RRW1 bits of the RWC register
Note
TRRW
TRCW
TSRW
TSRW
T1
CLKOUT (output)
<121>
<122>
REFRQ (output)
<125>
RASn (output)
<124>
UCAS (output)
LCAS (output)
Note At least one clock is inserted in TRCW, regardless of the settings of the RCW0 to RCW2 bits of the RWC
register.
Remarks 1. This is the timing for the following case.
Wait count based on the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Wait count based on the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Wait count based on the SRW0 to SRW2 bits of the RWC register (TSRW): 1 (Wait count of 2×
setting value is inserted)
2. 1, 3, 4, 6
Data Sheet U15578EJ1V0DS
59
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(8) SDRAM access timing
(a) Read timing (SDRAM access) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address delay time (from SDCLK↑)
<126>
tDKA
2
13
ns
BCYST delay time (from SDCLK↑)
<127>
tDKBC
2
13
ns
CSn delay time (from SDCLK↑)
<128>
tDKCS
2
13
ns
SDRAS delay time (from SDCLK↑)
<129>
tDKRAS
2
13
ns
SDCAS delay time (from SDCLK↑)
<130>
tDKCAS
2
13
ns
UDQM, LDQM delay time (from
SDCLK↑)
<131>
tDKDQM
2
13
ns
SDCKE delay time (from SDCLK↑)
<132>
tDKCKE
2
13
Data input setup time
(at SDRAM read, to SDCLK↑)
<133>
tSDRMK
8
ns
Data input hold time
(at SDRAM read, from SDCLK↑)
<134>
tHKDRM
0
ns
Delay time from SDCLK↑ to data output
<135>
tDSDOD
Remarks 1. T = tCYK2
2. i = Idle state count
3. n = 1, 3, 4, 6
60
Data Sheet U15578EJ1V0DS
(1 + i)T − 5
ns
ns
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(a) Read timing (SDRAM access) (2/2)
TW
TACT
TBCW
TREAD TLATE
TLATE
SDCLK (output)
<126>
<126>
Bank address and addresses
other than A10 and A0 to A9
(output)
Address
<126>
<126>
Address
Bank address (output)
<126>
<126>
Address
A10 (output)
<126>
Bank
address
Row
address
<126>
<126>
<126>
Row
Address address
A0 to A9 (output)
<127>
Column address
<127>
BCYST (output)
<128>
<128>
CSn (output)
<129>
<129>
SDRAS (output)
<130>
<130>
SDCAS (output)
RD (output)
OE (output)
WE (output)
<131>
<131>
<131>
<131>
LDQM (output)
UDQM (output)
<135>
<133> <134>
D0 to D15 (I/O)
Data
<132>
<132>
SDCKE (output)
Remarks 1. Wait count based on the BCW1n and BCW0n bits of the SCRn register (TBCW): 2
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6
Data Sheet U15578EJ1V0DS
61
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Write timing (SDRAM access) (1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address delay time (from SDCLK↑)
<126> tDKA
2
13
ns
BCYST delay time (from SDCLK↑)
<127> tDKBC
2
13
ns
CSn delay time (from SDCLK↑)
<128> tDKCS
2
13
ns
SDRAS delay time (from SDCLK↑)
<129> tDKRAS
2
13
ns
SDCAS delay time (from SDCLK↑)
<130> tDKCAS
2
13
ns
UDQM, LDQM delay time (from SDCLK↑)
<131> tDKDQM
2
13
ns
SDCKE delay time (from SDCLK↑)
<132> tDKCKE
2
13
ns
WE delay time (from SDCLK↑)
<136> tDKWE
2
13
ns
Data output delay time (from SDCLK↑)
<137> tDKDT
2
13
ns
Data float delay time (from SDCLK↑)
<138> tHZKDT
2
13
ns
Remark n = 1, 3, 4, 6
62
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(b) Write timing (SDRAM access) (2/2)
TW
TACT
TBCW
TWR1
TWR2
TWR3
SDCLK (output)
<126>
<126>
Bank address and addresses
other than A10 and A0 to A9
(output)
Address
<126>
Bank address (output)
<126>
Address
<126>
A10 (output)
Bank
address
<126>
Address
<126>
<126>
Row
address
<126>
<126>
Row
Address address
A0 to A9 (output)
<127>
Column address
<127>
BCYST (output)
<128>
<128>
CSn (output)
<129>
<129>
SDRAS (output)
<130>
<130>
<136>
<136>
<131>
<131>
<131>
<131>
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
<137>
D0 to D15 (I/O)
<138>
Data
<132>
<132>
SDCKE (output)
Remarks 1. Wait count based on the BCW1n and BCW0n bits of the SCRn register (TBCW): 2
2. Broken lines indicate high impedance.
3. n = 1, 3, 4, 6
Data Sheet U15578EJ1V0DS
63
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(9)
DMAC timing
Parameter
Symbol
DMARQn setup time
(to CLKOUT↑)
<139>
tSDRK
DMARQn hold time
<140>
tHKDR1
<141>
tHKDR2
Second DMA request disable
timing in single transfer
<142>
tAKDR
DMAAKn output delay time
(from CLKOUT↑)
<143>
tDKDA
DMAAKn output hold time
(from CLKOUT↑)
<144>
TCn output delay time (from
CLKOUT↑)
TCn output hold time
(from CLKOUT↑)
Conditions
MIN.
After inactive (from CLKOUT↑)
MAX.
8
ns
3
ns
Until DMAAKn↓
ns
3T
ns
2
13
ns
tHKDA
2
13
ns
<145>
tHKTC
2
13
ns
<146>
tHKTC
2
13
ns
Remarks 1. T = tCYK
2. n = 0 to 3
CLKOUT (output)
<141>
<140>
DMARQn (input)
<139>
<142>
<144>
<143>
DMAAKn (output)
<145>
<146>
TCn (output)
Remarks 1. In 2-cycle transfer, the TCn signal is output in the write cycle.
2. n = 0 to 3
64
Unit
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(10) Bus hold timing (1/2)
Parameter
Symbol
HLDRQ setup time (to CLKOUT↑)
<147>
HLDRQ hold time (from CLKOUT↑)
Delay time from CLKOUT↑ to HLDAK
Conditions
MIN.
MAX.
Unit
tSHRK
8
<148>
tHKHR
3
<149>
tDKHA
2
HLDRQ high-level width
<150>
tWHQH
T+3
ns
HLDAK low-level width
<151>
tWHAL
T − 11
ns
Delay time from HLDAK↓ to bus float
<152>
tDKCF
0
ns
Delay time from HLDAK↑ to bus output
<153>
tDHAC
Delay time from HLDRQ↓ to HLDAK↓
<154>
tDHQHA1
2T
Delay time from HLDRQ↑ to HLDAK↑
<155>
tDHQHA2
T
Remark
2
ns
ns
13
13
ns
ns
ns
2T + 10
ns
T = tCYK
Data Sheet U15578EJ1V0DS
65
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(10) Bus hold timing (2/2)
TI
TH
TH
TH
TI
CLKOUT (output)
<148>
<147>
<148>
<147>
<147>
<150>
HLDRQ (input)
<149>
<149>
<154>
<155>
HLDAK (output)
<151>
<152>
A0 to A25 (output)
D0 to D15 (I/O)
Address
Data
CSn/RASn (output)
BCYST (output)
RD (output)
WE (output)
UCAS (output)
LCAS (output)
WAIT (input)
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 7
66
Data Sheet U15578EJ1V0DS
<153>
Undefined
T1
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(11) Interrupt timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
NMI high-level width
<156>
tWNIH
500
ns
NMI low-level width
<157>
tWNIL
500
ns
INTP0nm high-level width
<158>
tWIT0H
3T + 500
ns
INTP0nm low-level width
<159>
tWIT0L
3T + 500
ns
INTP1nm high-level width
<160>
tWIT1H
500
ns
INTP1nm low-level width
<161>
tWIT1L
500
ns
Remarks 1. INTP0nm: n = 0 to 3, m = 0, 1
INTP1nm: n = 0 to 3, m = 0 to 3
2. T = tCYK
<156>
<157>
<158>
<159>
<160>
<161>
NMI (input)
INTP0nm (input)
INTP1nm (input)
Remark
INTP0nm: n = 0 to 3, m = 0, 1
INTP1nm: n = 0 to 3, m = 0 to 3
(12) RPU timing
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
TI0n0 high-level width
<162>
tWTIH
3T + 500
ns
TI0n0 low-level width
<163>
tWTIL
3T + 500
ns
Remarks 1. n = 0 to 3
2. T = tCYK
<162>
<163>
TI0n0 (input)
Remark
n = 0 to 3
Data Sheet U15578EJ1V0DS
67
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(13) CSI0 to CSI2 timing (1/3)
(a) Master mode
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<164>
tCYSK1
Output
320
ns
SCKn high-level width
<165>
tWSK1H
Output
0.5tCYSK1 − 20
ns
SCKn low-level width
<166>
tWSK1L
Output
0.5tCYSK1 − 20
ns
SIn setup time (to SCKn↑)
<167>
tSSISK
30
ns
30
ns
30
ns
30
ns
SIn setup time (to SCKn ↓)
SIn hold time (from SCKn↑)
<168>
tHSKSI
SIn hold time (from SCKn ↓)
SOn output delay time (from SCKn↓)
<169>
tDSKSO
SOn output delay time (from SCKn ↑)
SOn output hold time (from SCKn↑)
<170>
tHSKSO
SOn output hold time (from SCKn ↓)
30
ns
30
ns
0.5tCYSK1 − 5
ns
0.5tCYSK1 − 5
ns
Remark n = 0 to 2
(b) Slave mode
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<164>
tCYSK1
Input
200
ns
SCKn high-level width
<165>
tWSK1H
Input
90
ns
SCKn low-level width
<166>
tWSK1L
Input
90
ns
SIn setup time (to SCKn↑)
<167>
tSSISK
50
ns
50
ns
SIn setup time (to SCKn ↓)
SIn hold time (from SCKn↑)
<168>
tHSKSI
SIn hold time (from SCKn ↓)
SOn output delay time (from SCKn↓)
<169>
50
ns
50
ns
tDSKSO
SOn output delay time (from SCKn ↑)
SOn output hold time (from SCKn↑)
<170>
tHSKSO
SOn output hold time (from SCKn ↓)
Remark n = 0 to 2
68
Data Sheet U15578EJ1V0DS
50
ns
50
ns
tWSK1H
ns
tWSK1H
ns
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(13) CSI0 to CSI2 timing (2/3)
(c) Timing when CKPn, DAPn bits of CSICn register = 00
<164>
<166>
<165>
SCKn (I/O)
<167>
SIn (input)
<168>
Input data
<169>
<170>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 2
(d) Timing when CKPn, DAPn bits of CSICn register = 01
<164>
<166>
<165>
SCKn (I/O)
<167>
SIn (input)
<168>
Input data
<169>
<170>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 2
Data Sheet U15578EJ1V0DS
69
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
(13) CSI0 to CSI2 timing (3/3)
(e) Timing when CKPn, DAPn bits of CSICn register = 10
<164>
<166>
<165>
SCKn (I/O)
<167>
SIn (input)
<168>
Input data
<169>
<170>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 2
(f) Timing when CKPn, DAPn bits of CSICn register = 11
<164>
<166>
<165>
SCKn (I/O)
<167>
SIn (input)
<168>
Input data
<169>
<170>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 2
70
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
A/D Converter Characteristics (TA = −40 to +85°°C, VDD = AVDD = 3.0 to 3.6 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
−
Resolution
TYP.
MAX.
10
Unit
bit
Overall error
−
±0.49
%FSR
Quantization error
−
±1/2
LSB
10
µs
Note 1
Conversion time
tCONV
5
Sampling time
tSAMP
Conversion
clockNote 2/6
ns
−
±0.49
%FSR
Full-scale error
−
±0.49
%FSR
Integral linearity errorNote 3
−
±4
LSB
−
±4
LSB
−0.3
AVREF + 0.3
V
3.0
3.6
V
10
mA
Zero-scale errorNote 1
Note 3
Note 3
Differential linearity error
Analog input voltage
VWASN
AVREF input voltage
AVREF
AVDD supply current
AIDD
Notes 1.
Remark
AVREF = AVDD
Excluding quantization error (±0.05 %FSR)
2.
Conversion clock is the number of clocks set by the ADM1 resister.
3.
Excluding quantization error (±0.5 LSB)
LSB: Least Significant Bit
FSR: Full Scale Range
%FSR is the ratio to the full-scale value.
Data Sheet U15578EJ1V0DS
71
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
5. PACKAGE DRAWING
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
A
MILLIMETERS
22.0±0.2
B
C
20.0±0.2
20.0±0.2
D
22.0±0.2
F
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
K
1.0±0.2
L
0.5±0.2
M
0.17 +0.03
−0.07
N
P
0.08
1.4
Q
0.10±0.05
R
3° +4°
−3°
S
1.5±0.1
S144GJ-50-UEN
72
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
161-PIN PLASTIC FBGA (13x13)
ZE
ZD
w
E
S B
B
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
D
P NML K J HG F E DCB A
w
INDEX MARK
S A
A
y1
A2
S
S
y
e
S
φb
φx
M
A1
S AB
ITEM
D
MILLIMETERS
13.00±0.10
E
13.00±0.10
w
0.20
A
A1
1.48±0.10
A2
0.35±0.06
1.13
e
0.80
b
0.50 +0.05
−0.10
x
0.08
y
y1
0.10
0.20
ZD
1.30
ZE
1.30
P161F1-80-EN4-1
Data Sheet U15578EJ1V0DS
73
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
6. RECOMMENDED SOLDERING CONDITIONS
The µPD703103A, 703105A, 703106A, 703106A(A), 703107A, and 703107A(A) should be soldered and mounted
under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 6-1. Surface Mounting Type Soldering Conditions
(1) µPD703106AGJ-×××
×××-UEN:
144-pin plastic LQFP (fine pitch) (20 × 20)
×××
×××-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703107AGJ-×××
×××
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 to 72 hours)
IR35-103-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 to 72 hours)
VP15-103-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
–
(2) µPD703106AF1-×××
×××-EN4:
161-pin plastic FBGA (13 × 13)
×××
×××-EN4: 161-pin plastic FBGA (13 × 13)
µPD703107AF1-×××
×××
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 to 72 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less
Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 to 72 hours)
VP15-107-2
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note
–
After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
Remark The soldering conditions for the following product is undetermined.
• µPD703103AGJ-×××-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
• µPD703105AGJ-×××-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
• µPD703106AGJ(A)-×××-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
• µPD703107AGJ(A)-×××-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
74
Recommended
Condition
Symbol
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
APPENDIX NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board and
conversion connector. Design your system making allowances for conditions such as the form of parts mounted on
the target system as shown below.
Appendix-1. 144-pin Plastic LQFP (Fine Pitch) (20 × 20)
Side View
In-circuit emulator
IE-V850E-MC-A
In-circuit emulator
option board
IE-703107-MC-EM1
206.26 mm
Note
Conversion connector
YQGUIDE
YQPACK144SD
NQPACK144SD
Target system
Note YQSOCKET144SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm).
Top View
IE-V850E-MC-A
Target system
IE-703107-MC-EM1
YQPACK144SD, NQPACK144SD,
YQGUIDE
Connection condition diagram
IE-703107-MC-EM1
Connect to IE-V850E-MC-A.
75 mm
YQGUIDE
YQPACK144SD
NQPACK144SD
13.3 mm
31.84 mm
17.99 mm
27.205 mm
Remark
21.58 mm
Target system
The connector for the 161-pin plastic FBGA package is under development.
Data Sheet U15578EJ1V0DS
75
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Related document µPD70F3107A, 70F3107A(A) Data Sheet (U15846E)
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MA1 and V850 Series are trademarks of NEC Corporation.
76
Data Sheet U15578EJ1V0DS
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (France) S.A.
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Vélizy-Villacoublay, France
Tel: 01-3067-58-00
Fax: 01-3067-58-99
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
NEC Electronics Hong Kong Ltd.
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 0211-65 03 327
• Branch The Netherlands
Eindhoven, The Netherlands
Tel: 040-244 58 45
Fax: 040-244 45 80
Representación en España
Madrid, Spain
Tel: 091-504-27-87
Fax: 091-504-28-60
NEC Electronics Italiana S.R.L.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.12
Data Sheet U15578EJ1V0DS
77
µPD703103A, 703105A, 703106A, 703106A(A), 703107A, 703107A(A)
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed: µPD703103A
The customer must judge the need for license: µPD703105A, 703106A, 703106A(A), 703107A, 703107A(A)
• The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
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Customers must check the quality grade of each semiconductor product before using it in a particular
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4