DATA SHEET MOS INTEGRATED CIRCUITS µPD70F3102-33 TM V850E/MS1 32-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD70F3102-33 is a product that substitutes the internal mask ROM of the µPD703102-33 with flash memory. This enables users to perform on-board program writing and erasure, enabling effective evaluation during system development, small-lot production of multiple devices, and rapid production start, and quick development and time-to-market. A version using a 3.3 V power supply for external pins, the µPD70F3102A-33, is also available. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. V850E/MS1 User’s Manual Hardware: U12688E V850E/MS1 User’s Manual Architecture: U12197E FEATURES • Compatible with µPD703102-33 Can be replaced by the µPD703102-33 with internal mask ROM for mass production • Internal flash memory: 128 KB ORDERING INFORMATION Part Number Package µPD70F3102GJ-33-8EU 144-pin plastic LQFP (fine pitch) (20 × 20) µPD70F3102GJ-33-UEN Note 144-pin plastic LQFP (fine pitch) (20 × 20) Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13844EJ3V0DS00 (3rd edition) Date Published May 2001 N CP(K) Printed in Japan The mark shows major revised points. © 1999 µPD70F3102-33 PIN CONFIGURATION (TOP VIEW) 144-pin plastic LQFP (fine pitch) (20 × 20) • µPD70F3102GJ-33-8EU 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD D0/P40 D1/P41 D2/P42 D3/P43 D4/P44 D5/P45 D6/P46 D7/P47 VSS D8/P50 D9/P51 D10/P52 D11/P53 D12/P54 D13/P55 D14/P56 D15/P57 HVDD A0/PA0 A1/PA1 A2/PA2 A3/PA3 A4/PA4 A5/PA5 A6/PA6 A7/PA7 VSS A8/PB0 A9/PB1 A10/PB2 A11/PB3 A12/PB4 A13/PB5 A14/PB6 A15/PB7 • µPD70F3102GJ-33-UEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NMI/P20 P21 TXD0/SO0/P22 RXD0/SI0/P23 SCK0/P24 TXD1/SO1/P25 RXD1/SI1/P26 SCK1/P27 VDD INTP133/SCK2/P37 INTP132/SI2/P36 INTP131/SO2/P35 INTP130/P34 TI13/P33 TCLR13/P32 TO131/P31 TO130/P30 INTP143/SCK3/P117 INTP142/SI3/P116 INTP141/SO3/P115 INTP140/P114 TI14/P113 TCLR14/P112 TO141/P111 TO140/P110 CVDD X2 X1 CVSS CKSEL MODE0 MODE1 MODE2 MODE3/VPP RESET INTP153/ADTRG/P127 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 INTP103/DMARQ3/P07 INTP102/DMARQ2/P06 INTP101/DMARQ1/P05 INTP100/DMARQ0/P04 TI10/P03 TCLR10/P02 TO101/P01 TO100/P00 VSS INTP113/DMAAK3/P17 INTP112/DMAAK2/P16 INTP111/DMAAK1/P15 INTP110/DMAAK0/P14 TI11/P13 TCLR11/P12 TO111/P11 TO110/P10 INTP123/TC3/P107 INTP122/TC2/P106 INTP121/TC1/P105 INTP120/TC0/P104 TI12/P103 TCLR12/P102 TO121/P101 TO120/P100 ANI7/P77 ANI6/P76 ANI5/P75 ANI4/P74 ANI3/P73 ANI2/P72 ANI1/P71 ANI0/P70 AVDD AVSS AVREF 2 Data Sheet U13844EJ3V0DS A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66 A23/P67 HVDD CS0/RAS0/P80 CS1/RAS1/P81 CS2/RAS2/P82 CS3/RAS3/P83 CS4/RAS4/IOWR/P84 CS5/RAS5/IORD/P85 CS6/RAS6/P86 CS7/RAS7/P87 LCAS/LWR/P90 UCAS/UWR/P91 RD/P92 WE/P93 BCYST/P94 OE/P95 HLDAK/P96 HLDRQ/P97 VSS REFRQ/PX5 WAIT/PX6 CLKOUT/PX7 TO150/P120 TO151/P121 TCLR15/P122 TI15/P123 INTP150/P124 INTP151/P125 INTP152/P126 µPD70F3102-33 PIN IDENTIFICATION A0 to A23: Address bus P50 to P57: Port 5 ADTRG: AD trigger input P60 to P67: Port 6 ANI0 to ANI7: Analog input P70 to P77: Port 7 AVDD: Analog power supply P80 to P87: Port 8 AVREF: Analog reference voltage P90 to P97: Port 9 AVSS: Analog ground P100 to P107: Port 10 BCYST: Bus cycle start timing P110 to P117: Port 11 CKSEL: Clock generator operating mode P120 to P127: Port 12 select PA0 to PA7: Port A CLKOUT: Clock output PB0 to PB7: Port B CS0 to CS7: Chip select PX5 to PX7: Port X CVDD: Clock generator power supply RAS0 to RAS7: Row address strobe CVSS: Clock generator RD: Read D0 to D15: Data bus REFRQ: Refresh request DMAAK0 to DMAAK3: DMA acknowledge RESET: Reset DMARQ0 to DMARQ3: DMA request RXD0, RXD1: Receive data HLDAK: Hold acknowledge SCK0 to SCK3: Serial clock HLDRQ: Hold request SI0 to SI3: Serial input HVDD: Power supply for external pins SO0 to SO3: Serial output TC0 to TC3: Terminal count signal INTP100 to INTP103, INTP110 to INTP113, TCLR10 to TCLR15: Timer clear INTP120 to INTP123, TI10 to TI15: INTP130 to INTP133, TO100, TO101, INTP140 to INTP143, TO110, TO111, Timer input INTP150 to INTP153: Interrupt request from peripherals TO120, TO121, IORD: I/O read strobe TO130, TO131, IOWR: I/O write strobe TO140, TO141, LCAS: Lower column address strobe TO150, TO151: Timer output LWR: Lower write strobe TXD0, TXD1: Transmit data MODE0 to MODE3: Mode UCAS: Upper column address strobe NMI: Non-maskable interrupt request UWR: Upper write strobe OE: Output enable VDD: Power supply for internal unit P00 to P07: Port 0 VPP: Programming power supply P10 to P17: Port 1 VSS: Ground P20 to P27: Port 2 WAIT: Wait P30 to P37: Port 3 WE: Write enable P40 to P47: Port 4 X1, X2: Crystal Data Sheet U13844EJ3V0DS 3 µPD70F3102-33 INTERNAL BLOCK DIAGRAM HLDRQ NMI INTP100 to INTP103, INTP110 to INTP113, INTP120 to INTP123, INTP130 to INTP133, INTP140 to INTP143, INTP150 to INTP153 CPU Flash memory BCU HLDAK INTC CS0 to CS7/RAS0 to RAS7 IOWR Instruction queue IORD Multiplier (32 × 32 → 64) 128 KB DRAMC REFRQ BCYST PC TO100, TO101, TO110, TO111, TO120, TO121, TO130, TO131, TO140, TO141, TO150, TO151 WE RD Barrel shifter RPU RAM System registers 4 KB General-purpose registers (32 bits × 32) Page ROM controller OE UWR/UCAS LWR/LCAS TCLR10 to TCLR15 TI10 to TI15 WAIT ALU A0 to A23 D0 to D15 DMAC DMARQ0 to DMARQ3 DMAAK0 to DMAAK3 SIO SO0/TXD0 SI0/RXD0 SCK0 TC0 to TC3 UART0/CSI0 BRG0 SO1/TXD1 SI1/RXD1 SCK1 CKSEL Port UART1/CSI1 CLKOUT CG SO3 SI3 SCK3 HVDD P00 to P07 P20 P10 to P17 P21 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 P100 to P107 PA0 to PA7 P110 to P117 BRG2 P120 to P127 CSI2 PB0 to PB7 SO2 SI2 SCK2 PX5 to PX7 BRG1 X1 X2 CVDD CVSS System controller MODE0 to MODE3 RESET VPP CSI3 VDD ANI0 to ANI7 AVREF AVSS AVDD ADTRG 4 VSS ADC Data Sheet U13844EJ3V0DS µPD70F3102-33 CONTENTS 1. DIFFERENCES AMONG PRODUCTS....................................................................................................6 1.1 Differences Between µPD70F3102-33 and µPD703102-33........................................................................6 1.2 Differences Between µPD70F3102-33 and µPD70F3102A-33 ...................................................................6 2. PIN FUNCTIONS .....................................................................................................................................7 2.1 Port Pins .......................................................................................................................................................7 2.2 Non-Port Pins .............................................................................................................................................10 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins ................................................14 3. FLASH MEMORY PROGRAMMING ....................................................................................................17 3.1 Selection of Communication Mode ..........................................................................................................17 3.2 Flash Memory Programming Functions ..................................................................................................18 3.3 Connecting the Dedicated Flash Programmer ........................................................................................18 4. ELECTRICAL SPECIFICATIONS .........................................................................................................19 4.1 Normal Operation Mode ............................................................................................................................19 4.2 Flash Memory Programming Mode ..........................................................................................................74 5. PACKAGE DRAWINGS ........................................................................................................................77 6. RECOMMENDED SOLDERING CONDITIONS....................................................................................79 Data Sheet U13844EJ3V0DS 5 µPD70F3102-33 1. DIFFERENCES AMONG PRODUCTS 1.1 Differences Between µPD70F3102-33 and µPD703102-33 µPD70F3102-33 Product µPD703102-33 Item Internal ROM Flash memory Mask ROM Flash memory programming pin Provided (VPP) None Flash memory programming mode Provided (MODE0 = L, MODE1 = H, MODE2 = L, MODE3/VPP = 7.8 V) None Electrical specifications Current consumption etc. differs (see individual data sheets). Others Circuit scale and master layout differ, thus noise immunity, noise radiation, etc. differ. Cautions 1. There are differences in noise immunity and noise radiation between the flash memory version and mask ROM version. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluation for commercial samples (not engineering samples) of the mask ROM version. 2. When switching from the flash memory version to the mask ROM version, write the same code to the free area of the internal ROM. 1.2 Differences Between µPD70F3102-33 and µPD70F3102A-33 µPD70F3102-33 Product µPD70F3102A-33 Item 6 HVDD 4.5 to 5.5 V 3.0 to 3.6 V Electrical specifications See individual data sheets. Package • 144-pin plastic LQFP (fine pitch) (20 × 20) Data Sheet U13844EJ3V0DS • 157-pin plastic FBGA (14 × 14) • 144-pin plastic LQFP (fine pitch) (20 × 20) µPD70F3102-33 2. PIN FUNCTIONS 2.1 Port Pins (1/3) Pin Name P00 I/O I/O P01 P02 Function Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function TO100 TO101 TCLR10 P03 TI10 P04 INTP100/DMARQ0 P05 INTP101/DMARQ1 P06 INTP102/DMARQ2 P07 INTP103/DMARQ3 P10 I/O P11 P12 Port 1 8-bit I/O port Input/output can be specified in 1-bit units. TO110 TO111 TCLR11 P13 TI11 P14 INTP110/DMAAK0 P15 INTP111/DMAAK1 P16 INTP112/DMAAK2 P17 INTP113/DMAAK3 P20 Input P21 I/O P22 P23 P24 Port 2 P20 is an input-only port. When a valid edge is input, it operates as an NMI input. The status of the NMI input is shown by bit 0 of register P2. P21 to P27 is a 7-bit I/O port. Input/output can be specified in 1-bit units. NMI − TXD0/SO0 RXD0/SI0 SCK0 P25 TXD1/SO1 P26 RXD1/SI1 P27 SCK1 P30 I/O P31 P32 Port 3 8-bit I/O port Input/output can be specified in 1-bit units. TO130 TO131 TCLR13 P33 TI13 P34 INTP130 P35 INTP131/SO2 P36 INTP132/SI2 P37 INTP133/SCK2 P40 to P47 I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Data Sheet U13844EJ3V0DS D0 to D7 7 µPD70F3102-33 (2/3) Pin Name I/O P50 to P57 I/O Port 5 8-bit I/O port Input/output can be specified in 1-bit units. D8 to D15 P60 to P67 I/O Port 6 8-bit I/O port Input/output can be specified in 1-bit units. A16 to A23 P70 to P77 Input Port 7 8-bit input-only port ANI0 to ANI7 Port 8 8-bit I/O port Input/output can be specified in 1-bit units. CS0/RAS0 P80 I/O P81 P82 Alternate Function CS1/RAS1 CS2/RAS2 P83 CS3/RAS3 P84 CS4/RAS4/IOWR P85 CS5/RAS5/IORD P86 CS6/RAS6 P87 CS7/RAS7 P90 I/O P91 P92 Port 9 8-bit I/O port Input/output can be specified in 1-bit units LCAS/LWR UCAS/UWR RD P93 WE P94 BCYST P95 OE P96 HLDAK P97 HLDRQ P100 P101 P102 8 Function I/O Port 10 8-bit I/O port Input/output can be specified in 1-bit units. TO120 TO121 TCLR12 P103 TI12 P104 INTP120/TC0 P105 INTP121/TC1 P106 INTP122/TC2 P107 INTP123/TC3 Data Sheet U13844EJ3V0DS µPD70F3102-33 (3/3) Pin Name P110 I/O I/O P111 P112 Function Port 11 8-bit I/O port Input/output can be specified in 1-bit units. Alternate Function TO140 TO141 TCLR14 P113 TI14 P114 INTP140 P115 INTP141/SO3 P116 INTP142/SI3 P117 INTP143/SCK3 P120 I/O P121 P122 Port 12 8-bit I/O port Input/output can be specified in 1-bit units. TO150 TO151 TCLR15 P123 TI15 P124 INTP150 P125 INTP151 P126 INTP152 P127 INTP153/ADTRG PA0 I/O PA1 PA2 Port A 8-bit I/O port Input/output can be specified in 1-bit units. A0 A1 A2 PA3 A3 PA4 A4 PA5 A5 PA6 A6 PA7 A7 PB0 I/O PB1 PB2 Port B 8-bit I/O port Input/output can be specified in 1-bit units. A8 A9 A10 PB3 A11 PB4 A12 PB5 A13 PB6 A14 PB7 A15 PX5 PX6 PX7 I/O Port X 3-bit I/O port Input/output can be specified in 1-bit units. Data Sheet U13844EJ3V0DS REFRQ WAIT CLKOUT 9 µPD70F3102-33 2.2 Non-Port Pins (1/4) Pin Name TO100 I/O Output Function Pulse signal output of timers 10 to 15 Alternate Function P00 TO101 P01 TO110 P10 TO111 P11 TO120 P100 TO121 P101 TO130 P30 TO131 P31 TO140 P110 TO141 P111 TO150 P120 TO151 P121 TCLR10 Input External clear signal input of timers 10 to 15 P02 TCLR11 P12 TCLR12 P102 TCLR13 P32 TCLR14 P112 TCLR15 P122 TI10 Input External count clock input of timers 10 to 15 P03 TI11 P13 TI12 P103 TI13 P33 TI14 P113 TI15 P123 INTP100 Input INTP101 External maskable interrupt request input, or timer 10 external capture trigger input P04/DMARQ0 P05/DMARQ1 INTP102 P06/DMARQ2 INTP103 P07/DMARQ3 INTP110 Input INTP111 External maskable interrupt request input, or timer 11 external capture trigger input P14/DMAAK0 P15/DMAAK1 INTP112 P16/DMAAK2 INTP113 P17/DMAAK3 INTP120 INTP121 Input External maskable interrupt request input, or timer 12 external capture trigger input P104/TC0 P105/TC1 INTP122 P106/TC2 INTP123 P107/TC3 10 Data Sheet U13844EJ3V0DS µPD70F3102-33 (2/4) Pin Name INTP130 I/O Input INTP131 Function External maskable interrupt request input, or timer 13 external capture trigger input Alternate Function P34 P35/SO2 INTP132 P36/SI2 INTP133 P37/SCK2 INTP140 Input INTP141 External maskable interrupt request input, or timer 14 external capture trigger input P114 P115/SO3 INTP142 P116/SI3 INTP143 P117/SCK3 INTP150 Input INTP151 External maskable interrupt request input, or timer 15 external capture trigger input P124 P125 INTP152 P126 INTP153 P127/ADTRG SO0 Output CSI0 to CSI3 serial transmission data output (3-wire) P22/TXD0 SO1 P25/TXD1 SO2 P35/INTP131 SO3 P115/INTP141 SI0 Input CSI0 to CSI3 serial reception data input (3-wire) P23/RXD0 SI1 P26/RXD1 SI2 P36/INTP132 SI3 P116/INTP142 SCK0 I/O CSI0 to CSI3 serial clock input/output (3-wire) P24 SCK1 P27 SCK2 P37/INTP133 SCK3 P117/INTP143 TXD0 Output UART0 and UART1 serial transmission data output TXD1 RXD0 P25/SO1 Input UART0 and UART1 serial reception data input RXD1 D0 to D7 P23/SI0 P26/SI1 I/O 16-bit data bus for external memory D8 to D15 A0 to A7 P22/SO0 P40 to P47 P50 to P57 Output 24-bit address bus for external memory PA0 to PA7 A8 to A15 PB0 to PB7 A16 to A23 P60 to P67 LWR Output External data bus lower byte write enable signal output P90/LCAS UWR Output External data bus upper byte write enable signal output P91/UCAS RD Output External data bus read strobe signal output P92 WE Output Write enable signal output for DRAM P93 OE Output Output enable signal output for DRAM P95 Data Sheet U13844EJ3V0DS 11 µPD70F3102-33 (3/4) Pin Name I/O Function Alternate Function LCAS Output Column address strobe signal output for lower data of DRAM P90/LWR UCAS Output Column address strobe signal output for higher data of DRAM P91/UWR RAS0 to RAS3 Output Row address strobe signal output for DRAM P80/CS0 to P83/CS3 RAS4 P84/CS4/IOWR RAS5 P85/CS5/IORD RAS6 P86/CS6 RAS7 P87/CS7 BCYST Output Strobe signal output indicating start of bus cycle P94 CS0 to CS3 Output Chip select signal output P80/RAS0 to P83/RAS3 CS4 P84/RAS4/IOWR CS5 P85/RAS5/IORD CS6 P86/RAS6 CS7 P87/RAS7 WAIT Input Control signal input that inserts a wait in the bus cycle PX6 REFRQ Output Refresh request signal output for DRAM PX5 IOWR Output DMA write strobe signal output P84/RAS4/CS4 IORD Output DMA read strobe signal output P85/RAS5/CS5 DMA request signal input P04/INTP100 to P07/INTP103 DMARQ0 to DMARQ3 Input DMAAK0 to DMAAK3 Output DMA acknowledge signal output P14/INTP110 to P17/INTP113 TC0 to TC3 Output DMA termination (terminal count) signal output P104/INTP120 to P107/INTP123 HLDAK Output Bus hold acknowledge output P96 HLDRQ Input Bus hold request input P97 ANI0 to ANI7 Input Analog input to A/D converter P70 to P77 NMI Input Non-maskable interrupt request input P20 System clock output PX7 CLKOUT Output CKSEL Input Input that specifies the clock generator's operation mode − MODE0 to MODE2 Input Operation mode specification − MODE3 VPP RESET Input System reset input − X1 Input − X2 − Connecting system clock resonator. In the case of an external clock, it is input to X1. − ADTRG Input A/D converter external trigger input AVREF Input Reference voltage applied to A/D converter − AVDD − Positive power supply for A/D converter − 12 Data Sheet U13844EJ3V0DS P127/INTP153 µPD70F3102-33 (4/4) Pin Name I/O Function Alternate Function AVSS − Ground potential for A/D converter − CVDD − Positive power supply for the dedicated clock generator − CVSS − Ground potential for dedicated clock generator − VDD − Positive power supply (internal unit power supply) − HVDD − Positive power supply (external pin power supply) − VSS − Ground potential − VPP − High-voltage application pin during program write/verify Data Sheet U13844EJ3V0DS MODE3 13 µPD70F3102-33 2.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin and the recommended connection of unused pins, and Figure 2-1 shows the schematic circuit diagram for each I/O circuit type. In the case of connection to VDD or VSS via a resistor, connection of a resistor of 1 to 10 kΩ is recommended. Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2) Pin I/O Circuit Type P00/TO100, P01/TO101 5 P02/TCLR10, P03/TI10 5-K Recommended Connection of Unused Pins Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3 P10/TO110, P11/TO111 5 P12/TCLR11, P13/TI11 5-K P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3 P20/NMI 2 Connect directly to VSS. P21 5 Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. P22/TXD0/SO0 P23/RXD0/SI0 5-K P24/SCK0 P25/TXD1/SO1 5 P26/RXD1/SI1 5-K P27/SCK1 P30/TO130, P31/TO131 5 P32/TCLR13, P33/TI13 5-K P34/INTP130 P35/INTP131/SO2 P36/INTP132/SI2 P37/INTP133/SCK2 P40/D0 to P47/D7 5 P50/D8 to P57/D15 P60/A16 to P67/A23 P70/ANI0 to P77/ANI7 14 9 Connect directly to VSS. Data Sheet U13844EJ3V0DS µPD70F3102-33 Table 2-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2) Pin I/O Circuit Type P80/CS0/RAS0 to P83/CS3/RAS3 5 Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. P100/TO120, P101/TO121 5 P102/TCLR12, P103/TI12 5-K Input: Independently connect to HVDD or VSS via a resistor. Output: Leave open. P84/CS4/RAS4/IOWR, P85/CS5/RAS5/IORD Recommended Connection of Unused Pins P86/CS6/RAS6, P87/CS7/RAS7 P90/LCAS/LWR P91/UCAS/UWR P92/RD P93/WE P94/BCYST P95/OE P96/HLDAK P97/HLDRQ P104/INTP120/TC0 to P107/INTP123/TC3 P110/TO140, P111/TO141 5 P112/TCLR14, P113/TI14 5-K P114/INTP140 P115/INTP141/SO3 P116/INTP142/SI3 P117/INTP143/SCK3 P120/TO150, P121/TO151 5 P122/TCLR15, P123/TI15 5-K P124/INTP150 to P126/INTP152 P127/INTP153/ADTRG PA0/A0 to PA7/A7 5 PB0/A8 to PB7/A15 PX5/REFRQ PX6/WAIT PX7/CLKOUT CKSEL 1 RESET 2 − MODE0 to MODE2 MODE3/VPP Connect to VSS via a resistor (RVPP). AVREF, AVSS − Connect directly to VSS. AVDD − Connect directly to HVDD. Data Sheet U13844EJ3V0DS 15 µPD70F3102-33 Figure 2-1. Pin I/O Circuits Type 5-K Type 1 VDD VDD Data P-ch IN/OUT P-ch IN Output disable N-ch N-ch Input enable Type 9 Type 2 P-ch IN N-ch IN + – Comparator VREF (threshold voltage) Input enable Schmitt-triggered input with hysteresis characteristics Type 5 VDD Data P-ch IN/OUT Output disable N-ch Input enable Caution Replace VDD in the circuit diagrams with HVDD. 16 Data Sheet U13844EJ3V0DS µPD70F3102-33 3. FLASH MEMORY PROGRAMMING The following two flash memory programming methods are available. (1) On-board programming The program is written to the flash memory using a dedicated flash programmer after the µPD70F3102-33 is mounted on the target board. Install the connectors, etc. required for communication with the dedicated flash programmer on the target board. (2) Off-board programming The program is written to the flash memory using a dedicated adapter before the µPD70F3102-33 is mounted on the target board. 3.1 Selection of Communication Mode Writing to the flash memory is done via serial communication using the dedicated flash programmer. Select one of the communication modes listed in Table 3-1. Base your selection of the communication mode on the selection format shown in Table 3-1. Refer to the number of VPP pulses shown in Table 3-1 when selecting the communication mode. Table 3-1. Communication Modes Communication Mode Pins Used Number of VPP Pulses CSI0 SO0 (serial data output) SI0 (serial data input) SCK0 (serial clock input) 0 UART0 TXD0 (serial data output) RXD0 (serial data input) 8 Figure 3-1. Communication Mode Selection Format 7.8 V VPP VDD VSS VDD RESET VSS Data Sheet U13844EJ3V0DS 17 µPD70F3102-33 3.2 Flash Memory Programming Functions Flash memory programming is performed by sending and receiving commands and data according to the selected communication mode. Table 3-2 shows the main flash memory programming functions. Table 3-2. Main Flash Memory Programming Functions Function Description Batch erasure Erases the contents of the entire memory. Batch blank check Checks whether the entire memory has been erased. Data write Writes data to flash memory based on the write start address and the number of bytes to be written. Batch verify Compares the contents of the entire memory with the input data. 3.3 Connecting the Dedicated Flash Programmer The connection of the dedicated flash programmer to the µPD70F3102-33 differs depending on the communication mode. Figures 3-2 and 3-3 show the various connection types. Figure 3-2. Connection of Dedicated Flash Programmer for CSI0 Mode Dedicated flash programmer CLK µ PD70F3102-33 CLK VPP VPP VDD VDD RESET RESET SCK SCK0 SO SI0 SI SO0 VSS VSS Figure 3-3. Connection of Dedicated Flash Programmer for UART0 Mode Dedicated flash programmer CLK VPP VPP VDD VDD RESET RESET TxD RXD0 RxD TXD0 VSS 18 µ PD70F3102-33 CLK VSS Data Sheet U13844EJ3V0DS µPD70F3102-33 4. ELECTRICAL SPECIFICATIONS 4.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Ratings Unit VDD pin −0.5 to +4.6 V HVDD HVDD pin, HVDD ≥ VDD −0.5 to +7.0 V CVDD CVDD pin −0.5 to +4.6 V CVSS CVSS pin −0.5 to +0.5 VDD Input voltage Conditions AVDD AVDD pin AVSS AVSS pin VI V Note −0.5 to HVDD + 0.5 −0.5 to +0.5 Except X1 pin, MODE3/VPP pin V Note −0.5 to HVDD + 0.5 Note MODE3/VPP pin MODE3/VPP pin in flash memory programming mode V V −0.5 to VDD + 0.5 V −0.5 to +11.0 V −0.5 to VDD + 1.0Note V Clock input voltage VK X1, VDD = 3.0 to 3.6 V Output current, low IOL 1 pin 4.0 mA Total of all pins 100 mA 1 pin −4.0 mA Total of all pins −100 mA Output current, high Output voltage IOH VO Analog input voltage A/D converter reference input voltage VIAN AVREF HVDD = 5.0 V ±10% P70/ANI0 to P77/ANI7 pins AVDD > HVDD HVDD ≥ AVDD AVDD > HVDD HVDD ≥ AVDD −0.5 to HVDD + 0.5Note V Note V Note V Note V Note V −0.5 to HVDD + 0.5 −0.5 to AVDD + 0.5 −0.5 to HVDD + 0.5 −0.5 to AVDD + 0.5 Operating ambient temperature TA −40 to +85 °C Storage temperature Tstg −65 to +125 °C Note Use the product under conditions that ensure the absolute maximum ratings (MAX. values) of respective supply voltages are not exceeded. Cautions 1. Do not directly connect the output pins (or I/O pins) of IC products to each other, to VDD, VCC, and GND. Open-drain pins and open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to a high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Data Sheet U13844EJ3V0DS 19 µPD70F3102-33 Capacitance (TA = 25°C, VDD = HVDD = CVDD = VSS = 0 V) Parameter Symbol Conditions Input capacitance CI I/O capacitance CIO fc = 1 MHz Unmeasured pins returned to 0 V Output capacitance CO MIN. TYP. MAX. Unit 15 pF 15 pF 15 pF Operating Conditions Operation Mode Direct mode PLL modeNote Internal Operation Clock Frequency (fX) Operating Ambient Temperature (TA) Supply Voltage (VDD, HVDD) 2 to 33 MHz −40 to +85°C VDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10% 20 to 33 MHzNote 2 −40 to +85°C VDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10% 1 Notes 1. The internal operation clock frequency in PLL mode is the value during operation with a ×5 clock. When using a ×1 or ×1/2 clock by setting the CKDIVn (n = 0, 1) bit in the CKC register, operation is possible at a frequency of 20 MHz or lower. 2. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz. 20 Data Sheet U13844EJ3V0DS µPD70F3102-33 Recommended Oscillator (a) Connection of ceramic resonator (TA = −40 to +85°C) (i) Murata Mfg. Co., Ltd. (TA = −40 to +85°C) X1 X2 Rd C2 C1 Type Surface mount Lead Product Name Oscillation Frequency fXX (MHz) C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) MAX. (V) Oscillation Stabilization Time (MAX.) TOST (ms) Recommended Circuit Constant Oscillation Voltage Range CSAC4.00MGC040 4.0 100 100 0 3.0 3.6 0.5 CSTCC4.00MG0H6 4.0 On-chip On-chip 0 3.0 3.6 0.3 CSAC5.00MGC040 5.0 100 100 0 3.0 3.6 0.4 CSTCC5.00MG0H6 5.0 On-chip On-chip 0 3.0 3.6 0.2 CSAC6.60MT 6.6 30 30 0 3.0 3.6 0.2 CSTCC6.60MG0H6 6.6 On-chip On-chip 0 3.0 3.6 0.1 CSAC8.00MT 8.0 30 30 0 3.0 3.6 0.2 CSTCC8.00MG0H6 8.0 On-chip On-chip 0 3.0 3.6 0.3 CSA4.00MG040 4.0 100 100 0 3.0 3.6 0.5 CST4.00MGW040 4.0 On-chip On-chip 0 3.0 3.6 0.5 CSA5.00MG040 5.0 100 100 0 3.0 3.6 0.5 CST5.00MGW040 5.0 On-chip On-chip 0 3.0 3.6 0.5 CSA6.60MTZ 6.6 30 30 0 3.0 3.6 0.1 CST6.60MTW 6.6 On-chip On-chip 0 3.0 3.6 0.1 CSA8.00MTZ 8.0 30 30 0 3.0 3.6 0.1 CST8.00MTW 8.0 On-chip On-chip 0 3.0 3.6 0.1 Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator. Data Sheet U13844EJ3V0DS 21 µPD70F3102-33 (ii) TDK Corporation (TA = −40 to +85°C) X1 X2 Rd C1 Manufacturer TDK Product Name Oscillation Frequency fXX (MHz) C2 Recommended Circuit Constant Oscillation Stabilization Time (MAX.) TOST (ms) MAX. (V) Oscillation Voltage Range C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) CCR4.0MC3 4.0 On-chip On-chip 0 3.0 3.6 0.17 CCR5.0MC3 5.0 On-chip On-chip 0 3.0 3.6 0.15 CCR8.0MC5 8.0 On-chip On-chip 0 3.0 3.6 0.11 Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator. (iii) Kyocera Corporation (TA = −20 to +80°C) X1 X2 Rd C1 Manufacturer Kyocera Product Name Oscillation Frequency fXX (MHz) C2 Recommended Circuit Constant Oscillation Stabilization Time (MAX.) TOST (ms) MAX. (V) Oscillation Voltage Range C1 (pF) C2 (pF) Rd (kΩ) MIN. (V) PBRC5.00BR-A 5.0 On-chip On-chip 0 3.0 3.6 0.06 PBRC6.00BR-A 6.0 On-chip On-chip 0 3.0 3.6 0.06 PBRC6.60BR-A 6.6 On-chip On-chip 0 3.0 3.6 0.06 Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. Thoroughly evaluate the matching between the µPD70F3102-33 and the resonator. 22 Data Sheet U13844EJ3V0DS µPD70F3102-33 (b) External clock input (TA = −40 to +85°C) X1 X2 Open External clock Caution Input a CMOS level voltage to the X1 pin. Cautions when turning on/off the power The µPD70F3102-33 is configured with power supply pins for the internal unit (VDD) and for the external pins (HVDD). The operation guaranteed range is VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%. The input and output state of ports may be undefined when the voltage exceeds this range. Data Sheet U13844EJ3V0DS 23 µPD70F3102-33 DC Characteristics (TA = −40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%, VSS = 0 V) (1/2) Parameter Input voltage, high Symbol Conditions MAX. Unit 2.2 HVDD + 0.3 V 0.8HVDD HVDD + 0.3 V Except Notes 1 and 2 −0.5 +0.8 V Note 1 −0.5 0.2HVDD V Direct mode 0.8VDD VDD + 0.3 V PLL mode 0.8VDD VDD + 0.3 V Direct mode −0.3 0.15VDD V PLL mode −0.3 0.15VDD V Except Note 1 VIH Note 1 Input voltage, low Clock input voltage, high Clock input voltage, low Schmitt-triggered input threshold voltage Schmitt-triggered input hysteresis width Output voltage, high VIL VXH VXL HVT X1 pin X1 pin MIN. TYP. + Note 1, rising edge 3.0 V − Note 1, falling edge 2.0 V + Note 1 HVT HVT −HVT− VOH 0.5 V IOH = −2.5 mA 0.7HVDD V IOH = −100 µA HVDD − 0.4 V Output voltage, low VOL IOL = 2.5 mA 0.45 V Input leakage current, high ILIH VI = HVDD, except Note 2 10 µA Input leakage current, low ILIL VI = 0 V, except Note 2 −10 µA Output leakage current, high ILOH VO = HVDD 10 µA Output leakage current, low ILOL VO = 0 V −10 µA Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET 2. When using the P70/AN10 to P77/ANI7 pins as analog inputs. Remark TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, HVDD = 5.0 V. 24 Data Sheet U13844EJ3V0DS µPD70F3102-33 DC Characteristics (TA = −40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%, VSS = 0 V) (2/2) Parameter Supply current During normal During HALT During IDLE During STOP Symbol IDD1 IDD2 IDD3 IDD4 Conditions TYP. MAX. Unit VDD + CVDD 2.0 × fX 4.5 × fX mA HVDD 1.8 × fX 3.0 × fX mA VDD + CVDD 1.4 × fX 3.0 × fX mA HVDD 0.8 × fX 1.5 × fX mA VDD + CVDD 3.0 10 mA HVDD 0.5 1.0 mA 20 50 µA 600 µA 20 µA VDD + CVDD −40°C ≤ TA ≤ +40°C MIN. +40°C < TA ≤ +85°C HVDD 10 Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, HVDD = 5.0 V. 2. Direct mode: fX = 2 to 33 MHz PLL mode: fX = 20 to 33 MHz 3. The fX unit is MHz. Data Sheet U13844EJ3V0DS 25 µPD70F3102-33 Data Retention Characteristics (TA = −40 to +85°C) Parameter Symbol Data retention voltage Conditions VDDDR STOP mode, VDD = VDDDR STOP mode, HVDD = HVDDDR HVDDDR Data retention current MIN. IDDDR VDD = VDDDR MAX. Unit 1.5 3.6 V VDDDR 5.5 V 50 µA 600 µA −40°C ≤ TA ≤ +40°C TYP. 20 +40°C < TA ≤ +85°C Supply voltage rise time tRVD 200 µs Supply voltage fall time tFVD 200 µs Supply voltage hold time (from STOP mode setting) tHVD 0 ms STOP release signal input time tDREL 0 ns Data retention high-level input voltage VIHDR Note 0.8HVDDDR HVDDDR V Data retention low-level input voltage VILDR Note 0 0.2HVDDDR V Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET Remark TYP. values are reference values for when TA = 25°C. STOP mode setting VDDDR VDD tFVD tRVD tHVD tDREL HVDD RESET (input) NMI (input) (released by falling edge) VIHDR VIHDR NMI (input) (released by rising edge) VILDR 26 Data Sheet U13844EJ3V0DS µPD70F3102-33 AC Characteristics (TA = −40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%, VSS = 0 V, Output Pin Load Capacitance: CL = 50 pF) AC Test Input Measurement Points (a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/INTP130, P35/INTP131/SO2, P107/INTP123/TC3, P36/INTP132/SI2, P114/INTP140, P37/INTP133/SCK2, P115/INTP141/SO3, P104/INTP120/TC0 P116/INTP142/SI3, to P117/INTP143/SCK3, P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET HVDD 0.8HVDD Input signal 0V Measurement points 0.2HVDD 0.8HVDD 0.2HVDD (b) Other than (a) 2.4 V 2.2 V Input signal 0.4 V Measurement points 2.2 V 0.8 V 0.8 V AC Test Output Measurement Points 2.4 V Output signal Measurement points 0.8 V 2.4 V 0.8 V Load Conditions DUT (Device under test) CL = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means. Data Sheet U13844EJ3V0DS 27 µPD70F3102-33 (1) Clock timing Parameter Symbol X1 input cycle <1> X1 input high-level width <2> X1 input low-level width <3> X1 input rise time <4> X1 input fall time <5> Conditions tCYX tWXH tWXL tXR tXF MIN. MAX. Unit In direct mode 15 250 ns In PLL mode 150 250 ns In direct mode 5 ns In PLL mode 50 ns In direct mode 5 ns In PLL mode 50 ns In direct mode 4 ns In PLL mode 10 ns In direct mode 4 ns In PLL mode 10 ns 100 ns CLKOUT output cycle <6> tCYK 30 CLKOUT high-level width <7> tWKH 0.5T − 7 ns CLKOUT low-level width <8> tWKL 0.5T − 4 ns CLKOUT rise time <9> tKR 5 ns CLKOUT fall time <10> tKF 5 ns Remark T = tCYK <1> <2> <3> <4> <5> X1 (PLL mode) <1> <2> <3> <4> X1 (Direct mode) <5> CLKOUT (Output) <9> <10> <7> <8> <6> 28 Data Sheet U13844EJ3V0DS µPD70F3102-33 (2) Output waveform (other than X1, CLKOUT) Parameter Symbol Conditions MIN. MAX. Unit Output rise time <12> tOR 10 ns Output fall time <13> tOF 10 ns <12> <13> Signals other than X1, CLKOUT (3) Reset timing Parameter Symbol Conditions RESET pin high-level width <14> tWRSH RESET pin low-level width <15> tWRSL MIN. MAX. Unit 500 ns At power ON, STOP mode release 500 + TOS ns Except at power ON, STOP mode release 500 ns Remark TOS: Oscillation stabilization time <14> <15> RESET (Input) Data Sheet U13844EJ3V0DS 29 µPD70F3102-33 (4) SRAM, external ROM, external I/O access timing (a) Access timing (SRAM, external ROM, external I/O) (1/2) Parameter Symbol Conditions MIN. MAX. Unit Address, CSn output delay time (from CLKOUT↓) <16> tDKA 2 10 ns Address, CSn output hold time (from CLKOUT↓) <17> tHKA 2 10 ns RD, IORD↓ delay time (from CLKOUT↑) <18> tDKRDL 2 14 ns RD, IORD↑ delay time (from CLKOUT↑) <19> tHKRDH 2 14 ns UWR, LWR, IOWR↓ delay time (from CLKOUT↑) <20> tDKWRL 2 10 ns UWR, LWR, IOWR↑ delay time (from CLKOUT↑) <21> tHKWRH 2 10 ns BCYST↓ delay time (from CLKOUT↓) <22> tDKBSL 2 10 ns BCYST↑ delay time (from CLKOUT↓) <23> tHKBSH 2 10 ns WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns Data input setup time (to CLKOUT↑) <26> tSKID 18 ns Data input hold time (from CLKOUT↑) <27> tHKID 2 ns Data output delay time (from CLKOUT↓) <28> tDKOD 2 10 ns Data output hold time (from CLKOUT↓) <29> tHKOD 2 10 ns Remarks 1. Observe at least one of the data input hold times, tHKID or tHRDID. 2. n = 0 to 7 30 Data Sheet U13844EJ3V0DS µPD70F3102-33 (a) Access timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) <16> <17> A0 to A23 (Output) CSn (Output) <22> <23> BCYST (Output) <18> <19> <20> <21> RD, IORD (Output) [Read time] UWR, LWR, IOWR (Output) [Write time] <26> <27> D0 to 15 (I/O) [Read time] <28> <29> D0 to 15 (I/O) [Write time] <25> <24> <25> <24> WAIT (Input) Remarks 1. Timing when number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 31 µPD70F3102-33 (b) Read timing (SRAM, external ROM, external I/O) (1/2) Parameter Symbol Conditions MIN. MAX. Unit Data input setup time (to address) <30> tSAID (1.5 + wD + w) T − 28 ns Data input setup time (to RD) <31> tSRDID (1 + wD +w) T − 32 ns RD, IORD low-level width <32> tWRDL (1 + wD + w) T − 10 ns RD, IORD high-level width <33> tWRDH T − 10 ns Delay time from address, CSn to RD, IORD↓ <34> tDARD 0.5T − 10 ns Delay time from RD, IORD↑ to address <35> tDRDA (0.5 + i) T − 10 ns Data input hold time <36> tHRDID 0 ns Delay time from RD, IORD↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns WAIT setup time (to address) <38> tSAW Note T − 25 ns WAIT setup time (to BCYST↓) <39> tSBSW Note T − 25 ns WAIT hold time (from BCYST↑) <40> tHBSW Note (from RD, IORD↑) 0 ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1, DWC2 4. i: Number of idle states inserted when a write cycle follows the read cycle. 5. Observe at least one of the data input hold times, tHKID or tHRDID. 6. n = 0 to 7 32 Data Sheet U13844EJ3V0DS µPD70F3102-33 (b) Read timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) UWR, LWR, IOWR (Output) <33> <32> <35> RD, IORD (Output) <34> <31> <30> <37> <36> D0 to D15 (I/O) <38> WAIT (Input) <39> <40> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 33 µPD70F3102-33 (c) Write timing (SRAM, external ROM, external I/O) (1/2) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to address) <38> tSAW Note T − 25 ns WAIT setup time (to BCYST↓) <39> tSBSW Note T − 25 ns WAIT hold time (from BCYST↑) <40> tHBSW Note Delay time from address, CSn to UWR, LWR, IOWR↓ <41> Address setup time (to UWR, LWR, IOWR↑) 0 ns tDAWR 0.5T − 10 ns <42> tSAWR (1.5 + wD + w) T − 10 ns Delay time from UWR, LWR, IOWR↑ to address <43> tDWRA 0.5T − 10 ns UWR, LWR, IOWR high-level width <44> tWWRH T − 10 ns UWR, LWR, IOWR low-level width <45> tWWRL (1 + wD + w) T − 10 ns Data output setup time (to UWR, LWR, IOWR↑) <46> tSODWR (1.5 + wD + w) T − 10 ns Data output hold time (from UWR, LWR, IOWR↑) <47> tHWROD 0.5T − 10 ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2 4. n = 0 to 7 34 Data Sheet U13844EJ3V0DS µPD70F3102-33 (c) Write timing (SRAM, external ROM, external I/O) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) RD, IORD (Output) <41> <42> <45> <43> <44> UWR, LWR, IOWR (Output) <46> <47> D0 to D15 (I/O) <38> WAIT (Input) <39> <40> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 35 µPD70F3102-33 (d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns RD low-level width <32> tWRDL (1 + wD + wF + w) T − 10 ns RD high-level width <33> tWRDH T − 10 ns Delay time from address, CSn to RD↓ <34> tDARD 0.5T − 10 ns Delay time from RD↑ to address <35> tDRDA (0.5 + i) T − 10 ns Delay time from RD↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns WAIT setup time (to address) <38> tSAW Note T − 25 ns WAIT setup time (to BCYST↓) <39> tSBSW Note T − 25 ns WAIT hold time (from BCYST↑) <40> tHBSW Note Delay time from address to IOWR↓ <41> Address setup time (to IOWR↑) 0 ns tDAWR 0.5T − 10 ns <42> tSAWR (1.5 + wD + w) T − 10 ns Delay time from IOWR↑ to address <43> tDWRA 0.5T − 10 ns IOWR high-level width <44> tWWRH T − 10 ns IOWR low-level width <45> tWWRL (1 + wD + w) T − 10 ns Delay time from IOWR↑ to RD↑ <48> tDWRRD wF = 0 0 ns wF = 1 T − 10 ns Delay time from DMAAKm↓ to IOWR↓ <49> tDDAWR 0.5T − 10 ns Delay time from IOWR↑ to DMAAKm↑ <50> tDWRDA (0.5 + wF) T − 10 ns Note During the first WAIT sampling, when number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1, DWC2 4. wF: Number of waits inserted to source-side access during DMA flyby transfer 5. i: Number of idle states inserted when a write cycle follows the read cycle 6. n = 0 to 7, m = 0 to 3 36 Data Sheet U13844EJ3V0DS µPD70F3102-33 (d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) <33> <32> <35> RD (Output) <34> <48> UWR, LWR (Output) DMAAKm (Output) <49> <50> IORD (Output) <42> <41> <43> <45> <44> IOWR (Output) <37> D0 to D15 (I/O) <38> <24> <25> <25> <24> WAIT (Input) <40> <39> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Data Sheet U13844EJ3V0DS 37 µPD70F3102-33 (e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns IORD low-level width <32> tWRDL (1 + wD + wF + w) T − 10 ns IORD high-level width <33> tWRDH T − 10 ns Delay time from address, CSn to IORD↓ <34> tDARD 0.5T − 10 ns Delay time from IORD↑ to address <35> tDRDA (0.5 + i) T − 10 ns Delay time from IORD↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns WAIT setup time (to address) <38> tSAW Note T − 25 ns WAIT setup time (to BCYST↓) <39> tSBSW Note T − 25 ns WAIT hold time (from BCYST↑) <40> tHBSW Note Delay time from address to UWR, LWR↓ <41> Address setup time (to UWR, LWR↑) 0 ns tDAWR 0.5T − 10 ns <42> tSAWR (1.5 + wD + w) T − 10 ns Delay time from UWR, LWR↑ to address <43> tDWRA 0.5T − 10 ns UWR, LWR high-level width <44> tWWRH T − 10 ns UWR, LWR low-level width <45> tWWRL (1 + wD + w) T − 10 ns Delay time from UWR, LWR↑ to IORD↑ <48> tDWRRD wF = 0 0 ns wF = 1 T − 10 ns Delay time from DMAAKm↓ to IORD↓ <51> tDDARD 0.5T − 10 ns Delay time from IORD↑ to DMAAKm↑ <52> tDRDDA 0.5T − 10 ns Note During the first WAIT sampling, when the number of waits specified by registers DWC1 and DWC2 is 0. Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2. 4. wF: Number of waits inserted to source-side access during DMA flyby transfer. 5. i: Number of idle states inserted when a write cycle follows the read cycle. 6. n = 0 to 7, m = 0 to 3 38 Data Sheet U13844EJ3V0DS µPD70F3102-33 (e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2) T1 TW T2 CLKOUT (Output) A0 to A23 (Output) CSn (Output) <41> <42> <45> <43> <44> UWR, LWR (Output) <48> RD (Output) <51> <52> DMAAKm (Output) IOWR (Output) <34> <33> <32> <35> IORD (Output) <37> D0 to D15 (I/O) <38> <24> <25> <25> <24> WAIT (Input) <40> <39> BCYST (Output) Remarks 1. Timing when the number of waits specified by registers DWC1 and DWC2 is 0 and wF = 0. 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Data Sheet U13844EJ3V0DS 39 µPD70F3102-33 (5) Page ROM access timing (1/2) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns Data input setup time (to CLKOUT↑) <26> tSKID 18 ns Data input hold time (from CLKOUT↑) <27> tHKID 2 ns Off-page data input setup time (to address) <30> tSAID (1.5 + wD +w) T − 28 ns Off-page data input setup time (to RD) <31> tSRDID (1 + wD + w) T − 32 ns Off-page RD low-level width <32> tWRDL (1 + wD + w) T − 10 ns RD high-level width <33> tWRDH 0.5T − 10 ns Data input hold time (from RD) <36> tHRDID 0 ns Delay time from RD↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns On-page RD low-level width <53> tWORDL (1.5 + wPR + w) T − 10 ns On-page data input setup time (to address) <54> tSOAID (1.5 + wPR + w) T − 28 ns On-page data input setup time (to RD) <55> tSORDID (1.5 + wPR + w) T − 32 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wD: Number of waits specified by registers DWC1 and DWC2. 4. wPR: Number of waits specified by register PRC. 5. i: Number of idle states inserted when a write cycle follows the read cycle. 6. Observe at least one of the data input hold times, tHKID or tHRDID. 40 Data Sheet U13844EJ3V0DS µPD70F3102-33 (5) Page ROM access timing (2/2) T1 TDW TW T2 TO1 TPRW TW TO2 CLKOUT (Output) Off-page addressNote CSn (Output) On-page addressNote <26> <30> <54> UWR, LWR (Output) <33> <32> <53> <55> <31> <37> RD (Output) <36> <36> <26> <27> <27> D0 to D15 (I/O) <25> <25> <24> <25> <24> <24> <25> <24> WAIT (Input) BCYST (Output) Note On-page addresses and off-page addresses are as follows. PRC Register On-Page Addresses Off-Page Addresses MA5 MA4 MA3 0 0 0 A0, A1 A2 to A23 0 0 1 A0 to A2 A3 to A23 0 1 1 A0 to A3 A4 to A23 1 1 1 A0 to A4 A5 to A23 Remarks 1. These timings are for the following cases: Number of waits (TDW) specified by registers DWC1 and DWC2: 1 Number of waits (TPRW) specified by register PRC: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 41 µPD70F3102-33 (6) DRAM access timing (a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns Data input setup time (to CLKOUT↑) <26> tSKID 18 ns Data input hold time (from CLKOUT↑) <27> tHKID 2 ns Delay time from OE↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T − 10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (1.5 + wDA + w) T − 10 ns Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + w) T − 10 ns RAS recharge time <61> tRP (0.5 + wRP) T − 10 ns RAS pulse time <62> tRAS (2.5 + wRH + wDA + w) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA + w) T − 10 ns Column address read time for RAS <64> tRAL (2 + wDA + w) T − 10 ns CAS pulse width <65> tCAS (1 + wDA + w) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRP) T − 10 ns CAS hold time <67> tCSH (2 + wRH + wDA + w) T − 10 ns WE setup time <68> tRCS (2 + wRP + wRH) T − 10 ns WE hold time (from RAS↑) <69> tRRH 0.5T − 10 ns WE hold time (from CAS↑) <70> tRCH T − 10 ns CAS precharge time <71> tCPN (2 + wRP + wRH) T − 10 ns Output enable access time <72> tOEA (2 + wRP + wRH + wDA + w) T − 28 ns RAS access time <73> tRAC (2 + wRH + wDA + w) T − 28 ns Access time from column address <74> tAA (1.5 + wDA + w) T − 28 ns CAS access time <75> tCAC (1 + wDA + w) T − 28 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: Number of idle states inserted when a write cycle follows the read cycle. 42 Data Sheet U13844EJ3V0DS µPD70F3102-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3) Parameter Symbol Conditions MIN. MAX. Unit RAS column address delay time <76> tRAD (0.5 + wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH) T − 10 ns Output buffer turn off delay time (from OE↑) <78> tOEZ 0 ns Output buffer turn off delay time (from CAS↑) <79> tOFF 0 ns Remarks 1. T = tCYK 2. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) Data Sheet U13844EJ3V0DS 43 µPD70F3102-33 (a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3) TRPW T1 TRHW T2 TDAW TW T3 CLKOUT (Output) <58> <56> <57> <59> Row address A0 to A23 (Output) Column address <63> <64> <76> <61> <62> RASn (Output) <60> <77> <65> <66> <67> UCAS (Output) LCAS (Output) <69> <71> <73> <68> <75> <70> WE (Output) <79> <74> <27> <72> <37> OE (Output) <78> <26> D0 to D15 (I/O) <24> <25> <25> <24> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 44 Data Sheet U13844EJ3V0DS µPD70F3102-33 [MEMO] Data Sheet U13844EJ3V0DS 45 µPD70F3102-33 (b) Read timing (high-speed DRAM access: on-page) (1/2) Parameter Symbol Conditions MIN. MAX. Unit Data input setup time (to CLKOUT↑) <26> tSKID 18 ns Data input hold time (from CLKOUT↑) <27> tHKID 2 ns Delay time from OE↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns Column address setup time <58> tASC (0.5 + wCP) T − 10 ns Column address hold time <59> tCAH (1.5 + wDA) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA) T − 10 ns Column address read time for RAS <64> tRAL (2 + wCP + wDA) T − 10 ns CAS pulse width <65> tCAS (1 + wDA) T − 10 ns WE setup time (to CAS↓) <68> tRCS (1 + wCP) T − 10 ns WE hold time (from RAS↑) <69> tRRH 0.5 T − 10 ns WE hold time (from CAS↑) <70> tRCH T − 10 ns Output enable access time <72> tOEA (1 + wCP + wDA) T − 28 ns Access time from column address <74> tAA (1.5 + wCP + wDA) T − 28 ns CAS access time <75> tCAC (1 + wDA) T − 28 ns Output buffer turn-off delay time (from OE↑) <78> tOEZ 0 ns Output buffer turn-off delay time (from CAS↑) <79> tOFF 0 ns Access time from CAS precharge <80> tACP CAS precharge time <81> tCP (1 + wCP) T − 10 ns High-speed page mode cycle time <82> tPC (2 + wCP + wDA) T − 10 ns RAS hold time from CAS precharge <83> tRHCP (2.5 + wCP + wDA) T − 10 ns (2 + wCP + wDA) T − 28 Remarks 1. T = tCYK 2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. i: Number of idle states inserted when a write cycle follows the read cycle. 46 Data Sheet U13844EJ3V0DS ns µPD70F3102-33 (b) Read timing (high-speed DRAM access: on-page) (2/2) TCPW TO1 TDAW TO2 CLKOUT (Output) <58> <59> A0 to A23 (Output) Column address <63> <64> RASn (Output) <83> <81> <65> <82> UCAS (Output) LCAS (Output) <69> <68> <70> WE (Output) <75> <72> <79> <26> <37> OE (Output) <74> <80> <78> <27> D0 to D15 (I/O) WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 47 µPD70F3102-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T − 10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (1.5 + wDA + w) T − 10 ns Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + w) T − 10 ns RAS precharge time <61> tRP (0.5 + wRP) T − 10 ns RAS pulse time <62> tRAS (2.5 + wRH + wDA + w) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA + w) T − 10 ns Column address read time (from RAS↑) <64> tRAL (2 + wDA + w) T − 10 ns CAS pulse width <65> tCAS (1 + wDA + w) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRH) T − 10 ns CAS hold time <67> tCSH (2 + wRH + wDA + w) T − 10 ns CAS precharge time <71> tCPN (2 + wRP + wRH) T − 10 ns RAS column address delay time <76> tRAD (0.5+ wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH) T − 10 ns WE setup time (to CAS↓) <84> tWCS (1 + wRP + wRH) T − 10 ns WE hold time (from CAS↓) <85> tWCH (1 + wDA + w) T − 10 ns Data setup time (to CAS↓) <86> tDS (1.5 + wRP + wRH) T − 10 ns Data hold time (from CAS↓) <87> tDH (1.5 + wDA + w) T − 10 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 48 Data Sheet U13844EJ3V0DS µPD70F3102-33 (c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2) TRPW T1 TRHW T2 TDAW TW T3 CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59> Row address Column address <63> <64> <76> <61> <62> RASn (Output) <60> <77> <66> <65> <67> UCAS (Output) LCAS (Output) <71> OE (Output) <84> <85> WE (Output) <86> <87> D0 to D15 (I/O) <24> <25> <25> <24> WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 49 µPD70F3102-33 (d) Write timing (high-speed page DRAM access: on-page) (1/2) Parameter Symbol Conditions MIN. MAX. Unit Column address setup time <58> tASC (0.5 + wCP) T − 10 ns Column address hold time <59> tCAH (1.5 + wDA) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA) T − 10 ns Column address read time (from RAS↑) <64> tRAL (2 + wCP + wDA) T − 10 ns CAS pulse width <65> tCAS (1 + wDA) T − 10 ns CAS precharge time <81> tCP (1 + wCP) T − 10 ns RAS hold time for CAS precharge <83> tRHCP (2.5 + wCP + wDA) T − 10 ns WE setup time (to CAS↓) <84> tWCS wCPT − 10 ns WE hold time (from CAS↓) <85> tWCH (1 + wDA) T − 10 ns Data setup time (to CAS↓) <86> tDS (0.5 + wCP) T − 10 ns Data hold time (from CAS↓) <87> tDH (1.5 + wDA) T − 10 ns WE read time (from RAS↑) <88> tRWL wCP = 0 (1.5 + wDA) T − 10 ns WE read time (from CAS↑) <89> tCWL wCP = 0 (1 + wDA) T − 10 ns Data setup time (to WE↓) <90> tDSWE wCP = 0 0.5T − 10 ns Data hold time (from WE↓) <91> tDHWE wCP = 0 (1.5 + wDA) T − 10 ns WE pulse width <92> tWP wCP = 0 (1 + wDA) T − 10 ns wCP ≥ 1 Remarks 1. T = tCYK 2. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 50 Data Sheet U13844EJ3V0DS µPD70F3102-33 (d) Write timing (high-speed page DRAM access: on-page) (2/2) TCPW TO1 TDAW TO2 CLKOUT (Output) <58> A0 to A23 (Output) <59> Column address <63> <64> RASn (Output) <83> <81> <65> UCAS (Output) LCAS (Output) <89> <88> OE (Output) <84> <85> <92> WE (Output) <91> <90> <86> <87> D0 to D15 (I/O) WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 51 µPD70F3102-33 (e) Read timing (EDO DRAM) (1/3) Parameter Symbol Conditions MIN. MAX. Unit Data input setup time (to CLKOUT↑) <26> tSKID 18 ns Data input hold time (from CLKOUT↑) <27> tHKID 2 ns Delay time from OE↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T − 10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (0.5 + wDA) T − 10 ns RAS precharge time <61> tRP (0.5 + wRP) T − 10 ns Column address read time (to RAS↑) <64> tRAL (2 + wCP + wDA) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRP) T − 10 ns CAS hold time <67> tCSH (1.5 + wRH + wDA) T − 10 ns WE setup time (to CAS↓) <68> tRCS (2 + wRP +wRH) T − 10 ns WE hold time (from RAS↑) <69> tRRH 0.5T − 10 ns WE hold time (from CAS↑) <70> tRCH 1.5T − 10 ns RAS access time <73> tRAC (2 + wRH + wDA) T − 28 ns Access time from column address <74> tAA (1.5 + wDA) T − 28 ns CAS access time <75> tCAC (1 + wDA) T − 28 ns Delay time from RAS to column address <76> tRAD (0.5 + wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH) T − 10 ns Output buffer turn-off delay time (from OE) <78> tOEZ 0 ns Access time from CAS precharge <80> tACP CAS precharge time <81> tCP (0.5 + wCP) T − 10 ns RAS hold time for CAS precharge <83> tRHCP (2 + wCP + wDA) T − 10 ns Read cycle time <93> tHPC (1 + wDA + wCP) T − 10 ns RAS pulse width <94> tRASP (2.5 + wRH + wDA) T − 10 ns CAS pulse width <95> tHCAS (0.5 + wDA) T − 10 ns Off-page <96> tOCH1 (2 + wRH + wDA) T − 10 ns On-page <97> tOCH2 (0.5 + wDA) T − 10 ns <98> tDHC 0 ns Hold time from OE to CAS Data input hold time (from CAS↓) (1.5 + wCP + wDA) T − 28 ns Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. i: Number of idle states inserted when a write cycle follows the read cycle. 52 Data Sheet U13844EJ3V0DS µPD70F3102-33 (e) Read timing (EDO DRAM) (2/3) Parameter Output enable access time Symbol Conditions MIN. MAX. Unit Off-page <99> tOEA1 (2 + wRP + wRH + wDA) T − 28 ns On-page <100> tOEA2 (1 + wCP + wDA) T − 28 ns Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) Data Sheet U13844EJ3V0DS 53 µPD70F3102-33 (e) Read timing (EDO DRAM) (3/3) TRPW T1 TRHW T2 TDAW TCPW TB TDAW TE CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> Row address <59> Column address Column address <64> <76> <74> <94> <61> RASn (Output) <67> <66> <83> <77> <95> <81> <75> UCAS (Output) LCAS (Output) <68> <93> <69> <95> <80> <70> WE (Output) <97> <96> <100> <26> Note OE (Output) <75> <74> <98> <27> <27> <78> <26> D0 to D15 (I/O) Data <73> <99> BCYST (Output) WAIT (Input) Note In case of on-page access from another cycle, while RASn is low level. Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 54 Data Sheet U13844EJ3V0DS Data <37> µPD70F3102-33 [MEMO] Data Sheet U13844EJ3V0DS 55 µPD70F3102-33 (f) Write timing (EDO DRAM) (1/2) Parameter Symbol Conditions MIN. MAX. Unit Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T −10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (0.5 + wDA) T − 10 ns RAS precharge time <61> tRP (0.5 + wRP) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA) T − 10 ns Column address read time (to RAS↑) <64> tRAL (2 + wCP + wDA) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRP) T − 10 ns CAS hold time <67> tCSH (1.5 + wRH + wDA) T − 10 ns Delay time from RAS to column address <76> tRAD (0.5 + wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH) T − 10 ns CAS precharge time <81> tCP (0.5 + wCP) T − 10 ns RAS hold time for CAS precharge <83> tRHCP (2 + wCP + wDA) T − 10 ns WE hold time (from CAS↓) <85> tWCH (1 + wDA) T − 10 ns Data hold time (from CAS↓) <87> tDH (0.5 + wDA) T − 10 ns WE read time (to RAS↑) On-page <88> tRWL wCP = 0 (1.5 + twDA) T − 10 ns WE read time (to CAS↑) On-page <89> tCWL wCP = 0 (0.5 + wDA) T − 10 ns WE pulse width On-page <92> tWP wCP = 0 (1 + wDA) T − 10 ns Write cycle time <93> tHPC (1 + wDA + wCP) T − 10 ns RAS pulse width <94> tRASP (2.5 + wRH + wDA) T − 10 ns CAS pulse width <95> tHCAS (0.5 + wDA) T − 10 ns Off-page <101> tWCS1 (1 + wRP + wRH) T − 10 ns On-page <102> tWCS2 wCPT − 10 ns Off-page <103> tDS1 (1.5 + wRP + wRH) T − 10 ns On-page <104> tDS2 (0.5 + wCP) T − 10 ns WE setup time (to CAS↓) Data setup time (to CAS↓) wCP ≥ 1 Remarks 1. T = tCYK 2. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 56 Data Sheet U13844EJ3V0DS µPD70F3102-33 (f) Write timing (EDO DRAM) (2/2) TRPW T1 TRHW T2 TDAW TCPW TB TDAW TE CLKOUT (Output) <58> <56> <57> <59> Row address A0 to A23 (Output) <58> Column address <59> Column address <76> <64> <61> <94> RASn (Output) <67> <66> <77> <83> <95> <81> <63> UCAS (Output) LCAS (Output) <93> <95> <89> <88> RD (Output) OE (Output) <102> <85> <101> <85> <92> WE (Output) <103> D0 to D15 (I/O) <87> Data <104> <87> Data BCYST (Output) WAIT (Input) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 57 µPD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns Delay time from OE↑ to data output <37> tDRDOD (0.5 + i) T − 10 ns Delay time from address to IOWR↓ <41> tDAWR (0.5 + wRP) T − 10 ns Address setup time (to IOWR↑) <42> tSAWR (2 + wRP + wRH + wDA + w) T −10 ns Delay time from IOWR↑ to address <43> tDWRA 0.5T − 10 ns Delay time from IOWR↑ to RD↑ <48> tDWRRD wF = 0 0 ns wF = 1 T − 10 ns IOWR low-level width <50> tWWRL (2 + wRH + wDA + w) T − 10 ns Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T − 10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (1.5 + wDA + wF + w) T − 10 ns Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + wF + w) T − 10 ns RAS precharge time <61> tRP (0.5 + wRP) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA + wF + w) T − 10 ns Column address read time for RAS <64> tRAL (2 + wCP + wDA + wF + w) T − 10 ns CAS pulse width <65> tCAS (1 + wDA + wF + w) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRP) T −10 ns CAS hold time <67> tCSH (2 + wRH + wDA + wF + w) T − 10 ns WE setup time (to CAS↓) <68> tRCS (2 + wRP + wRH) T − 10 ns WE hold time (from RAS↑) <69> tRRH 0.5T − 10 ns WE hold time (from CAS↑) <70> tRCH 1.5T − 10 ns CAS precharge time <71> tCPN (2 + wRP + wRH) T − 10 ns Delay time from RAS to column address <76> tRAD (0.5 + wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH) T − 10 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer. 8. i: Number of idle states inserted when a write cycle follows the read cycle. 58 Data Sheet U13844EJ3V0DS µPD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3) Parameter Symbol Conditions MIN. MAX. Unit Output buffer turn-off delay time (from OE↑) <78> tOEZ 0 ns Output buffer turn-off delay time (from CAS↑) <79> tOFF 0 ns CAS precharge time <81> tCP (0.5 + wCP) T − 10 ns High-speed mode cycle time <82> tPC (2 + wCP + wDA + wF + w) T − 10 ns RAS hold time for CAS precharge <83> tRHCP (2.5 + wCP + wDA + wF + w) T − 10 ns RAS pulse width <94> tRASP (2.5 + wRH + wDA + wF + w) T − 10 ns Off-page <96> tOCH1 (2.5 + wRP + wRH + wDA + wF + w) T − 10 ns On-page <97> tOCH2 (1.5 + wCP + wDA + wF + w) T − 10 ns Delay time from DMAAKm↓ to CAS↓ <105> tDDACS (1.5 + wRH) T − 10 ns Delay time from IOWR↓ to CAS↓ <106> tDRDCS (1 + wRH) T − 10 ns Hold time from OE to CAS (from CAS↑) Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer. 8. m = 0 to 3 Data Sheet U13844EJ3V0DS 59 µPD70F3102-33 (g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3) TRPW T1 T2 TRHW TDAW TW T3 TCPW TO1 TDAW TW TO2 CLKOUT (Output) <58> <56> A0 to A23 (Output) <57> <59> Row address Column address Column address <76> <64> <61> <94> <60> RASn (Output) <77> <65> <66> <69> <83> <67> <81> <63> UCAS (Output) LCAS (Output) <71> <70> <82> <96> <79> RD (Output) OE (Output) <105> <48> <97> DMAAKm (Output) <68> WE (Output) IORD (Output) <106> <42> <41> <43> <78> <37> <50> IOWR (Output) <24> D0 to D15 (I/O) Data <25> <24> Data <24> <25> <25> WAIT (Input) BCYST (Output) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits inserted to source-side access during DMA flyby transfer: 0 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 60 Data Sheet U13844EJ3V0DS µPD70F3102-33 (h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3) Parameter Symbol Conditions MIN. MAX. Unit WAIT setup time (to CLKOUT↓) <24> tSWK 15 ns WAIT hold time (from CLKOUT↓) <25> tHKW 2 ns IORD low-level width <32> tWRDL (2 + wRH + wDA + wF + w) T − 10 ns IORD high-level width <33> tWRDH T − 10 ns Delay time from address to IORD↑ <34> tDARD 0.5T − 10 ns Delay time from IORD↑ to address <35> tDRDA (0.5 + i) T − 10 ns Row address setup time <56> tASR (0.5 + wRP) T − 10 ns Row address hold time <57> tRAH (0.5 + wRH) T − 10 ns Column address setup time <58> tASC 0.5T − 10 ns Column address hold time <59> tCAH (1.5 + wDA + wF) T − 10 ns Read/write cycle time <60> tRC (3 + wRP + wRH + wDA + wF + w) T − 10 ns RAS precharge time <61> tRP (0.5 + wRP) T − 10 ns RAS hold time <63> tRSH (1.5 + wDA + wF) T − 10 ns Column address read time for RAS <64> tRAL (2 + wCP + wDA + wF + w) T − 10 ns CAS pulse width <65> tCAS (1 + wDA + wF) T − 10 ns CAS to RAS precharge time <66> tCRP (1 + wRP) T − 10 ns CAS hold time <67> tCSH (2 + wRH + wDA + wF + w) T − 10 ns CAS precharge time <71> tCPN (2 + wRP + wRH + w) T − 10 ns Delay time from RAS to column address <76> tRAD (0.5 + wRH) T − 10 ns RAS to CAS delay time <77> tRCD (1 + wRH + w) T − 10 ns CAS precharge time <81> tCP (0.5 + wCP + w) T − 10 ns High-speed page mode cycle time <82> tPC (2 + wCP + wDA + wF + w) T − 10 ns RAS hold time for CAS precharge <83> tRHCP (2.5 + wCP + wDA + w) T − 10 ns WE hold time (from CAS↓) <85> tWCH (1 + wDA ) T − 10 ns WE read time (to RAS↑) <88> tRWL wCP = 0 (1.5 + wDA + w) T − 10 ns WE read time (to CAS↑) <89> tCWL wCP = 0 (1 + wDA + w) T − 10 ns WE pulse width <92> tWP wCP = 0 (1 + wDA + w) T − 10 ns RAS pulse width <94> tRASP (2.5 + wRH + wDA + wF + w) T − 10 ns Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wDA: Number of waits specified by DACxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 7. wF: Number of waits inserted to source-side access during DMA flyby transfer. 8. i: Number of idle states inserted when a write cycle follows the read cycle. Data Sheet U13844EJ3V0DS 61 µPD70F3102-33 (h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3) Parameter Symbol Conditions MIN. MAX. Unit Off-page <101> tWCS1 wCP = 0 (1 + wRH + wRP + w) T − 10 ns On-page <102> tWCS2 wCP ≥ 1 wCPT − 10 ns Delay time from DMAAKm↓ to CAS↓ <105> tDDACS (1.5 + wRH + w) T − 10 ns Delay time from IORD↓ to CAS↓ <106> tDRDCS (1 + wRH + w) T − 10 ns Delay time from WE↑ to IORD↑ <107> tDWERD wF = 0 0 ns wF = 1 T − 10 ns WE setup time (to CAS↓) Remarks 1. T = tCYK 2. w: Number of waits due to WAIT 3. wRH: Number of waits specified by RHCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 4. wRP: Number of waits specified by RPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 5. wCP: Number of waits specified by CPCxx bit of register DRCn (n = 0 to 3, xx = 00 to 03, 10 to 13) 6. wF: Number of waits inserted to source-side access during DMA flyby transfer. 7. m = 0 to 3 62 Data Sheet U13844EJ3V0DS µPD70F3102-33 (h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3) TRPW T1 TRHW TW T2 TDAW T3 TCPW TW TO1 TDAW TO2 CLKOUT (Output) <56> A0 to A23 (Output) <57> <58> Row address <59> Column address Column address <76> <64> <61> <94> <60> RASn (Output) <77> <65> <66> <67> <63> <81> UCAS (Output) LCAS (Output) <71> <82> <83> RD (Output) OE (Output) <101> <102> <88> <89> <85> WE (Output) <92> <105> DMAAKm (Output) IOWR (Output) <106> <107> <35> <34> IORD (Output) <32> <25> <33> D0 to D15 (I/O) Data <24> <24> <25> Data <24> <25> WAIT (Input) BCYST (Output) Remarks 1. These timings are for the following cases (n = 0 to 3, xx = 00 to 03, 10 to 13): Number of waits (TRPW) specified by RPCxx bit of register DRCn: 1 Number of waits (TRHW) specified by RHCxx bit of register DRCn: 1 Number of waits (TDAW) specified by DACxx bit of register DRCn: 1 Number of waits (TCPW) specified by CPCxx bit of register DRCn: 1 Number of waits inserted to source-side access during DMA flyby transfer: 0 2. Broken lines indicate high impedance. 3. n = 0 to 7, m = 0 to 3 Data Sheet U13844EJ3V0DS 63 µPD70F3102-33 (i) CBR refresh timing Parameter RAS precharge time RAS pulse width Symbol <61> tRAS <108> MIN. MAX. Unit (1.5 + wRRW ) T − 10 tRP <62> CAS hold time Conditions tCHR ns (1.5 + wRCW Note ) T − 10 ns (1.5 + wRCW Note ) T − 10 ns (3 +wRRW + wRCW Note ) T − 10 ns REFRQ pulse width <109> tWRFL RAS precharge CAS hold time <110> tRPC (0.5 + wRRW ) T − 10 REFRQ active delay time (from CLKOUT↓) <111> tDKRF 2 10 ns REFRQ inactive delay time (from CLKOUT↓) <112> tHKRF 2 10 ns CAS setup time <113> tCSR T − 10 ns ns Note wRCW is inserted for at least 1 clock, regardless of the setting of bits RCW0 to RCW2 of register RWC. Remarks 1. T = tCYK 2. wRRW : Number of waits specified by bits RRW0 and RRW1 of register RWC. 3. wRCW : Number of waits specified by bits RCW0 to RCW2 of register RWC. TRRW T1 T2 TRCWNote TRCW T3 TI CLKOUT (Output) <111> <112> <109> REFRQ (Output) <61> <62> RASn (Output) <110> <110> <113> <108> UCAS (Output) LCAS (Output) Note This TRCW is always inserted, regardless of the setting of bits RCW0 to RCW2 of register RWC. Remarks 1. These timings are for the following cases: Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1 Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 2 2. n = 0 to 7 64 Data Sheet U13844EJ3V0DS µPD70F3102-33 (j) CBR self refresh timing Parameter Symbol Conditions MIN. MAX. Unit REFRQ active delay time (from CLKOUT↓) <111> tDKRF 2 10 ns REFRQ inactive delay time (from CLKOUT↓) <112> tHKRF 2 10 ns CAS hold time <114> tCHS −5 ns RAS precharge time <115> tRPS (1 + 2wSRW ) T − 10 ns Remarks 1. T = tCYK 2. wSRW : Number of waits specified by bits SRW0 to SRW2 of register RWC. TRRW TH TH TH TRCW TH TI TSRW TSRW CLKOUT (Output) <111> <112> REFRQ (Output) <115> RASn (Output) <114> UCAS (Output) LCAS (Output) Output signals other than above Remarks 1. These timings are for the following cases: Number of waits (TRRW) specified by bits RRW0 and RRW1 of register RWC: 1 Number of waits (TRCW) specified by bits RCW0 to RCW2 of register RWC: 1 Number of waits (TSRW) specified by bits SRW0 to SRW2 of register RWC: 2 2. Broken lines indicate high impedance. 3. n = 0 to 7 Data Sheet U13844EJ3V0DS 65 µPD70F3102-33 (7) DMAC timing Parameter Symbol Conditions MIN. MAX. Unit DMARQn setup time (to CLKOUT↑) <116> tSDRK 15 ns DMARQn hold time (from CLKOUT↑) <117> tHKDR1 2 ns <118> tHKDR2 Until DMAAKn↓ ns DMAAKn output delay time (from CLKOUT↓) <119> tDKDA 2 10 ns DMAAKn output hold time (from CLKOUT↓) <120> tHKDA 2 10 ns TCn output delay time (from CLKOUT↓) <121> tDKTC 2 10 ns TCn output hold time (from CLKOUT↓) <122> tHKTC 2 10 ns Remark n = 0 to 3 CLKOUT (Output) <117> <116> <118> DMARQn (Input) <116> <119> <120> DMAAKn (Output) <122> <121> TCn (Output) Remark n = 0 to 3 66 Data Sheet U13844EJ3V0DS µPD70F3102-33 [MEMO] Data Sheet U13844EJ3V0DS 67 µPD70F3102-33 (8) Bus hold timing (1/2) Parameter Symbol Conditions MIN. MAX. Unit HLDRQ setup time (to CLKOUT↑) <123> tSHRK 15 ns HLDRQ hold time (from CLKOUT↑) <124> tHKHR 2 ns Delay time from CLKOUT↓ to HLDAK <125> tDKHA 2 HLDRQ high-level width <126> tWHQH T + 17 ns HLDAK low-level width <127> tWHAL T−8 ns Delay time from CLKOUT↓ to bus float <128> tDKCF Delay time from HLDAK↑ to bus output <129> tDHAC 0 ns Delay time from HLDRQ↓ to HLDAK↓ <130> tDHQHA1 2.5T ns Delay time from HLDRQ↑ to HLDAK↑ <131> tDHQHA2 0.5T Remark T = tCYK 68 Data Sheet U13844EJ3V0DS 10 10 1.5T ns ns ns µPD70F3102-33 (8) Bus hold timing (2/2) T1 T2 T3 TI TH TH TH TI T1 CLKOUT (Output) <123> <124> <123> <123> <124> <123> <126> HLDRQ (Intput) <125> <125> <130> <131> HLDAK (Output) <127> <128> A0 to A23 (Output) D0 to D15 (I/O) Address <129> Undefined Data CSn/RASn (Output) BCYST (Output) RD (Output) WE (Output) UCAS (Output) LCAS (Output) Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 7 Data Sheet U13844EJ3V0DS 69 µPD70F3102-33 (9) Interrupt timing Parameter Symbol Conditions MIN. MAX. Unit NMI high-level width <132> tWNIH 500 ns NMI low-level width <133> tWNIL 500 ns INTPn high-level width <134> tWITH 4T + 10 ns INTPn low-level width <135> tWITL 4T + 10 ns Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153 2. T = tCYK <132> <133> <134> <135> NMI (Input) INTPn (Input) Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, and 150 to 153 (10) RPU timing Parameter Symbol Conditions MIN. MAX. Unit TI1n high-level width <136> tWTIH 3T + 18 ns TI1n low-level width <137> tWTIL 3T + 18 ns TCLR1n high-level width <138> tWTCH 3T + 18 ns TCLR1n low-level width <139> tWTCL 3T + 18 ns Remarks 1. n = 0 to 5 2. T = tCYK <136> <137> <138> <139> TI1n (Input) TCLR1n (Input) Remark n = 0 to 5 70 Data Sheet U13844EJ3V0DS µPD70F3102-33 (11) UART0, UART1 timing (synchronized with clock, master mode only) Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <140> tCYSK0 Output 250 ns SCKn high-level width <141> tWSK0H Output 0.5tCYSK0 − 20 ns SCKn low-level width <142> tWSK0L Output 0.5tCYSK0 − 20 ns RXDn setup time (to SCKn↑) <143> tSRXSK 30 ns RXDn hold time (from SCKn↑) <144> tHSKRX 0 ns TXDn output delay time (from SCKn↓) <145> tDSKTX TXDn output hold time (from SCKn↑) <146> tHSKTX 20 0.5tCYSK0 − 5 ns ns Remark n = 0, 1 <140> <141> <142> SCKn (I/O) <143> RXDn (Input) <144> Input data <145> <146> TXDn (Output) Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0, 1 Data Sheet U13844EJ3V0DS 71 µPD70F3102-33 (12) CSI0 to CSI3 timing (a) Master mode Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <147> tCYSK1 Output 100 ns SCKn high-level width <148> tWSK1H Output 0.5tCYSK1 − 20 ns SCKn low-level width <149> tWSK1L Output 0.5tCYSK1 − 20 ns SIn setup time (to SCKn↑) <150> tSSISK 30 ns SIn hold time (from SCKn↑) <151> tHSKSI 0 ns SOn output delay time (from SCKn↓) <152> tDSKSO SOn output hold time (from SCKn↑) <153> tHSKSO 20 0.5tCYSK1 − 5 ns ns Remark n = 0 to 3 (b) Slave mode Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <147> tCYSK1 Input 100 ns SCKn high-level width <148> tWSK1H Input 30 ns SCKn low-level width <149> tWSK1L Input 30 ns SIn setup time (to SCKn↑) <150> tSSISK 10 ns SIn hold time (from SCKn↑) <151> tHSKSI 10 ns SOn output delay time (from SCKn↓) <152> tDSKSO SOn output hold time (from SCKn↑) <153> tHSKSO 30 tWSK1H Remark n = 0 to 3 <147> <148> <149> SCKn (I/O) <150> Sln (Input) <151> Input data <152> SOn (Output) <153> Output data Remarks 1. Broken lines indicate high impedance. 2. n = 0 to 3 72 Data Sheet U13844EJ3V0DS ns ns µPD70F3102-33 A/D Converter Characteristics (TA = −40 to +85°°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%, VSS = 0 V, HVDD − 0.5 V ≤ AVDD ≤ HVDD) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution − Overall error − ±4 LSB Quantization error − ±1/2 LSB 10 µs 10 Conversion time tCONV 5 Sampling time tSAMP Conversion clockNote/6 bit ns Zero scale error − ±4 LSB Scale error − ±4 LSB Linearity error − ±3 LSB AVREF + 0.3 V Analog input voltage VIAN Analog input resistance RAN AVREF input voltage AVREF AVREF input current AVDD current −0.3 2 AVREF = AVDD 4.5 MΩ 5.5 V AIREF 2.0 mA AIDD 6 mA Note The conversion clock is the clock value set by the ADM1 register. Data Sheet U13844EJ3V0DS 73 µPD70F3102-33 4.2 Flash Memory Programming Mode Basic Characteristics (TA = −40 to +85°°C (Other Than When Rewriting), HVDD = AVDD = 4.5 to 5.5 V, VDD = 3.0 to 3.6 V, VSS = AVSS = 0 V) (1/2) Parameter Operating frequency VPP supply voltage Symbol Conditions fX TYP. MAX. Unit 33 MHz 8.1 V 1.2VDD V 20 VPP1 During flash memory programming VPPL VPP low-level detection 0.8VDD VPPM VPP and VDD level detection 0.65VDD VDD VDD + 0.3 V VPPH VPP high-voltage level detection 7.5 7.8 8.1 V 50 mA 150 mA HVDD supply current IDD VPP = VPP1 VPP supply current IPP VPP = 8.1 V Step erase time MIN. tER 7.5 7.8 Note 1 K, P category 5 s 0.2 s (Recommendation: Step erase = 5 s) Other than K, P categoryNote 1 (Recommendation: Step erase = 0.2 s) Total erase time tERA K, P categoryNote 1 60 s 20 s 1.01 ms When step erase time =5s Note 2 Other than K, P categoryNote 1 When step erase time = 0.2 s Note 2 Write-back time tWB Note 3 0.99 1 Notes 1. The category is indicated by the fifth letter from the left of the lot number. 2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included. 3. The recommended set value of the write-back time is 1 ms. Caution The I category is applied to engineering samples only. The number of rewrites is not guaranteed for I category products. Remark When PG-FP3 is used, the time parameters required for write/erase are automatically set by downloading parameter files. Do not change the set values unless otherwise specified. 74 Data Sheet U13844EJ3V0DS µPD70F3102-33 Basic Characteristics (TA = −40 to +85°°C (Other Than When Rewriting), HVDD = AVDD = 4.5 to 5.5 V, VDD = 3.0 to 3.6 V, VSS = AVSS = 0 V) (2/2) Parameter Symbol Number of write-backs per writeback command Number of erase/write-backs Step write time CWB Number of rewrites MIN. TYP. When write-back time = 1 ms Note 1 CERWB tWT Total write time per word Conditions tWTW CERWR Note 2 18 Setting: Step write time = 20 µs (1 word = 4 bytes) Note 3 20 K categoryNote 4 20 MAX. Unit 300 Times/writeback command 16 Times 22 µs 200 µs/word 5 Tiimes Note 4 P category 10 Times Other than K, P categoryNote 4 20 Times One erase + one write after erase = one rewrite Note 5 Temperature during write TPRG K, P categoryNote 4 10 40 °C Other than K, P categoryNote 4 10 85 °C Notes 1. When the write-back command is issued, write-back is performed once. Therefore, the retry count must be the maximum value minus the number of commands issued. 2. The recommended set value of the step write time is 20 µs. 3. The actual write time per word is the sum of this value plus 100 µs. The internal verify time during and after write is not included. 4. The category is indicated by the fifth letter from the left of the lot number. 5. When writing initially to shipped products, “erase to write” and “write only” are both counted as one rewrite. Example (P: Write E: Erase) Product → P → E → P → E → P: Three rewrites Product → E → P → E → P → E → P: Three rewrites Caution The I category is applied to engineering samples only. The number of rewrites is not guaranteed for I category products. Remark When PG-FP3 is used, the time parameters required for write/erase are automatically set by downloading parameter files. Do not change the set values unless otherwise specified. Data Sheet U13844EJ3V0DS 75 µPD70F3102-33 Serial Write Operation Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD↑ to VPP↑ set time <201> tDRPSR 200 ns VPP↑ to RESET↑ set time <202> tPSRRF 1 µs RESET↑ to VPP count start time <203> tRFOF 5T + 500 µs Count execution time <204> tCOUNT VPP counter high-level width <205> tCH 1 µs VPP counter low-level width <206> tCL 1 µs VPP counter rise time <207> tR 3 µs VPP counter fall time <208> tF 3 µs VPP = 7.8 V 10 VDD, HVDD VDD, HVDD 0V <204> <201> <203> <206> <205> <207> VPPH VPP VDD <208> 0V <202> HVDD RESET (Input) 0V 76 Data Sheet U13844EJ3V0DS ms µPD70F3102-33 5. PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I J M K P S N S L M NOTE ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 22.0±0.2 B 20.0±0.2 C 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22 +0.05 −0.04 I J 0.10 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.145+0.055 −0.045 N 0.10 P 1.4±0.1 Q 0.125±0.075 R 3° +7° −3° S 1.7 MAX. S144GJ-50-8EU-3 Data Sheet U13844EJ3V0DS 77 µPD70F3102-33 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 22.0±0.2 B C 20.0±0.2 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N P 0.08 1.4 Q 0.10±0.05 R 3° +4° −3° S 1.5±0.1 S144GJ-50-UEN 78 Data Sheet U13844EJ3V0DS µPD70F3102-33 6. RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document “Semiconductor Device Mounting Technology Manual (C10535E)”. For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions µPD70F3102GJ-33-8EU: 144-pin plastic LQFP (fine pitch) (20 × 20) µPD70F3102GJ-33-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: Twice or less, Exposure limit: 3 daysNote Recommended Condition Symbol IR35-103-2 (after that, prebake at 125°C for 10 hours) VPS Package peak temperature: 215°C, Time: 25 to 40 seconds max. (at 200°C or higher), Count: Twice or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for 10 hours) Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) VP15-103-2 − Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Data Sheet U13844EJ3V0DS 79 µPD70F3102-33 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Related Documents µPD70F3102A-33 Data Sheet (U13845E) µPD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet (U13995E) µPD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet (U14168E) The related documents in this publication may include preliminary versions. However, preliminary versions are not marked as such. The V850E/MS1 is a trademark of NEC Corporation. 80 Data Sheet U13844EJ3V0DS µPD70F3102-33 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U13844EJ3V0DS 81 µPD70F3102-33 • The information in this document is current as of March, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4