DATA SHEET MOS Integrated Circuit µPD70732 V810TM 32-BIT MICROPROCESSOR The µPD70732 (a.k.a. V810) microprocessor is NEC’s first microprocessor of the V810 family TM for embedded control applications. The V810 employs a RISC architecture for embedded control applications. This product has high-speed real time response, high-speed integer operation instruction, bit string instruction, floating-point operation instruction, and significantly high cost performance is realized for applications such as facsimile, digital PPC, word processor, image processor, real time control device, etc. The functions are described in detail in the following User’s Manuals, which should be read before starting design work. • V805TM, V810 User’s Manual Hardware : U10661E • V810 Family User’s Manual Architecture : U10082E Features High-performance 32-bit architecture for embedded control application • 32-bit separate address/data bus • 1-Kbyte cache memory • • • • Pipeline structure of 1 clock pitch 16-bit fixed instructions (with some exceptions) 32-bit general-purpose registers: 32 4-Gbyte linear address space • Register/flag hazard interlocked by hardware Dynamic bus sizing function (16 bits) 16-bit bus fixing function 16-bit bus system can be configured. Instructions ideal for various application fields • Floating-point operation instructions (based upon IEEE754 data format) • Bit string instructions 16 levels of high-speed interrupt responses Clock can be stopped by internal static operation Maximum operating frequency: 16/20/25 MHz Low voltage: VDD = 2.7 to 3.6 V (Max. 16 MHz) VDD = 2.2 to 3.6 V (Max. 10 MHz) ★ Small package versions available (14 x 14 mm fine-pitch TQFP) The information in this document is subject to change without notice. Document No. U10691EJ3V0DS00 (3rd edition) Date Published September 1996 P Printed in Japan The mark ★ shows major revised points. © 1993 µPD70732 Ordering Information Part Number ★ Package Max. operating freq. (MHz) µPD70732GD-16-LBB 120-pin plastic QFP (28 x 28 mm) 16 µPD70732GD-20-LBB 120-pin plastic QFP (28 x 28 mm) 20 µPD70732GD-25-LBB 120-pin plastic QFP (28 x 28 mm) 25 µPD70732GC-25-9EV 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) 25 176-pin ceramic PGA (Seam weld) 25 µPD70732R-25 Pin Outline A31 to A1 V810 CLK RESET INT INTV3 to INTV0 NMI D31 to D0 BE3 to BE0 ST1, ST0 DA MRQ R/W HLDRQ BCYST HLDAK BLOCK READY SZRQ SIZ16B ICHEEN ADRSERR 2 µPD70732 Pin Configuration • 120-pin plastic QFP (28 x 28 mm) (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD ST0 HLDRQ SZRQ READY A2 A3 A4 A5 A6 A7 A8 GND A9 VDD VDD GND A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND VDD D19 D20 D21 GND D22 D23 D24 D25 D26 D27 D28 D29 D30 VDD GND VDD D31 A31 A30 A29 A28 A27 A26 A25 A24 A23 GND A22 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VDD IC1 IC1 IC1 RESET D0 D1 D2 GND D3 D4 GND D5 D6 D7 VDD VDD D8 D9 D10 D11 D12 GND D13 D14 D15 D16 D17 D18 GND 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 IC1 IC2 IC2 ICHEEN NMI INT INTV0 INTV1 INTV2 INTV3 BLOCK GND VDD CLK GND SIZ16B DA VDD BCYST HLDAK ADRSERR BE0 BE1 A1 BE2 BE3 R/W MRQ ST1 GND µ PD70732GD-xx-LBB Cautions 1. Leave the IC1 pin open. 2. Connect the IC2 pin to GND. Remark IC: Internally Connected 3 µPD70732 ★ • 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IC1 IC2 IC2 ICHEEN NMI INT INTV0 INTV1 INTV2 INTV3 BLOCK GND VDD CLK GND SIZ16B DA VDD BCYST HLDAK ADRSERR BE0 BE1 A1 BE2 BE3 R/W MRQ ST1 GND GND A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND VDD VDD A9 GND A8 A7 A6 A5 A4 A3 A2 READY SZRQ HLDRQ ST0 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VDD D19 D20 D21 GND D22 D23 D24 D25 D26 D27 D28 D29 D30 VDD GND VDD D31 A31 A30 A29 A28 A27 A26 A25 A24 A23 GND A22 VDD 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND D18 D17 D16 D15 D14 D13 GND D12 D11 D10 D9 D8 VDD VDD D7 D6 D5 GND D4 D3 GND D2 D1 D0 RESET IC1 IC1 IC1 VDD µ PD70732GC-25-9EV Cautions 1. VDD is power supply pin. All V DD pins should be connected to a +5V power supply (the same power supply). 2. GND is ground pin. All GND pins should be connected to the same GND. 3. Leave the IC1 pin open. 4. Connect the IC2 pin to GND. Remark 4 IC: Internally Connected µPD70732 • 176-pin ceramic PGA (Seam weld) µ PD70732R-25 Bottom View Top View 15 14 13 12 11 10 9 8 Insertion guide pin 7 6 5 4 3 2 1 Q P N M L K J H G F E D C B A A B C D E F G H J K L M N P Q No. 1 pin index Remark The insertion guide pin is not included in the number of pins. No. Signal No. Signal No. Signal No. Signal A1 IC2 B3 GND C5 VDD D7 VDD A2 D12 B4 D11 C6 D8 D8 VDD A3 D13 B5 GND C7 VDD D9 GND A4 D10 B6 D7 C8 D4 D10 IC3 A5 GND B7 VDD C9 D2 D11 IC2 A6 D6 B8 D3 C10 IC3 D12 GND A7 IC2 B9 GND C11 VDD D13 INT A8 D5 B10 D0 C12 IC1 D14 INTV1 A9 IC2 B11 GND C13 IC2 D15 GND A10 D1 B12 IC1 C14 VDD E1 D27 A11 VDD B13 GND C15 NMI E2 D25 A12 RESET B14 IC1 D1 D23 E3 D21 A13 IC1 B15 ICHEEN D2 D22 E4 D19 A14 IC1 C1 VDD D3 D20 E12 IC3 A15 IC2 C2 VDD D4 GND E13 INTV0 B1 D17 C3 D16 D5 D15 E14 IC3 B2 D18 C4 D14 D6 D9 E15 IC1 5 µPD70732 No. Signal No. Signal No. Signal No. Signal F1 VDD J4 VDD M7 VDD P4 A12 F2 D26 J12 IC2 M8 A5 P5 GND F3 D24 J13 IC2 M9 VDD P6 A8 F4 GND J14 IC1 M10 ST1 P7 GND F12 INTV2 J15 IC1 M11 A1 P8 A6 F13 INTV3 K1 IC2 M12 GND P9 GND F14 VDD K2 A27 M13 BCYST P10 SZRQ F15 GND K3 A25 M14 DA P11 GND G1 D29 K4 A24 M15 SIZ16B P12 MRQ G2 D28 K12 GND N1 VDD P13 GND G3 IC2 K13 BLOCK N2 VDD P14 ADRSERR G4 IC2 K14 VDD N3 A17 P15 BE0 G12 VDD K15 VDD N4 A15 Q1 IC2 G13 IC2 L1 A28 N5 VDD Q2 A13 G14 IC1 L2 A26 N6 A9 Q3 A14 G15 IC1 L3 A22 N7 VDD Q4 A11 H1 A31 L4 A20 N8 VDD Q5 GND H2 D30 L12 HLDAK N9 A3 Q6 A7 H3 GND L13 VDD N10 HLDRQ Q7 IC2 H4 D31 L14 IC1 N11 VDD Q8 A4 H12 GND L15 IC1 N12 BE2 Q9 IC2 H13 CLK M1 GND N13 BE1 Q10 A2 H14 IC1 M2 A23 N14 VDD Q11 READY H15 IC2 M3 A21 N15 IC1 Q12 ST0 J1 A30 M4 GND P1 A18 Q13 BE3 J2 A29 M5 A16 P2 A19 Q14 R/W J3 IC2 M6 A10 P3 GND Q15 IC2 Cautions 1. Leave the IC1 pin open. 2. Connect the IC2 pin to GND. 3. Connect the IC3 pin to power supply. Remark 6 IC: Internally Connected µPD70732 CONTENTS 1. PIN FUNCTIONS .............................................................................................................................. 8 1.1 Pin Function List ................................................................................................................... 8 1.2 Pin I/O Circuits and Recommended Connection of Unused Pins ................................. 10 ★ 2. REGISTER SET ............................................................................................................................... 12 2.1 Program Register Set ........................................................................................................... 13 2.2 System Register Set ............................................................................................................. 14 ★ 3. DATA TYPES ................................................................................................................................... 15 3.1 Data Types ............................................................................................................................. 15 ★ 3.2 3.1.1 Data type and addressing ......................................................................................................... 15 3.1.2 Integer ........................................................................................................................................ 16 3.1.3 Unsigned integer ....................................................................................................................... 16 3.1.4 Bit string ..................................................................................................................................... 16 3.1.5 Single-precision floating-point data .......................................................................................... 17 Data Alignment ...................................................................................................................... 17 4. ADDRESS SPACE ........................................................................................................................... 18 ★ 5. BUS INTERFACE FUNCTION ......................................................................................................... 21 ★ 6. INTERRUPT AND EXCEPTION ....................................................................................................... 22 ★ 7. CACHE ............................................................................................................................................. 23 ★ 8. RESET .............................................................................................................................................. 24 ★ 9. INSTRUCTION SET ......................................................................................................................... 25 9.1 Instruction Format ................................................................................................................ 25 9.2 Instruction Mnemonic (in alphabetical order) ................................................................... 27 ★ 10. ELECTRICAL SPECIFICATIONS .................................................................................................... 10.1 Specifications When VDD = +5 V ± 10% .............................................................................. 10.2 Specifications When VDD = 2.7 to 3.6 V ............................................................................. 10.3 Specifications When VDD = 2.2 to 3.6 V ............................................................................. 37 38 47 51 11. PACKAGE DRAWINGS ................................................................................................................... 59 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 62 7 µPD70732 1. PIN FUNCTIONS 1.1 Pin Function List Bus hold status Name I/O Function Bus hold Bus idle during operation status status at reset at reset Address bus Hi-Z Hi-Z H Note Bidirectional data bus Hi-Z Hi-Z Hi-Z Indicates valid data bus when data is accessed Hi-Z Hi-Z H A31 to A1 3-state (Address Bus) output D31 to D0 3-state (Data Bus) I/O BE3 to BE0 3-state (Byte Enable) output ST1, ST0 (Status) 3-state output Indicates type of bus cycle Hi-Z Hi-Z H DA 3-state Strobe signal for bus cycle Hi-Z Hi-Z H (Data Access) output MRQ 3-state Indicates memory access Hi-Z Hi-Z H (Memory Request) output R/W 3-state Distinguishes between read access and write access Hi-Z Hi-Z H (Read/Write) output BCYST (Bus Cycle Start) 3-state output Indicates start of bus cycle Hi-Z Hi-Z H READY (Ready) Input Extends bus cycle — — — HLDRQ Input Requests bus mastership — — — Acknowledges HLDRQ L L H Input Requests bus sizing — — — Input Fixes external data bus width to 16 bits — — — Requests to inhibit use of bus L L L Input Operates instruction cache — — — Input Interrupt request — — — Input Interrupt level — — — (Hold Request) HLDAK Output (Hold Acknowledge) SZRQ (Bus Sizing Request) SIZ16B (Bus Size 16 Bit) BLOCK Output (Bus Lock) ICHEEN (Instruction Cache Enable) INT (Maskable Interrupt) INTV3 to INTV0 (Interrupt Level) Note 8 A1 pin is “H” in the 16-bit bus fixed mode; otherwise, it is “L”. µPD70732 Name NMI I/O Function Bus hold Bus hold status status during at reset operation Bus idle status at reset Input Non-maskable interrupt request — — — CLK Input CPU clock input — — — RESET Input Resets internal status — — — Not H H (Non-Maskable Interrupt) (Reset) ADRSERR Output Indicates that data alignment is illegal (Address Error) affected — Positive power supply — — — GND (Ground) — Ground potential (0 V) — — — IC1 — Internally connected (Leave this pin open.) — — — — Internally connected (Ground this pin.) — — — — Internally connected (Connect this pin to power supply.) — — — VDD (Power Supply) (Internally Connected 1) IC2 (Internally Connected 2) IC3 (Internally Connected 3) 9 µPD70732 ★ 1.2 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. Figure 1-1 shows the I/O circuit of each type. Table 1-1. Pin I/O Circuit Types and Recommended Connection Method of Unused Pins Pin I/O Circuit Type D31 to D0 5 A31 to A1 4 Recommended Connection Method Open BE3 to BE0 ST1, ST0 DA MRQ R/W BCYST READY 1 HLDRQ Connect to GND via resistor Connect to VDD via resistor HLDAK 4 Open SZRQ 1 Connect to VDD via resistor SIZ16B Connect to GND via resistor BLOCK 4 Open ICHEEN 1 Connect to VDD via resistor INT Connect to GND via resistor INTV3 to INTV0 Connect to VDD via resistor NMI CLK — RESET 10 ADRSERR 4 Open IC1 — IC2 — Connect to GND IC3 — Connect to VDD µPD70732 Figure 1-1. Pin I/O Circuit Type 1 Type 5 VDD VDD data P-ch P-ch IN/OUT IN output disable N-ch N-ch input enable Type 4 VDD data P-ch OUT output disable N-ch Push-pull output that can be output high impedance (both P-ch and N-ch are off). 11 µPD70732 ★ 2. REGISTER SET The registers of the V810 can be classified into two types: general-purpose program register set and dedicated system register set. All registers are 32 bits wide. Program register sets 31 System register sets 0 31 0 r0 Zero Register EIPC Exception/Interrupt PC r1 Reserved for Address Generation EIPSW Exception/Interrupt PSW r2 Handler Stack Pointer (hp) r3 Stack Pointer (sp) r4 Global Pointer (gp) FEPC Fatal Error PC r5 Text Pointer (tp) FEPSW Fatal Error PSW 31 0 r6 r7 31 r8 ECR 0 Exception Cause Register r9 r10 31 r11 PSW 0 Program Status Word r12 r13 31 r14 PIR 0 Processor ID Register r15 r16 31 r17 TKCW 0 Task Control Word r18 r19 31 r20 CHCW 0 Cache Control Word r21 r22 31 r23 ADTRE r24 r25 r26 String Destination Bit Offset r27 String Source Bit Offset r28 String Length r29 String Destination r30 String Source r31 Link Pointer (lp) 31 PC 12 0 Program Counter 0 Address Trap Register µPD70732 2.1 Program Register Set The program register set is composed of general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. All these registers can be used as data registers or address registers. Of these registers, r0 and r26 through r30 are implicitly used by some instructions, and r1 through r5 and r31 are implicitly used by the assembler and C compiler. Therefore, when using these registers, it is necessary to take special care such as saving these registers’ contents to different areas before using these registers and restoring the contents after using them. Table 2-1. Program Registers Register Application Operation r0 Zero register Always holds zeros. r1 Register reserved for assembler Used as a working register to generate a 32-bit immediate data. r2 Handler stack pointer Used as the stack pointer for the handler. r3 Stack pointer Used to generate a stack frame at a function call. r4 Global pointer Used to access a global variable in the data area. r5 Text pointer Points the start address of the text area. r6 to r25 — r26 String destination bit offset r27 String source bit offset r28 String length register r29 String destination address register r30 String address register r31 Link pointer (2) Stores address or data variables. Used in a bit-string instruction execution. Stores the return address at execution of a JAL instruction. Program Counter The program counter (PC) indicates the address of the instruction currently executed by the program. Bit 0 of the PC is fixed to 0, and execution cannot branch to an odd address. The contents of the PC are initialized to FFFFFFF0H at reset. 13 µPD70732 2.2 System Register Set The system register set is composed of the following registers that perform operations such as CPU-status control and interrupt information holding. Table 2-2. System Register Number Number Register Name 0 EIPC 1 EIPSW 2 Application Operation Status saving registers for exception/interrupt The EIPC and EIPSW registers save the PC and PSW, respectively, when an exception or interrupt occurs. Because in the V810 the registers incorporated for this purpose are these registers only, save the contents of these registers by means of programming if your application set can cause multiple interrupt requests to be issued in the V810. FEPC Status saving registers for The FEPC and FEPSW registers save the PC and PSW, 3 FEPSW NMI/duplexed exception respectively, when an NMI or duplexed exception occurs. 4 ECR Exception cause register This register, when an exception, maskable interrupt, or NMI occurs, holds its cause. This register consists of 32 bits. Its higher 16 bits, called FECC, hold the exception code for an NMI or duplexed exception, while the lower 16 bits, called EICC, hold the exception code for an exception or maskable interrupt. 5 PSW Program status word This register, also called the program status word, is a set of flags indicating the statuses of the CPU and program (instruction execution results). 6 PIR Processor ID register This register identifies the CPU type number. 7 TKCW Task control word This register controls floating-point operations. 8 to 23 Reserved 24 CHCW Cache control word This register controls the on-chip instruction cache. 25 ADTRE Address trap register This register holds an address and is used for address trapping. When the address in this register matches the PC value, the execution jumps to a predefined address. 26 to 31 Reserved To read or write one of the registers shown above, specify a system register number with the system register load (LDSR) or system register store (STSR) instruction. 14 µPD70732 3. ★ DATA TYPES 3.1 Data Types The data types supported by the V810 are as follows: • Integer (8, 16, 32 bits) • Unsigned integer (8, 16, 32 bits) • Bit string • Single-precision floating-point data (32 bits) 3.1.1 Data type and addressing The V810 uses the little-endian data addressing. In this addressing, if a fixed-length data is located in a memory area, the data must be either of the data types shown below. (1) Byte A byte is a consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte is numbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. To access a byte, specify address A. (See diagram below.) 7 0 A (2) Halfword A halfword is a consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary. Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0). 15 8 7 A+1 (3) 0 A Word/short real A word, also called short real, is a consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to a word boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bits must be 0). 31 24 23 A+3 16 15 A+2 8 7 A+1 0 A 15 µPD70732 3.1.2 Integer In the V810, all integers are expressed in the two’s-complement binary notation, and are composed of either 8 bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bits express higher digits of the integer with the highest bit expressing its sign. Data Length Byte Halfword Word Range 8 bits 16 bits 32 bits –128 to +127 –32768 to +32767 –2147483648 to +2147483647 3.1.3 Unsigned integer An unsigned integer is either zero or a positive integer unlike the integer explained in section 3.1.2 which can be negative as well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers, and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the same as in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a part of the integer. Data Length Byte Halfword Word 8 bits 16 bits 32 bits Range 0 to 255 0 to 65535 0 to 4294967295 3.1.4 Bit string A bit string is a type of data whose bit length is variable from 0 to 232 – 1. To specify a bit-string data, define the following three attributes. • A : address of the string data’s first word (lower two bits must be 0.) • B : in-word bit offset in the string data (0 to 31) • M : bit length of the string data (0 to 232 – 1) The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward, as shown below. The former is the direction from lower addresses to higher addresses while the latter is the direction from higher to lower addresses. M–1 0 M A+8 A+4 A (Word boundary) D Attribute Upward Downward First-word address (0s in bits 1 and 0) A A+4 In-word bit offset (0 to 31) B D M M 32 Bit length (0 to 2 – 1) 16 B µPD70732 3.1.5 Single-precision floating-point data This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floating-point data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offsetexpressed from the bias value – 127, and the mantissa is binary-expressed with the integer part omitted. 31 30 s 23 22 exp (8) 0 mantissa (23) 3.2 Data Alignment In the V810, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s), and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not aligned as specified, the lowest one bit (in the case of word) or two bits (in the case of halfword) of its address will forcibly be masked with 0s when the data is accessed. 17 µPD70732 ★ 4. ADDRESS SPACE The V810 supports 4 Gbytes of linear memory space and I/O space. The CPU outputs 32-bit addresses to the memory and I/Os; therefore, the addresses are from 0 to 232 – 1. Bit number 0 of each byte data is defined as the LSB (Least Significant Bit), and bit number 7 is the MSB (Most Significant Bit). Unless otherwise specified, the byte data at the lower address side of data consisting of two or more bytes is the LSB, and the byte data at the higher address side is the MSB (little endian). Data consisting of 2 bytes is called a halfword, and data consisting of 4 bytes is called a word. The lower address of memory or I/O data of two or more bytes, here, is shown on the right, and the higher address is shown on the left, as follows: 7 Byte of address A 0 A (address) 15 Halfword of address A 8 7 A+1 Word/short real of address A 31 24 23 A+3 18 16 15 A+2 0 A (address) 8 7 A+1 0 A µPD70732 Figure 4-1 shows the memory map of the V810, and Figure 4-2 shows the I/O map. Figure 4-1. Memory Map FFFFFFFFH Interrupt handler tableNote FFFFFE00H FFFFFDFFH General use 00000000H Note For the details, refer to Table 6-1 Exception Codes. 19 µPD70732 Figure 4-2. I/O Map FFFFFFFFH General use 00000000H 20 µPD70732 5. ★ BUS INTERFACE FUNCTION The V810 is equipped with a 32-bit data bus. In the bus interface, there are two modes: 32-bit bus mode which uses the data bus in 32 bits and 16-bit bus fixed mode which fixes the bus in 16 bits. Modes can be switched only at reset using the SIZ16B signal. The 32-bit bus mode has a dynamic bus sizing function which uses the data bus in 16-bit bus width to access the 16-bit peripherals. This function can be used by setting the SZRQ signal active. Access to word data (32-bit data) in the dynamic bus sizing is executed by loading/storing a 16-bit data twice. In the 16-bit bus fixed mode, access to word data (32-bit data) is executed by activating a bus cycle twice. The control signal and the A1 signal output values according to the 16-bit system. The relationship between the external access and byte enable signals (BE3 to BE0) during the 32-bit bus mode and the 16-bit bus fixed mode is shown below. Table 5-1. Relationship among Address, Data Length, Byte Enable Signals and A1 (32-bit bus mode) Operand address Byte enable Data length Byte Halfword Word Bus cycle sequence Bit 1 Bit 0 BE3 BE2 BE1 BE0 0 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 Note 0 Note A1 0 1 1 2 Bus cycle added by dynamic bus sizing Table 5-2. Relationship among Address, Data Length, Byte Enable Signals and A1 (16-bit bus fixed mode) Operand address Byte enable Data length Byte Halfword Word Bus cycle sequence Bit 1 Bit 0 BE3 BE2 BE1 BE0 0 0 Hi-Z Hi-Z 1 0 0 1 0 1 Hi-Z Hi-Z 0 1 0 1 1 0 Hi-Z Hi-Z 1 0 1 1 1 1 Hi-Z Hi-Z 0 1 1 1 0 0 Hi-Z Hi-Z 0 0 0 1 1 0 Hi-Z Hi-Z 0 0 1 1 0 0 Hi-Z Hi-Z 0 0 0 1 1 Note Hi-Z Note A1 Hi-Z 0 0 2 Added bus cycle 21 µPD70732 ★ 6. INTERRUPT AND EXCEPTION Interrupts are events that take place independently of the program execution and can be classified into maskable interrupts and a non-maskable interrupt. An exception is an event that takes place depending upon the program execution. There is little difference between the interrupt and exception in terms of flow, but the interrupt takes precedence over the exception. The V810 architecture is provided with the interrupts and exceptions listed in the table below. If an exception, a maskable interrupt or NMI occurs, control is transferred to a handler whose address is determined by the source of the interrupt or exception. The exception source can be checked by examining an exception code stored in the ECR (Exception Code Register). Each handler analyzes the contents of the ECR and performs appropriate exception/interrupt servicing. Table 6-1. Exception Codes Classification Exception code Handler address Restore PCNote 1 Reset Interrupt FFF0 FFFFFFF0 Note 2 NMI Interrupt FFD0 FFFFFFD0 next PCNote 3 Duplexed exception Exception Note 4 FFFFFFD0 current PC Address trap Exception FFC0 FFFFFFC0 current PC Trap instruction (parameter is 0x1n) Exception FFBn FFFFFFB0 next PC Trap instruction (parameter is 0x0n) Exception FFAn FFFFFFA0 next PC Invalid instruction code Exception FF90 FFFFFF90 current PC Exception and interrupt Zero division Exception FF80 FFFFFF80 current PC FIV (floating-point invalid operation) Exception FF70 FFFFFF60 current PC FZD (floating-point zero division) Exception FF68 FFFFFF60 current PC FOV (floating-point overflow) Exception FF64 FFFFFF60 current PC FUD (floating-point underflow)Note 5 Exception FF62 FFFFFF60 current PC FPR (floating-point precision degradation)Note 5 Exception FF61 FFFFFF60 current PC FRO (floating-point reserved operand) Exception FF60 FFFFFF60 current PC Interrupt FEn0 FFFFFEn0 next PCNote 3 INT level n (n = 0 to 15) Notes 1. PC to be saved to EIPC or FEPC. 2. EIPC and FEPC are undefined. 3. While an instruction whose execution is aborted by an interrupt (DIV/DIVU, single-precision floatingpoint data, bit string instruction) is executed, restore PC = current PC. 4. The exception code of the exception that occurs for the first time is stored to the lower 16 bits of the ECR, and that of the second exception is stored in the higher 16 bits. 5. In the V810, the floating-point underflow exception and floating-point precision degradation exception do not occur. 22 µPD70732 7. ★ CACHE Figure 7-1 shows the instruction cache configuration provided to the V810. Figure 7-1. Cache Configuration Capacity : 1 Kbytes Mapping system : direct map Block size : 8 bytes Sub-block size : 4 bytes 10 9 31 Memory address Tag memory (ICHT27 to ICHT0) 27 22 21 3 2 Index TAG Data memory (ICHD31 to ICHD0) 0 31 0 Sub-block (4 bytes) Entry 0 0 Offset TAG31 to TAG10 Block (8 bytes) Entry 1 128 entries 128 blocks Entry 127 Valid bits (1 bit for every 4 bytes) NECRV (Reserved by NEC) 23 µPD70732 ★ 8. RESET A low-level input detection on the RESET pin always triggers a system reset. Consequently, all the hardware- controlling registers are initialized as shown in Table 8-1. After the initialization procedure is completed and the RESET pin returns to the high level, the device is released from the resetting state and starts the implementation of a program. Then, if necessary, set some registers to user-desired values in the first stage of the program. Table 8-1. Register State after Reset Hardware (Symbol) State after Reset Program counter PC FFFFFFF0H Status saving register for interrupt EIPC Undefind EIPSW Status saving register for NMI FEPC Undefind FEPSW Interrupt cause register 24 FECC 0000H EICC FFF0H Program status word PSW 00008000H General-purpose register r0 Fixed to 00000000H r1 to r31 Undefind µPD70732 9. ★ INSTRUCTION SET 9.1 Instruction Format The V810 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction are binomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, 16bit immediate, jump & link, and extended operations. Some instructions have an unused field. However, do not write a program that uses this field because it is reserved for future use. This unused field must be set to zeros. Instructions are stored in memory in the following manner. • The lower half of an instruction, that is, the half which includes bit 0, is stored at the lower address. • The higher half of an instruction, that is, the half which includes bit 15 or 31, is stored at the higher address. (1) reg-reg instruction format (Format I) This format consists of one 6-bit field to hold an operation code and two 5-bit fields to specify generalpurpose registers as instruction’s operands. 16-bit instructions use this format. 15 10 9 opcode (2) 5 4 reg2 0 reg1 imm-reg instruction format (Format II) This format consists of one 6-bit field to hold an operation code, one 5-bit field to hold an immediate data, and one field to specify a general-purpose register as an operand. 16-bit instructions use this format. 15 10 9 opcode (3) 5 4 reg2 0 imm Conditonal branch instruction format (Format III) This format consists of one 3-bit field to hold an operation code, one 4-bit field to hold a condition code, and one 9-bit field to hold a branch displacement (with its LSB masked to 0). 16-bit instructions use this format. 15 13 12 opcode 9 8 cond 0 disp 0 25 µPD70732 (4) Intermediate jump instruction format (Format IV) This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (with its LSB masked to 0). 32-bit instructions use this format. 15 10 9 0 31 opcode (5) 16 0 disp 3-operand instruction format (Format V) This format consists of one 6-bit field to hold an operation code, two fields to specify general-purpose registers as operands, and one 16-bit field to hold an immediate data. 32-bit instructions use this format. 15 10 9 opcode (6) 5 4 reg2 0 31 16 reg1 imm Load/store instruction format (Format VI) This format consists of one 6-bit field to hold an operation code, two fields to specify a general-purpose register, and one 16-bit field to hold a displacement. 32-bit instructions use this format. 15 10 9 opcode (7) 5 4 reg2 0 31 16 reg1 disp Extension instruction format (Format VII) This format consists of one 6-bit field to hold an operation code, two 5-bit fields to specify general-purpose registers as operands, and one 6-bit field to hold an sub-operation code. The remaining 10 bits are reserved for future use and must be set to zeros. 32-bit instructions use this format. 15 10 9 opcode 26 5 4 reg2 0 31 reg1 16 sub-opcode RFU µPD70732 9.2 Instruction Mnemonic (in alphabetical order) The list of mnemonics is shown below. This section lists the instructions incorporated in the V810 along with their operations. The instructions are listed in the instruction mnemonic’s alphabetical order to allow users to use this section as a quick reference or dictionary. The conventions used in the list are shown below. Instruction Mnemonic Operand (s) Format ADD reg1, reg2 I Mnemonic of instruction Identifier of operand Instruction format (Refer to 9.1.) CY OV S Z * * Instruction Function Legend * * Flag operation – Remains unchanged * Inverts the previous value 0 Changes to 0 1 Changes to 1 Identifier Description reg1 General-purpose register (Used as a source register) reg2 General-purpose register (Used mainly as a destination register and occasionally as a source register) imm5 5-bit immediate imm16 16-bit immediate disp9 9-bit displacement disp16 16-bit displacement disp26 26-bit displacement regID System register number vector adr Trap handler address that corresponds to a trap vector 27 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (1/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic ADD reg1, reg2 I * * * * Addition: Adds the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. ADD imm5, reg2 II * * * * Addition: Sign-extends the 5-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg2-specified register, then stores the result into the reg2-specified register. ADDF.S reg1, reg2 VII * 0 * * Floating-point addition: Adds the single-precision floating-point data in the reg2-specified register and the single-precision floatingpoint data in the reg1-specified register, then restores the result into the reg2-specified register while changing flags according to the result. ADDI imm16, reg1, reg2 V * * * * Addition: Sign-extends the 16-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. AND reg1, reg2 I – 0 * * AND: Performs the logical AND operation on the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. ANDBSU – II – – – – Transfer after ANDing bit strings: Performs a logical AND operation on a source bit string and a destination bit string, then transfers the result to the destination bit string. ANDI imm16, reg1, reg2 V – 0 0 * AND: Sign-extends the 16-bit immediate data to 32 bits, and performs a logical AND operation on the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. ANDNBSU – II – – – – Transfer after NOTting a bit string then ANDing it with another bit string: Performs a logical AND operation on a destination bit string and the 1’s complement of a source bit string, then transfers the result to the destination bit string. BC disp9 III – – – – Conditional branch (if Carry): PC relative branch BE disp9 III – – – – Conditional branch (if Equal): PC relative branch BGE disp9 III – – – – Conditional branch (if Greater than or Equal): PC relative branch BGT disp9 III – – – – Conditional branch (if Greater than): PC relative branch 28 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (2/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic BH disp9 III – – – – Conditional branch (if Higher): PC relative branch BL disp9 III – – – – Conditional branch (if Lower): PC relative branch BLE disp9 III – – – – Conditional branch (if Less than or Equal): PC relative branch BLT disp9 III – – – – Conditional branch (if Less than): PC relative branch BN disp9 III – – – – Conditional branch (if Negative): PC relative branch BNC disp9 III – – – – Conditional branch (if Not Carry): PC relative branch BNE disp9 III – – – – Conditional branch (if Not Equal): PC relative branch BNH disp9 III – – – – Conditional branch (if Not Higher): PC relative branch BNL disp9 III – – – – Conditional branch (if Not Lower): PC relative branch BNV disp9 III – – – – Conditional branch (if Not Overflow): PC relative branch BNZ disp9 III – – – – Conditional branch (if Not Zero): PC relative branch BP disp9 III – – – – Conditional branch (if Positive): PC relative branch BR disp9 III – – – – Unconditional branch: PC relative branch BV disp9 III – – – – Conditional branch (if Overflow): PC relative branch BZ disp9 III – – – – Conditional branch (if Zero): PC relative branch CAXI disp16 [reg1], reg2 VI * * * * Inter-processor synchronization in a multi-processor system. CMP reg1, reg2 I * * * * Comparison: Subtracts the word data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. CMP imm5, reg2 II * * * * Comparison: Sign-extends the 5-bit immediate data to 32 bits, and subtracts the extended immediate data from the word data in the reg2-specified register for comparison, then changes flags according to the result. CMPF.S reg1, reg2 VII * 0 * * Floating-point comparison: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. 29 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (3/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic CVT.SW reg1, reg2 VII – 0 * * Data conversion from floating-point to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. CVT.WS reg1, reg2 VII * 0 * * Data conversion from integer to floating-point: Converts the integer data in the reg1-specified register into a single-precision floating-point data, then stores the result into the reg2-specified register while changing flags according to the result. DIV reg1, reg2 I – * * * Signed division: Divides the word data in the reg2-specified register by that for reg1 with their sign bits validated, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. DIVF.S reg1, reg2 VII * 0 * * Floating-point division: Divides the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. DIVU reg1, reg2 I – 0 * * Unsigned division: Divides the word data in the reg2-specified register by that for reg1 with their data handled as unsigned data, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. HALT – II – – – – Processor stop IN.B disp16 [reg1], reg2 VI – – – – Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the byte data located at the generated port address, zero-extends the byte data to 32 bits, and stores the result into the reg2-specified register. IN.H disp16 [reg1], reg2 VI – – – – Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the halfword data located at the generated port address while masking the address’s bit 0 to 0, zero-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. 30 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (4/9) Instruction Operand (s) Format disp16 [reg1], reg2 VI CY OV S Z – – Instruction Function Mnemonic IN.W – – Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the word data located at the generated address while masking the address’s bits 0 and 1 to 0, and stores the word into the reg2specified register. JAL disp26 IV – – – – JMP [reg1] I – – – – JR disp26 IV – – – – Jump and link: Increments the current PC by 4, then saves it into r31, and sign-extends the 26-bit displacement to 32 bits while masking the displacement’s bit 0 to 0, adds the extended displacement and the PC value, loads the PC with the addition result, so that the instruction stored at the PC-pointing address is executed next. Register-indirect unconditional branch: Loads the PC with the jump address value in the reg1specified register while masking the value’s bit 0 to 0, so that the instruction stored at the address pointed by the reg1-specified register is executed next. Unconditional branch: Sign-extends the 26-bit displacement to 32 bits while masking bit 0 to 0, adds the result with the current PC value, and loads the PC with the addition result so that the instruction stored at the PC-pointing address is executed next. LD.B disp16 [reg1], reg2 VI – – – – Byte load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate the 32-bit unsigned address, then reads the byte data located at the generated address, sign-extends the byte data to 32 bits, and stores the result into the reg2-specified register. LD.H disp16 [reg1], reg2 VI – – – – Halfword load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking its bit 0 to 0, then reads the halfword data located at the generated address, sign-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. LD.W disp16 [reg1], reg2 VI – – – – Word load: Sign-extends the 16-bit displacement to 32 bits and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking bits 0 and 1 to 0, then reads the word data located at the generated address and stores the data into the reg2-specified register. 31 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (5/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic LDSR reg2, regID II * * * * Loading system register: Transfers the word data in the reg2-specified register to the system register specified with the system register number (regID). MOV reg1, reg2 I – – – – Transferring data: Loads the reg2-specified register with the word data in of the reg1-specified register. MOV imm5, reg2 II – – – – Transferring data: Sign-extends the 5-bit immediate data to 32 bits, then loads the reg2-specified register with the extended immediate data. MOVBSU – II – – – – Transferring bit strings: Loads the destination bit string with the source bit string. MOVEA imm16, reg1, reg2 V – – – – Addition: Sign-extends the 16-bit immediate data to 32 bits, adds it with the word data in the reg1-specified register, then stores the addition result into reg2. MOVHI imm16, reg1, reg2 V – – – – Addition: Appends 16-bit zeros below the 16-bit immediate data to form a 32-bit word data, then adds it with the word data in the reg1-specified register, and stores the result into the reg2-specified register. MUL reg1, reg2 I – * * * Signed multiplication: Signed-multiplies the word data in the reg2-specified register by that for reg1, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. MULF.S reg1, reg2 VII * 0 * * Floating-point multiplication: Multiplies the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. MULU reg1, reg2 I – * * * Unsigned multiplication: Multiplies the word data in the reg2-specified register by that for reg1 while handling these data as unsigned data, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. NOP – III – – – – No operation: Makes no changes or operations while spending one instruction cycle. NOT reg1, reg2 I – 0 * * Logical NOT: Obtains the 1’s complement (logical NOT) of the content of the reg1-specified register, then stores the result into the reg2-specified register. 32 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (6/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic NOTBSU – II – – – – Transfer after NOTting a bit string: Obtains the 1’s complement (all bits inverted) of the source bit string, then transfers the result to the destination bit string. OR reg1, reg2 I – 0 * * OR: Performs a logical OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. ORBSU – II – – – – Transfer after ORing bit strings: Performs a logical OR operation on the source and destination bit strings, then transfers the result to the destination bit string. ORI imm16, reg1, reg2 V – 0 * * OR: Zero-extends the 16-bit immediate data to 32 bits, performs a logical OR operation on the extended data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. ORNBSU – II – – – – Transfer after NOTting a bit string and ORing it with another bit string: Obtains the 1’s complement (logical NOT) of the source bit string, performs a logical OR operation on the NOTted bit string and the destination bit string, then transfers the result to the destination bit string. OUT.B reg2, disp16 [reg1] VI – – – – Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address, then outputs the lowest 8 bits (= 1 byte) of the reg2-specified register onto the port pins corresponding to the generated port address. OUT.H reg2, disp16 [reg1] VI – – – – Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bit 0 masked to 0, then outputs the lowest 16 bits (= 1 halfword) of the reg2-specified register onto the port pins corresponding to the generated port address. OUT.W reg2, disp16 [reg1] VI – – – – Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bits 0 and 1 masked to 0, then outputs the 32 bits (= 1 word) of the reg2-specified register onto the port pins corresponding to the generated port address. 33 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (7/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic RETI – II * * * * Return from a trap or interrupt routine: Reads the restore PC and PSW from the system registers and loads them to the due places to return from a trap or interrupt routine to the original operation flow. SAR reg1, reg2 I * 0 * * Arithmetic right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register’s lowest 5 bits, then stores the result into the reg2-specified register. In arithmetic right shift operations, the MSB is loaded with the LSB value at each shift. SAR imm5, reg2 II * 0 * * Arithmetic right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the extended immediate data, then stores the result into the reg2-specified register. In arithmetic right shift operations, the MSB is loaded with the LSB value at each shift. SCH0BSU SCH0BSD – – II II – – – – – – * * Searching 0s in a bit string: Searches “0” bits in the source bit string, and loads r30 and r27 with the address of the bit next to the first detected “0” bit, then r29 with the number of bits skipped until the first “0” bit is detected, and r28 with the value subtracted by the r29 value. SCH1BSU SCH1BSD – – II II – – – – – – – – Searching 1s in a bit string: Searches 1s in the source bit string, and loads r30 and r27 with the bit address next to the first detected “1” bit, then r29 with the number of bits skipped until the first “1” is detected, and r28 with the value subtracted by the r29 value. SETF imm5, reg2 II – – – – Flag condition setting: Sets the reg2-specified register to 1 if the condition flag value matches the lowest 4 bits of the 5-bit immediate data, and sets the reg2-specified register to 0 when they do not match. SHL reg1, reg2 I * 0 * * Logical left shift: Shifts every bit of the word data in the reg2-specified register to the left by the number of times specified with the reg1-specified register’s lowest 5 bits, then stores the result into the reg2-specified register. In logical left shift operations, the LSB is loaded with 0 at each shift. 34 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (8/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic SHL imm5, reg2 II * 0 * * Logical left shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the left by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. In logical left shift operations, the LSB is loaded with 0 at each shift. SHR reg1, reg2 I * 0 * * Logical right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register’s lowest 5 bits, then stores the result into the reg2-specified register. In logical right shift operations, the MSB is loaded with 0 at each shift. SHR imm5, reg2 II * 0 * * Logical right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. In logical right shift operations, the MSB is loaded with 0 at each shift. ST.B reg2, disp16 [reg1] VI – – – – Byte store: Sign-extends the 16-bit displacement to 32 bits and adds the 32-bit displacement and the content of the reg1-specified register to generate a 32-bit unsigned address, then transfers the reg2-specified register’s lowest 8 bits to the generated address. ST.H reg2, disp16 [reg1] VI – – – – Halfword store: Sign-extends the 16-bit displacement to 32 bits with its bit 0 masked to 0, and adds the content of the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the reg2specified register’s lower 16 bits to the generated address. ST.W reg2, disp16 [reg1] VI – – – – Word store: Sign-extends the 16-bit displacement to 32 bits with its bits 0 and 1 masked to 0, and adds the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the content of the reg1-specified register to the generated address. STSR regID, reg2 II – – – – Storing system register contents: Loads the reg2-specified register with the content of the system register specified by the system register number (regID). SUB reg1, reg2 I * * * * Subtraction: Subtracts the content of the reg1-specified register from the content of the reg2-specified register, then stores the result into the reg2-specified register. 35 µPD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (9/9) Instruction Operand (s) Format CY OV S Z Instruction Function Mnemonic SUBF.S reg1, reg2 VII * 0 * * Floating-point subtraction: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2, then stores the result into the reg2-specified register while changing flags according to the result. TRAP vector II – – – – Software trap: Jumps to a trap handler address according to the vector-specified trap vector (from 0 to 31) to start an exception handling after completing all necessary saving and presetting procedures as follows: (1) Saving the restore PC and PSW into the FEPC and FEPSW system registers, respectively, if the PSW’s EP flag = 1, or into the EIPC and EIPSW system registers, respectively, if EP = 0 (2) Setting an exception code into the ECR’s FECC and FESW flags if the PSW’s EP flag = 1, or into the ECR’s EICC if EP = 0 (3) Setting the PSW’s ID flag and clearing the PSW’s AE flag (4) Setting the PSW’s NP flag if the PSW’s EP flag = 1, or setting the PSW’s ID flag if EP = 0 TRNC.SW reg1, reg2 VII – 0 * * Conversion from floating-point data to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. XOR reg1, reg2 I – 0 * * Exclusive OR: Performs a logical exclusive-OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. XORBSU – II – – – – Transfer of exclusive ORed bit string: Performs a logical exclusive-OR operation on the source and destination bit strings, then transfers the result to the destination bit string. XORI imm16, reg1, reg2 V – 0 * * Exclusive OR: Zero-extends the 16-bit immediate data to 32 bits and performs a logical exclusive-OR operation on the extended immediate data and the word data in the reg2-specified register, then stores the result into the reg2-specified register. XORNBSU – II – – – – Transfer after exclusive-ORing a NOTted bit string and another bit string: Obtains the 1’s complement (NOT) of the source bit string, and exclusive-ORs it with the destination bit string, then transfers the result to the destination bit string. 36 µPD70732 10. ELECTRICAL SPECIFICATIONS Supported Electrical Specifications Operating Supply Operating Ambient Voltage Temperature (TA) VDD = +5 V ± 10% –10 to +70˚C µPD70732-16 µPD70732-20 µPD70732-25 120-pin Plastic QFP (16 MHz) (20 MHz) 120-pin Plastic TQFP 176-pin Ceramic PGA (25 MHz) (25 MHz) (25 MHz) –40 to +85˚C — — (20 MHz) (20 MHz) — VDD = 2.7 to 3.6 V –40 to +85˚C — — (16 MHz) (16 MHz) — VDD = 2.2 to 3.6 V –40 to +85˚C — — (10 MHz) (10 MHz) — Remarks 1. : with electrical specifications — : without electrical specifications 2. ( ) : maximum operating frequency 37 ★ µPD70732 10.1 Specifications When VDD = +5 V ± 10% (1) TA = –10 to +70˚C Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Test Conditions Rating Unit –0.5 to +7.0 V Supply voltage VDD Input voltage VI VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Clock Input voltage VK VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Output voltage VO VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Operating ambient temperature TA –10 to +70 ˚C Storage temperature Tstg –65 to +150 ˚C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = –10 to +70˚C, VDD = +5V ± 10%) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock input voltage, high VKH 4.0 VDD + 0.3 V Clock input voltage, low VKL –0.5 +0.6 V Input voltage, high VIH 2.2 VDD + 0.3 V Input voltage, low VIL –0.5 +0.8 V Output voltage, high VOH IOH = –400 µA Output voltage, low VOL IOL = 3.2 mA Input leak current, high ILIH Input leak current, low 2.4 V 0.45 V VIN = VDD 10 µA ILIL VIN = 0 V –10 µA Output leak current, high ILOH VO = VDD 10 µA Output leak current, low ILOL VO = 0 V –10 µA Supply current IDD f = 16 MHz 64Note 2 160 f = 20 MHz 80Note 2 200 f = 25 MHz Stopping clock 100 Note 1 Note 2 240 5 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark 38 mA Operating supply current is approximately proportional to operating clock frequency. µA µPD70732 Capacitance (TA = 25˚C, VDD = +5 V ± 10%) Parameter Symbol Input capacitance CI I/O capacitance CIO Test Conditions MIN. fC = 1 MHz MAX. Unit 15 pF 15 pF AC Characteristics (TA = –10 to +70˚C, VDD = +5V ± 10%) Clock Input Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MIN. MIN. MAX. MAX. Unit MAX. Clock cycle tCYK 62.5 50 40 ns Clock pulse high-level width tKKH 26 21 17 ns Clock pulse low-level width tKKL 26 21 17 ns Clock rise time tKR 5 4 3 ns Clock fall time tKF 5 4 3 ns Reset Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MIN. MIN. MAX. MAX. 1000 + 20 tCYKR Unit MAX. RESET hold time (from VDD VALID) tHVR 1000 + 20 tCYKR Clock cycle (at reset) tCYKR 62.5 Clock high-level time (at reset) tKKHR 26 21 17 ns Clock low-level time (at reset) tKKLR 26 21 17 ns RESET setup time (to CLK↓, active) tSRKF 10 10 10 ns RESET setup time (to CLK↓, inactive) tSRKR 10 10 10 ns RESET hold time (from CLK↓) tHKR 10 10 10 ns RESET pulse low-level width (to CLK↓) tWRL 20 tCYKR 20 tCYKR 20 tCYKR ns 1000 50 1000 + 20 tCYKR 1000 40 ns 1000 ns 39 µPD70732 Memory, I/O Access Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MAX. MIN. MAX. MIN. MAX. Unit Address, etc. output delay time (from CLK↑) tDKA 2 20 2 15 2 15 ns Address, etc. ouput hold time (from CLK↑) tHKA 2 20 2 15 2 15 ns BCYST output delay time (from CLK↑) tDKBC 2 20 2 15 2 15 ns BCYST output hold time (from CLK↑) tHKBC 2 20 2 15 2 15 ns DA output delay time (from CLK↑) tDKDA 2 20 2 15 2 15 ns DA output hold time (from CLK↑) tHKDA 2 20 2 15 2 15 ns READY setup time (to CLK↓) tSRYK 6 5 4 ns READY hold time (from CLK↓) tHKRY 5 5 4 ns Data setup time (to CLK↑) tSDK 6 5 4 ns Data hold time (from CLK↑) tHKD 5 5 4 ns Data output delay time tDKDT 2 20 2 15 2 15 ns Data output hold time (to active, from CLK↓) tHKDT 2 20 2 15 2 15 ns Data output delay time (from float, from CLK↓) tLZKDT 5 25 5 20 5 20 ns Data output hold time tHZKDT 5 25 5 20 5 20 ns (from active, from CLK↓) (to float, from CLK↓) Dynamic Bus Sizing Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MIN. MIN. MAX. MAX. Unit MAX. SZRQ setup time (to CLK↓) tSSZK 6 5 4 ns SZRQ hold time (from CLK↓) tHKSZ 5 5 4 ns Interrupt Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MIN. MIN. MAX. MAX. Unit MAX. NMI setup time (to CLK↓) tSNK 6 5 4 ns NMI hold time (from CLK↓) tHKN 5 5 4 ns INT, etc. setup time (to CLK↑) tSIK 6 5 4 ns INT, etc. hold time (from CLK↑) tHKI 5 5 4 ns 40 µPD70732 Bus Hold Parameter Symbol Test Conditions µPD70732-16 µPD70732-20 µPD70732-25 MIN. MIN. MIN. MAX. MAX. Unit MAX. HLDRQ setup time (to CLK↓) tSHQK 6 5 4 ns HLDRQ hold time (from CLK↓) tHKHQ 5 5 4 ns HLDAK output delay time (from CLK↑) tDKHA 2 20 2 15 2 15 ns HLDAK output hold time (from CLK↑) tHKHA 2 20 2 15 2 15 ns Address, etc. delay time (from active, from CLK↑) tHZKA 2 25 2 20 2 20 ns Address, etc. delay time (from float, from CLK↑) tLZKA 2 25 2 20 2 20 ns Data delay time (from active, from CLK↓) tHZKD 5 25 5 20 5 20 ns Data delay time (from float, from CLK↓) tLZKD 5 25 5 20 5 20 ns BCYST delay time (from active, from CLK↑) tHZKBC 2 25 2 20 2 20 ns BCYST delay time tLZKBC 2 25 2 20 2 20 ns tHZKDA 2 25 2 20 2 20 ns tLZKDA 2 25 2 20 2 20 ns (from float, from CLK↑) DA delay time (from active, from CLK↑) DA delay time (from float, from CLK↑) AC Test Input Waveform (Except CLK) 2.2 V Test points 2.2 V 0.8 V 0.8 V AC Test Input Waveform (CLK) 4.0 V 3.0 V Test points 1.7 V 0.6 V 3.0 V 1.7 V tKF tKR AC Test Output Test Points 2.4 V 0.45 V Test points 2.4 V 0.45 V 41 µPD70732 Load Conditions V810 output pin CL = 100 pF 42 µPD70732 (2) TA = –40 to +85˚C Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Test Conditions Rating Unit –0.5 to +7.0 V Supply voltage VDD Input voltage VI VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Clock Input voltage VK VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Output voltage VO VDD = +5 V ± 10% –0.5 to VDD + 0.3 V Operating ambient temperature TA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = –40 to +85˚C, VDD = +5V ± 10%) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock input voltage, high VKH 4.0 VDD + 0.3 V Clock input voltage, low VKL –0.5 +0.6 V Input voltage, high VIH 2.2 VDD + 0.3 V Input voltage, low VIL –0.5 +0.8 V Output voltage, high VOH IOH = –400 µA Output voltage, low VOL IOL = 3.2 mA Input leak current, high ILIH Input leak current, low 2.4 V 0.45 V VIN = VDD 10 µA ILIL VIN = 0 V –10 µA Output leak current, high ILOH VO = VDD 10 µA Output leak current, low ILOL VO = 0 V –10 µA 200 mA Supply current IDD f = 20 MHz Stopping clock 80 Note 1 Note 2 5 µA Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 43 µPD70732 Capacitance (TA = 25˚C, VDD = +5 V ± 10%) Parameter Symbol Input capacitance CI I/O capacitance CIO Test Conditions MIN. fC = 1 MHz MAX. Unit 15 pF 15 pF AC Characteristics (TA = –40 to +85˚C, VDD = +5V ± 10%) Clock Input Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. Clock cycle tCYK 50 ns Clock pulse high-level width tKKH 21 ns Clock pulse low-level width tKKL 21 ns Clock rise time tKR 4 ns Clock fall time tKF 4 ns Reset Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. RESET hold time (from VDD VALID) tHVR 1000 + 20 tCYKR Clock cycle (at reset) tCYKR 50 Clock high-level time (at reset) tKKHR 21 ns Clock low-level time (at reset) tKKLR 21 ns RESET setup time (to CLK↓, active) tSRKF 10 ns RESET setup time (to CLK↓, inactive) tSRKR 10 ns RESET hold time (from CLK↓) tHKR 10 ns RESET pulse low-level width (to CLK↓) tWRL 20 tCYKR ns 44 ns 1000 ns µPD70732 Memory, I/O Access Parameter Symbol µPD70732-25 Test Conditions Unit MIN. MAX. Address, etc. ouput delay time (from CLK↑) tDKA 1 15 ns Address, etc. ouput hold time (from CLK↑) tHKA 1 15 ns BCYST output delay time (from CLK↑) tDKBC 1 15 ns BCYST output hold time (from CLK↑) tHKBC 1 15 ns DA output delay time (from CLK↑) tDKDA 1 15 ns DA output hold time (from CLK↑) tHKDA 1 15 ns READY setup time (to CLK↓) tSRYK 5 ns READY hold time (from CLK↓) tHKRY 5 ns Data setup time (to CLK↑) tSDK 5 ns Data hold time (from CLK↑) tHKD 5 ns Data output delay time (from active, from CLK↓) tDKDT 1 15 ns Data output hold time (to active, from CLK↓) tHKDT 1 15 ns Data output delay time (from float, from CLK↓) tLZKDT 5 20 ns Data output hold time (to float, from CLK↓) tHZKDT 5 20 ns Dynamic Bus Sizing Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. SZRQ setup time (to CLK↓) tSSZK 5 ns SZRQ hold time (from CLK↓) tHKSZ 5 ns Interrupt Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. NMI setup time (to CLK↓) tSNK 5 ns NMI hold time (from CLK↓) tHKN 5 ns INT, etc. setup time (to CLK↑) tSIK 5 ns INT, etc. hold time (from CLK↑) tHKI 5 ns 45 µPD70732 Bus Hold Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. HLDRQ setup time (to CLK↓) tSHQK 5 ns HLDRQ hold time (from CLK↓) tHKHQ 5 ns HLDAK output delay time (from CLK↑) tDKHA 1 15 ns HLDAK output hold time (from CLK↑) tHKHA 1 15 ns Address, etc. delay time (from active, from CLK↑) tHZKA 2 20 ns Address, etc. delay time (from float, from CLK↑) tLZKA 2 20 ns Data delay time (from active, from CLK↓) tHZKD 5 20 ns Data delay time (from float, from CLK↓) tLZKD 5 20 ns BCYST delay time (from active, from CLK↑) tHZKBC 2 20 ns BCYST delay time (from float, from CLK↑) tLZKBC 2 20 ns DA delay time (from active, from CLK↑) tHZKDA 2 20 ns DA delay time (from float, from CLK↑) tLZKDA 2 20 ns AC Test Input Waveform (Except CLK) 2.2 V Test points 2.2 V 0.8 V 0.8 V AC Test Input Waveform (CLK) 4.0 V 3.0 V 3.0 V Test points 1.7 V 1.7 V 0.6 V tKR tKF AC Test Output Test Points 2.4 V Test points 0.45 V 0.45 V Load Conditions V810 output pin CL = 100 pF 46 2.4 V µPD70732 10.2 Specifications When VDD = 2.7 to 3.6 V Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Test Conditions Rating Unit –0.5 to +7.0 V Supply voltage VDD Input voltage VI VDD = 2.7 to 3.6 V –0.5 to VDD + 0.3 V Clock Input voltage VK VDD = 2.7 to 3.6 V –0.5 to VDD + 0.3 V Output voltage VO VDD = 2.7 to 3.6 V –0.5 to VDD + 0.3 V Operaitng ambient temperature TA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = –40 to +85˚C, VDD = 2.7 to 3.6 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock input voltage, high VKH 0.8 VDD VDD + 0.3 V Clock input voltage, low VKL –0.5 +0.2 VDD V Input voltage, high VIH 2.0 VDD + 0.3 V Input voltage, low VIL –0.5 +0.6 V Output voltage, high VOH IOH = –2.0 mA 0.85 VDD V IOH = –100 µA VDD – 0.2 V Output voltage, low VOL IOL = 3.2 mA 0.4 V Input leak current, high ILIH VIN = VDD 5 µA Input leak current, low ILIL VIN = 0 V –5 µA Output leak current, high ILOH VO = VDD 5 µA Output leak current, low ILOL VO = 0 V –5 µA 100 mA 30 µA Supply current IDD f = 16 MHz Stopping clockNote 1 38 Note 2 3 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 47 µPD70732 Capacitance (TA = 25˚C, VDD = 2.7 to 3.6 V) Parameter Symbol Input capacitance CI I/O capacitance CIO Test Conditions MIN. fC = 1 MHz MAX. Unit 15 pF 15 pF AC Characteristics (TA = –40 to +85˚C, VDD = 2.7 to 3.6 V) Clock Input Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. Clock cycle tCYK 62.5 ns Clock pulse high-level width tKKH 26 ns Clock pulse low-level width tKKL 26 ns Clock rise time tKR 5 ns Clock fall time tKF 5 ns Reset Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. RESET hold time (from VDD VALID) tHVR 1000 + 20tCYKR Clock cycle (at reset) tCYKR 62.5 Clock high-level time (at reset) tKKHR 26 ns Clock low-level time (at reset) tKKLR 26 ns RESET setup time (to CLK↓, active) tSRKF 10 ns RESET setup time (to CLK↓, inactive) tSRKR 10 ns RESET hold time (from CLK↓) tHKR 10 ns RESET pulse low-level width (to CLK↓) tWRL 20tCYKR ns 48 ns 1000 ns µPD70732 Memory, I/O Access Parameter Symbol µPD70732-25 Test Conditions Unit MIN. MAX. Address etc. output delay time (from CLK↑) tDKA 1 25 ns Address etc. output hold time (from CLK↑) tHKA 1 25 ns BCYST output delay time (from CLK↑) tDKBC 1 25 ns BCYST output hold time (from CLK↑) tHKBC 1 25 ns DA output delay time (from CLK↑) tDKDA 1 25 ns DA output hold time (from CLK↑) tHKDA 1 25 ns READY setup time (to CLK↓) tSRYK 8 ns READY hold time (from CLK↓) tHKRY 5 ns Data setup time (to CLK↑) tSDK 8 ns Data hold time (from CLK↑) tHKD 5 ns Data output delay time (from active, from CLK↓) tDKDT 1 35 ns Data output hold time (to active, from CLK↓) tHKDT 1 35 ns Data output delay time (from float, from CLK↓) tLZKDT 3 40 ns Data output hold time (to float, from CLK↓) tHZKDT 3 40 ns Dynamic Bus Sizing Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. SZRQ setup time (to CLK↓) tSSZK 8 ns SZRQ hold time (from CLK↓) tHKSZ 5 ns Interrupt Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. NMI setup time (to CLK↓) tSNK 8 ns NMI hold time (from CLK↓) tHKN 5 ns INT etc. setup time (to CLK↑) tSIK 8 ns INT etc. hold time (from CLK↑) tHKI 5 ns 49 µPD70732 Bus Hold Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. HLDRQ setup time (to CLK↓) tSHQK 8 ns HLDRQ hold time (from CLK↓) tHKHQ 5 ns HLDAK output delay time (from CLK↑) tDKHA 1 25 ns HLDAK output hold time (from CLK↑) tHKHA 1 25 ns Address, etc. delay time (from active, from CLK↑) tHZKA 3 30 ns Address, etc. delay time (from float, from CLK↑) tLZKA 3 30 ns Data delay time (from active, from CLK↓) tHZKD 3 40 ns Data delay time (from float, from CLK↓) tLZKD 3 40 ns BCYST delay time (from active, from CLK↑) tHZKBC 3 30 ns BCYST delay time (from float, from CLK↑) tLZKBC 3 30 ns DA delay time (from active, from CLK↑) tHZKDA 3 30 ns DA delay time (from float, from CLK↑) tLZKDA 3 30 ns AC Test Input Waveform (Except CLK) 2.0 V Test points 2.0 V 0.6 V 0.6 V AC Test Input Waveform (CLK) 0.8 VDD 0.7 VDD Test points 0.3 VDD 0.2 VDD 0.7 VDD 0.3 VDD tKF tKR AC Test Output Test Points 0.85 VDD 0.4 V Test points 0.85 VDD 0.4 V Load Conditions V810 output pin CL = 100 pF 50 µPD70732 10.3 Specifications When VDD = 2.2 to 3.6 V Absolute Maximum Ratings (TA = 25˚C) Parameter Symbol Test Conditions Rating Unit –0.5 to +7.0 V Supply voltage VDD Input voltage VI VDD = 2.2 to 3.6 V –0.5 to VDD + 0.3 V Clock Input voltage VK VDD = 2.2 to 3.6 V –0.5 to VDD + 0.3 V Output voltage VO VDD = 2.2 to 3.6 V –0.5 to VDD + 0.3 V Operaitng ambient temperature TA –40 to +85 ˚C Storage temperature Tstg –65 to +150 ˚C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = –40 to +85˚C, VDD = 2.2 to 3.6 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Clock input voltage, high VKH 0.8 VDD VDD + 0.3 V Clock input voltage, low VKL –0.5 +0.2 VDD V Input voltage, high VIH VDD ≥ 2.5 V 2.0 VDD + 0.3 V VDD ≤ 2.5 V 0.8 VDD VDD + 0.3 V –0.5 +0.2 VDD V Input voltage, low VIL Output voltage, high VOH IOH = –2.0 mA 0.85 VDD V IOH = –100 µA VDD – 0.2 V Output voltage, low VOL IOL = 3.2 mA 0.4 V Input leak current, high ILIH VIN = VDD 5 µA Input leak current, low ILIL VIN = 0 V –5 µA Output leak current, high ILOH VO = VDD 5 µA Output leak current, low ILOL VO = 0 V –5 µA Supply current IDD f = 10 MHz 24Note 2 70 mA 3 30 µA Stopping clockNote 1 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 51 µPD70732 Capacitance (TA = 25˚C, VDD = 2.2 to 3.6 V) Parameter Symbol Input capacitance CI I/O capacitance CIO Test Conditions MIN. fC = 1 MHz MAX. Unit 15 pF 15 pF AC Characteristics (TA = –40 to +85˚C, VDD = 2.2 to 3.6 V) Clock Input Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. Clock cycle tCYK 100 ns Clock pulse high-level width tKKH 40 ns Clock pulse low-level width tKKL 40 ns Clock rise time tKR 10 ns Clock fall time tKF 10 ns Reset Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. RESET hold time (from VDD VALID) tHVR 1000 + 20tCYKR Clock cycle (at reset) tCYKR 100 Clock high-level time (at reset) tKKHR 40 ns Clock low-level time (at reset) tKKLR 40 ns RESET setup time (to CLK↓, active) tSRKF 10 ns RESET setup time (to CLK↓, inactive) tSRKR 10 ns RESET hold time (from CLK↓) tHKR 15 ns RESET pulse low-level width (to CLK↓) tWRL 20tCYKR ns 52 ns 1000 ns µPD70732 Memory, I/O Access Parameter Symbol µPD70732-25 Test Conditions Unit MIN. MAX. tDKA 1 35 ns Address, etc. output hold time (from CLK↑) tHKA 1 35 ns BCYST output delay time (from CLK↑) tDKBC 1 35 ns BCYST output hold time (from CLK↑) tHKBC 1 35 ns DA output delay time (from CLK↑) tDKDA 1 35 ns DA output hold time (from CLK↑) tHKDA 1 35 ns READY setup time (to CLK↓) tSRYK 15 ns READY hold time (from CLK↓) tHKRY 5 ns Data setup time (to CLK↑) tSDK 15 ns Data hold time (from CLK↑) tHKD 5 ns Data output delay time (from active, from CLK↓) tDKDT 1 50 ns Data output hold time (to active, from CLK↓) tHKDT 1 50 ns Data output delay time (from float, from CLK↓) tLZKDT 3 50 ns Data output hold time (to float, from CLK↓) tHZKDT 3 50 ns Address, etc. output delay time (from CLK↑) Dynamic Bus Sizing Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. SZRQ setup time (to CLK↓) tSSZK 15 ns SZRQ hold time (from CLK↓) tHKSZ 5 ns Interrupt Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. NMI setup time (to CLK↓) tSNK 15 ns NMI hold time (from CLK↓) tHKN 5 ns INT, etc. setup time (to CLK↑) tSIK 15 ns INT, etc. hold time (from CLK↑) tHKI 5 ns 53 µPD70732 Bus Hold Parameter Symbol µPD70732-25 Test Conditions MIN. Unit MAX. HLDRQ setup time (to CLK↓) tSHQK 15 ns HLDRQ hold time (from CLK↓) tHKHQ 5 ns HLDAK output delay time (from CLK↑) tDKHA 1 35 ns HLDAK output hold time (from CLK↑) tHKHA 1 35 ns Address, etc. delay time (from active, from CLK↑) tHZKA 3 35 ns Address, etc. delay time (from float, from CLK↑) tLZKA 3 35 ns Data delay time (from active, from CLK↓) tHZKD 3 50 ns Data delay time (from float, from CLK↓) tLZKD 3 50 ns BCYST delay time (from active, from CLK↑) tHZKBC 3 35 ns BCYST delay time (from float, from CLK↑) tLZKBC 3 35 ns DA delay time (from active, from CLK↑) tHZKDA 3 35 ns DA delay time (from float, from CLK↑) tLZKDA 3 35 ns AC Test Input Waveform (Except CLK) 0.8 VDD Test points 0.2 VDD 0.8 VDD 0.2 VDD AC Test Input Waveform (CLK) 0.8 VDD 0.7 VDD Test points 0.3 VDD 0.2 VDD 0.7 VDD 0.3 VDD tKF tKR AC Test Output Test Points 0.85 VDD 0.4 V Test points 0.85 VDD 0.4 V Load Conditions V810 output pin CL = 100 pF 54 µPD70732 Clock Timing tCYK tKF tKKH tKR CLK tKKL Reset Timing 0.9 VDD VDD tHVR tCYKR tKKHR tKKLR CLK tWRL tSRKF RESET tHKR tSRKR Clock stopping exception period 55 µPD70732 Memory, I/O Access Timing T1 T2 T2 CLK tDKA tHKA Note tDKBC tHKBC tHKDA tDKDA BCYST tHKDA DA tSRYK tHKRY tSRYK tHKRY READY tSDK tHKD Hi-Z D31 to D0 (Read) tLZKDT D31 to D0 (Write) Hi-Z D31 to D0 (Write) 56 tHZKDT Hi-Z tDKDT Note Hi-Z A31 to A1, BE3 to BE0, R/W, MRQ, ST1, ST0, BLOCK, ADRSERR tHKDT µPD70732 Dynamic Bus Sizing Timing T2 CLK tSSZK tHKSZ SZRQ Interrupt Timing CLK tSNK tHKN NMI tSIK tHKI INT, INTV3 to INTV0 57 58 Bus Hold Timing T1 T2 TI TH TH TH TI T1 CLK tSHQK tHKHQ tSHQK HLDRQ tHKHA tDKHA HLDAK tLZKA tHZKA Note 2 Note 1 tLZKD tHZKD Note 2 D31 to D0 (Write) tHZKBC tLZKBC tHZKDA tLZKDA BCYST DA 2. The level immediately before the high-impedance state has been stored internally. Remark A dashed line indicates high impedance. µPD70732 Notes 1. A31 to A1, BE3 to BE0, R/W, MRQ, ST1, ST0 µPD70732 11. PACKAGE DRAWINGS 120-pin plastic QFP (28 x 28) A B 90 61 91 60 F 120 1 G R Q S D C detail of lead end 31 30 J H I M M P K N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM MILLIMETERS INCHES A 32.0±0.3 1.260±0.012 B 28.0±0.2 1.102 +0.009 –0.008 C 28.0±0.2 1.102 +0.009 –0.008 D 32.0±0.3 1.260±0.012 F 2.4 0.094 G 2.4 0.094 H 0.35±0.10 0.014 +0.004 –0.005 I 0.15 0.006 J 0.8 (T.P.) 0.031 (T.P.) K 2.0±0.2 0.079 +0.009 –0.008 L 0.8±0.2 0.031 +0.009 –0.008 M 0.15 +0.10 –0.05 0.006 +0.004 –0.003 N 0.1 0.004 P 3.2 0.126 Q 0.1±0.1 0.004±0.004 R 5°±5° 5°±5° S 3.5 MAX. 0.138 MAX. P120GD-80-LBB, MBB-1 59 µPD70732 120-pin plastic TQFP (Fine pitch) (14 x 14) A B 90 91 61 60 F 120 1 G 3° +7° –3° Q S D C detail of lead end 31 30 H I M J K M P ★ N L S120GC-40-9EV NOTE Each lead centerline is located within 0.09 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 60 ITEM MILLIMETERS INCHES A 16.0 ±0.2 0.630 ±0.008 B 14.0 ±0.2 0.551 +0.009 –0.008 C 14.0 ±0.2 0.551 +0.009 –0.008 D 16.0 ±0.2 0.630 ±0.008 F 1.2 0.047 G 1.2 0.047 H 0.18 ±0.05 0.007 ±0.002 I 0.09 0.004 J 0.4 (T.P.) 0.016 (T.P.) K 1.0 ±0.2 0.039 +0.009 –0.008 L 0.5 ±0.2 0.020 +0.008 –0.009 M 0.145 ±0.05 0.006 +0.002 –0.003 N 0.08 0.003 P 1.0 ±0.1 0.039 +0.005 –0.004 Q 0.1 ±0.05 0.004 ±0.002 S 1.2 MAX. 0.048 MAX. µPD70732 176-pin ceramic PGA (Seamweld) A (Bottom View) D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Q P N M L K J H G F E D C B A I Orientation pin H G J Index mark K L F E φM M NOTE Each lead centerline is located within φ 0.5 mm (φ 0.020 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 38.1±0.4 1.500 +0.016 –0.015 D 38.1±0.4 1.500 +0.016 –0.015 E 1.27 0.050 F 2.54 (T.P.) 0.100 (T.P.) G 2.8±0.3 0.110 +0.012 –0.011 H 0.5 MIN. 0.019 MIN. I 2.81 0.111 J 4.57 MAX. 0.180 MAX. K φ 1.2±0.2 φ 0.047 +0.008 –0.007 L φ 0.46±0.05 φ 0.018 +0.002 –0.001 M 0.5 0.020 X176R-100A-1 61 µPD70732 12. RECOMMENDED SOLDERING CONDITIONS The µPD70732 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions (1) µPD70732GD-16-LBB : 120-pin plastic QFP (28 x 28 mm) µPD70732GD-20-LBB : 120-pin plastic QFP (28 x 28 mm) µPD70732GD-25-LBB : 120-pin plastic QFP (28 x 28 mm) E specification model only Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. Max. (at 210°C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 36 hours prebaking required at 125°C) IR35-367-2 VPS Package peak temperature: 215°C, Duration: 40 sec. Max. (at 200°C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 36 hours prebaking required at 125°C) VP15-367-2 Wave soldering Solder bath temperature: 260°C Max., Duration: 10 sec. Max., Number of times: Once, Time limit: 7 days Note (thereafter 36 hours prebaking required at 125°C), Preliminary heat temperature: 120°C Max. (Package surface temperature) WS60-367-1 Partial heating Pin temperature: 300°C Max., Duration: 3 sec. Max. (per device side) Note For the storage period after dry-pack decapsulation, storage conditions are Max. 25°C, 65% RH. Caution 62 — Use of more than one soldering method should be avoided (except for partial heating). µPD70732 (2) µPD70732GC-25-9EV: 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) Soldering Method Soldering Conditions ★ Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Duration: 30 sec. Max. (at 210°C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 10 hours prebaking required at 125°C) IR35-107-2 VPS Package peak temperature: 215°C, Duration: 40 sec. Max. (at 200°C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 10 hours prebaking required at 125°C) VP15-107-2 Partial heating Pin temperature: 300°C Max., Duration: 3 sec. Max. (per device side) Note — For the storage period after dry-pack decapsulation, storage conditions are Max. 25°C, 65% RH. Caution Use of more than one soldering method should be avoided (except for partial heating). Table 12-2. Insertion Type Soldering Conditions µPD70732R-25: 176-pin ceramic PGA (Seam weld) Soldering Method Wave soldering Soldering Conditions Solder bath temperature: 260°C Max., Duration: 10 sec. Max. (Pin only) Partial heating Caution Pin temperature: 300°C Max., Duration: 3 sec. Max. (per one pin) Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. 63 µPD70732 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 64 µPD70732 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 65 µPD70732 Reference: Electrical Characteristics for Microcomputer (IEI-601) The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V805, V810, and V810 Family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5