NEC UPD703130GC-8EU

PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703130
V850E/MS2TM
32-BIT SINGLE-CHIP MICROCONTROLLER
TM
The µPD703130 is a member of the V850 Family
control operations.
of 32-bit single-chip microcontrollers designed for real-time
These microcontrollers provide on-chip features, including a 32-bit CPU, RAM, interrupt
controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
The µPD703130 is a ROMless version product.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS2 User’s Manual Hardware:
V850E/MS1
TM
U14985E
User’s Manual Architecture: U12197E
FEATURES
• Number of instructions: 81
• Minimum instruction execution time 30 ns (@ 33 MHz operation)
• General-purpose registers 32 bits × 32
• Instruction set suitable for control applications
• Internal memory ROM: None
RAM: 4 KB
• Advanced on-chip interrupt controller
• Real-time pulse unit suitable for control operations
• Powerful serial interface (on-chip dedicated baud rate generator)
• On-chip clock generator
• 10-bit resolution A/D converter: 4 channels
• DMA controller: 4 channels
• Power saving functions
APPLICATIONS
• Optical storage equipment (DVD players, etc.)
• System control for digital consumer equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15390EJ1V0DS00 (1st edition)
Date Published April 2001 N CP(K)
Printed in Japan
©
2001
µPD703130
ORDERING INFORMATION
Part Number
µPD703130GC-8EU
Package
Maximum Operating
Frequency
100-pin plastic LQFP (fine pitch) (14 × 14)
33 MHz
Internal ROM
None
PIN CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch) (14 × 14)
D1
D0
VDD
INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04
TCLR10/P02
TO100/P00
VSS
INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14
TCLR11/P12
TO110/P10
TCLR12/P102
TO120/P100
ANI3/P73
ANI2/P72
ANI1/P71
ANI0/P70
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NMI/P20
TXD0/SO0/P22
RXD0/SI0/P23
SCK0/P24
TXD1/SO1/P25
RXD1/SI1/P26
SCK1/P27
VDD
INTP130/P34
TI13/P33
CVDD
X2
X1
CVSS
CKSEL
MODE0
MODE2
RESET
VSS
CLKOUT/PX7
WAIT/PX6
HLDRQ/P97
HLDAK/P96
OE/P95
BCYST/P94
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
AVDD
AVSS
AVREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
D2
D3
D4
D5
D6
D7
VSS
D8/P50
D9/P51
D10/P52
D11/P53
D12/P54
D13/P55
D14/P56
D15/P57
HVDD
A0
A1
A2
A3
A4
A5
A6
A7
VSS
• µPD703130GC-8EU
2
Preliminary Data Sheet U15390EJ1V0DS
A8
A9
A10
A11
A12
A13
A14
A15
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
HVDD
CS0/P80
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
WE/P93
µPD703130
PIN NAMES
A0 to A23:
Address bus
P20, P22 to P27:
Port 2
ANI0 to ANI3:
Analog input
P33, P34:
Port 3
AVDD:
Analog power supply
P50 to P57:
Port 5
AVREF:
Analog reference voltage
P60 to P67:
Port 6
AVSS:
Analog ground
P70 to P73:
Port 7
BCYST:
Bus cycle start timing
P80, P83 to P85:
Port 8
CKSEL:
Clock generator operating mode select
P90 to P97:
Port 9
CLKOUT:
Clock output
P100, P102:
Port 10
CS0, CS3 to CS5:
Chip select
PX6, PX7:
Port X
CVDD:
Clock generator power supply
RAS3 to RAS5:
Row address strobe
CVSS:
Clock generator ground
RD:
Read
D0 to D15:
Data bus
RESET:
Reset
DMAAK0 to DMAAK3:
DMA acknowledge
RXD0, RXD1:
Receive data
DMARQ0 to DMARQ3: DMA request
SCK0, SCK1:
Serial clock
HLDAK:
Hold acknowledge
SI0, SI1:
Serial input
HLDRQ:
Hold request
SO0, SO1:
Serial output
HVDD:
Power supply for external pins
TCLR10 to TCLR12: Timer clear
INTP100 to INTP103, : Interrupt request from peripherals
TI13:
Timer input
INTP110 to INTP113,
TO100, TO110:
Timer output
INTP130
TO120
IORD:
I/O read strobe
TXD0, TXD1:
Transmit data
IOWR:
I/O write strobe
UCAS:
Upper column address strobe
LCAS:
Lower column address strobe
UWR:
Upper write strobe
LWR:
Lower write strobe
VDD:
Power supply for internal unit
MODE0, MODE2:
Mode
VSS:
Ground
NMI:
Non-maskable interrupt request
WAIT:
Wait
OE:
Output enable
WE:
Write enable
X1, X2:
Crystal
P00, P02, P04 to P07: Port 0
P10, P12, P14 to P17: Port 1
Preliminary Data Sheet U15390EJ1V0DS
3
µPD703130
INTERNAL BLOCK DIAGRAM
BCU
CPU
NMI
INTP100 to INTP103
INTP110 to INTP113
INTP130
INTC
Instruction
queue
Multiplier
(32 × 32→64)
DRAMC
PC
TO100,TO110,
TO120
Barrel
shifter
System
registers
RPU
TCLR10 to TCLR12
TI13
RAM
4 KB
General-purpose
registers
(32 bits × 32)
PageROM
controller
ALU
DMAC
SIO
SO0/TXD0
SI0/RXD0
SCK0
HLDRQ
HLDAK
CS0,CS3 to CS5
RAS3 to RAS5
IOWR
IORD
BCYST
WE
RD
OE
UWR/UCAS
LWR/LCAS
WAIT
A0 to A23
D0 to D15
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
UART0/CSI0
BRG0
UART1/CSI1
BRG1
ANI0 to ANI3
AVREF
AVSS
AVDD
ADC
Port
CG
PX6,PX7
P100,P102
P90 to P97
P80,P83 to P85
P70 to P73
P60 to P67
P50 to P57
P33,P34
P22 to P27
P20
P10,P12,P14 to P17
P00,P02,P04 to P07
HVDD
SO1/TXD1
SI1/RXD1
SCK1
System
controller
CKSEL
CLKOUT
X1
X2
CVDD
CVSS
MODE0,MODE2
RESET
VDD
VSS
4
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
CONTENTS
1.
DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1............................................................
2.
PIN
2.1
2.2
2.3
FUNCTIONS .............................................................................................................................
Port Pins .................................................................................................................................
Non-Port Pins .........................................................................................................................
Pin I/O Circuits and Recommended Connection of Unused Pins.....................................
7
7
9
11
3.
ELECTRICAL SPECIFICATIONS ...................................................................................................
14
4.
PACKAGE DRAWING .....................................................................................................................
68
5.
RECOMMENDED SOLDERING CONDITIONS .............................................................................
69
Preliminary Data Sheet U15390EJ1V0DS
6
5
µPD703130
1. DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1
Product Name
V850E/MS2
µPD703130
Item
Internal ROM
Maximum
operating
frequency
6
None
V850E/MS1
µPD703100-33
None
33 MHz
µPD703102-33
128 KB (mask ROM)
33 MHz
Memory space
64 MB linear (only 22 MB supports on-chip
CS signal)
64 MB linear
Chip select output
4 spaces
8 spaces
Interrupt function
External: 10, internal: 35
External: 25, internal: 47
I/O lines
Input: 5, I/O: 52
Input: 9, I/O: 114
Timer
16-bit timer/event counter: 4 channels
16-bit timer: 2 channels
16-bit timer/event counter: 6 channels
16-bit timer: 2 channels
Serial interface
CSI/UART: 2 channels
Dedicated baud rate generator: 2 channels
CSI: 2 channels
CSI/UART: 2 channels
Dedicated baud rate generator: 3 channels
A/D converter
10-bit resolution × 4 channels
10-bit resolution × 8 channels
Package
100-pin plastic LQFP (fine-pitch) (14 × 14)
144-pin plastic LQFP (fine-pitch) (20 × 20)
Other
Noise tolerance and noise radiation will differ due to differences in circuit scale and mask layout.
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
P02
Function
Port 0
6-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
TO100
TCLR10
P04
INTP100/DMARQ0
P05
INTP101/DMARQ1
P06
INTP102/DMARQ2
P07
INTP103/DMARQ3
P10
I/O
P12
Port 1
6-bit I/O port
Input/output can be specified in 1-bit units.
TO110
TCLR11
P14
INTP110/DMAAK0
P15
INTP111/DMAAK1
P16
INTP112/DMAAK2
P17
INTP113/DMAAK3
P20
Input
P22
I/O
P23
P24
P25
Port 2
P20 is an input only port.
When a valid edge is input, this pin operates as NMI input. Also, bit 0
of the P2 register indicates the NMI input status.
P22 to P27 are 6-bit I/O port.
Input/output can be specified in 1-bit units.
NMI
TXD0/SO0
RXD0/SI0
SCK0
TXD1/SO1
P26
RXD1/SI1
P27
SCK1
P33
I/O
P34
Port 3
2-bit I/O port
Input/output can be specified in 1-bit units.
TI13
INTP130
P50 to P57
I/O
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units.
D8 to D15
P60 to P67
I/O
Port 6
8-bit I/O port
Input/output can be specified in 1-bit units.
A16 to A23
P70 to P73
Input
Port 7
4-bit input only port
ANI0 to ANI3
Port 8
4-bit I/O port
Input/output can be specified in 1-bit units.
CS0
P80
P83
I/O
CS3/RAS3
P84
CS4/RAS4/IOWR
P85
CS5/RAS5/IORD
Preliminary Data Sheet U15390EJ1V0DS
7
µPD703130
(2/2)
Pin Name
P90
I/O
I/O
P91
Port 9
8-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
LCAS/LWR
UCAS/UWR
P92
RD
P93
WE
P94
BCYST
P95
OE
P96
HLDAK
P97
HLDRQ
P100
I/O
P102
PX6
PX7
8
Function
I/O
Port 10
2-bit I/O port
Input/output can be specified in 1-bit units.
TO120
Port X
2-bit I/O port
Input/output can be specified in 1-bit units.
WAIT
Preliminary Data Sheet U15390EJ1V0DS
TCLR12
CLKOUT
µPD703130
2.2 Non-Port Pins
(1/2)
Pin Name
TO100
I/O
Output
Function
Pulse signal output for timers 10 to 12
Alternate Function
P00
TO110
P10
TO120
P100
TCLR10
Input
External clear signal input for timers 10 to 12
P02
TCLR11
P12
TCLR12
P102
TI13
Input
External count clock input for timer 13
P33
INTP100
Input
External maskable interrupt request input, shared as external capture
trigger input for timer 10
P04/DMARQ0
INTP101
P05/DMARQ1
INTP102
P06/DMARQ2
INTP103
P07/DMARQ3
INTP110
Input
INTP111
External maskable interrupt request input, shared as external capture
trigger input for timer 11
P14/DMAAK0
P15/DMAAK1
INTP112
P16/DMAAK2
INTP113
P17/DMAAK3
INTP130
SO0
Input
Output
External maskable interrupt request input, shared as external capture
trigger input for timer 13
P34
Serial transmit data output (3-wire) for CSI0 and CSI1
P22/TXD0
SO1
SI0
P25/TXD1
Input
Serial receive data input (3-wire) for CSI0 and CSI1
SI1
SCK0
P26/RXD1
I/O
Serial clock I/O (3-wire) for CSI0 and CSI1
SCK1
TXD0
Output
Serial transmit data output for UART0 and UART1
Input
Serial receive data input for UART0 and UART1
P23/SI0
P26/SI1
I/O
–
16-bit data bus for external memory
D8 to D15
A0 to A15
P22/SO0
P25/SO1
RXD1
D0 to D7
P24
P27
TXD1
RXD0
P23/RXD0
P50 to P57
Output
–
24-bit address bus for external memory
A16 to A23
P60 to P67
LWR
Output
Lower byte write-enable signal output for external data bus
P90/LCAS
UWR
Output
Higher byte write-enable signal output for external data bus
P91/UCAS
RD
Output
Read strobe signal output for external data bus
P92
WE
Output
Write enable signal output for DRAM
P93
OE
Output
Output enable signal output for DRAM
P95
Preliminary Data Sheet U15390EJ1V0DS
9
µPD703130
(2/2)
Pin Name
I/O
Function
Alternate Function
LCAS
Output
Column address strobe signal output for DRAM’s lower data
P90/LWR
UCAS
Output
Column address strobe signal output for DRAM’s higher data
P91/UWR
RAS3
Output
Row address strobe signal output for DRAM
P83/CS3
RAS4
P84/CS4/IOWR
RAS5
P85/CS5/IORD
BCYST
Output
Strobe signal output indicating start of bus cycle
P94
CS0
Output
Chip select signal output
P80
CS3
P83/RAS3
CS4
P84/RAS4/IOWR
CS5
P85/RAS5/IORD
WAIT
Input
Control signal input for inserting waits in bus cycle
PX6
IOWR
Output
DMA write strobe signal output
P84/RAS4/CS4
IORD
Output
DMA read strobe signal output
P85/RAS5/CS5
DMA request signal input
P04/INTP100 to
P07/INTP103
DMARQ0 to
DMARQ3
Input
DMAAK0 to
DMAAK3
Output
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
HLDAK
Output
Bus hold acknowledge output
P96
HLDRQ
Input
Bus hold request input
P97
ANI0 to ANI3
Input
Analog input to A/D converter
P70 to P73
NMI
Input
Non-maskable interrupt request input
P20
System clock output
PX7
CLKOUT
Output
CKSEL
Input
Input for specifying clock generator’s operation mode
–
MODE0,
MODE2
Input
Specify operation modes
–
RESET
Input
System reset input
–
X1
Input
–
X2
–
Connecting resonator for system clock. Input is via X1 when using an
external clock.
Reference voltage input for A/D converter
–
–
AVREF
Input
AVDD
–
Positive power supply for A/D converter
–
AVSS
–
Ground potential for A/D converter
–
CVDD
–
Positive power supply for dedicated clock generator
–
CVSS
–
Ground potential for dedicated clock generator
–
VDD
–
Positive power supply (power supply for internal units)
–
HVDD
–
Positive power supply (power supply for external pins)
–
VSS
–
Ground potential
–
10
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
Recommended Connection of Unused Pins
5
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P20/NMI
2
Connect directly to VSS
P22/TXD0/SO0
5
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P70/ANI0 to P73/ANI3
9
Connect directly to VSS
P80/CS0, to P83/CS3/RAS3
5
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P00/TO100
P02/TCLR10
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110
P12/TCLR11
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P23/RXD0/SI0
P24/SCK0
P25/TXD1/SO1
P26/RXD1/SI1
P27/SCK1
P33/TI13
P34/INTP130
P50/D8 to P57/D15
P60/A16 to P67/A23
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P90/LCAS/LWR
P91/UCAS/UWR
P92/RD
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120
P102/TCLR12
Preliminary Data Sheet U15390EJ1V0DS
11
µPD703130
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin
PX6/WAIT
I/O Circuit Type
5
PX7/CLKOUT
A0 to A15
4
D0 to D7
5
CKSEL
1
RESET
2
Recommended Connection of Unused Pins
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
–
MODE0, MODE2
AVREF, AVSS
–
Connect directly to VSS
AVDD
–
Connect directly to HVDD
12
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Figure 2-1. Pin I/O Circuits
Type 1
Type 5
VDD
VDD
Data
P-ch
IN/OUT
P-ch
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 9
P-ch
IN
IN
+
–
N-ch
Comparator
VREF (threshold voltage)
Input enable
Schmitt-triggered input with hysteresis characteristics
Type 4
VDD
Data
P-ch
OUT
Output
disable
N-ch
Push-pull output with possible high-impedance output
(P-ch, N-ch both off)
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
Preliminary Data Sheet U15390EJ1V0DS
13
µPD703130
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°°C)
Parameter
Power supply voltage
Input voltage
Symbol
Rating
Unit
VDD pin
−0.5 to +4.6
V
HVDD
HVDD pin, HVDD ≥ VDD
−0.5 to +7.0
V
CVDD
CVDD pin
−0.5 to +4.6
V
CVSS
CVSS pin
−0.5 to +0.5
VDD
Condition
AVDD
AVDD pin
AVSS
AVSS pin
VI
V
Note
−0.5 to HVDD + 0.5
−0.5 to +0.5
V
Note
−0.5 to HVDD + 0.5
Except X1 pin
V
Note
−0.5 to VDD + 1.0
V
Clock input voltage
VK
X1, VDD = 3.0 to 3.6 V
Output current, low
IOL
1 pin
4.0
mA
Total of all pins
100
mA
1 pin
−4.0
mA
Total of all pins
−100
Output current, high
Output voltage
IOH
Analog input voltage
A/D converter reference input
voltage
VIAN
P70/ANI0 to P73
pins
AVREF
mA
Note
V
Note
V
Note
V
Note
V
Note
V
−0.5 to HVDD + 0.5
HVDD = 5.0 V ±10%
VO
AVDD > HVDD
HVDD ≥ AVDD
AVDD > HVDD
HVDD ≥ AVDD
V
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
−0.5 to HVDD + 0.5
−0.5 to AVDD + 0.5
Operating ambient temperature
TA
−40 to +85
°C
Storage temperature
Tstg
−60 to +150
°C
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of the each power supply voltage.
Cautions
1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected to each other. A direct connection
can also be made for an external circuit designed with timing specifications that prevent
conflicting output from pins subject to a high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
14
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Capacitance (TA = 25°°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Condition
MIN.
fc = 1 MHz
Unmeasured pins returned to 0 V.
TYP.
MAX.
Unit
15
pF
15
pF
15
pF
Operating Conditions
Operation Mode
Operating Ambient
Temperature (TA)
Note 1
−40 to +85°C
Note 3
−40 to +85°C
10 to 33 MHz
Direct mode
Note 2
PLL mode
Internal Operating Clock Frequency (fX)
20 to 33 MHz
Power Supply Voltage
(VDD, HVDD)
VDD = 3.0 to 3.6 V,
HVDD = 5.0 V ±10%
Notes 1. Set the input clock frequency used in direct mode to 20 to 66 MHz.
2. The internal operating clock frequency in PLL mode is the value for 5× operation. When used for 1× or
1/2× operation as set by the CKDIVn (n = 0, 1) bit of the CKC register, operation at a frequency of 20
MHz or less is possible.
3. Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
Preliminary Data Sheet U15390EJ1V0DS
15
µPD703130
Recommended Oscillator
(a) Ceramic resonator
(i) Murata Mfg. Co., Ltd. (TA = −40 to +85°°C)
X1
X2
Rd
C2
C1
Manufacturer
Murata
Mfg.
Part Number
Note
CSTS400MG06
Oscillation
Frequency
fXX (MHz)
Recommended Circuit Constant
Oscillation Voltage
Range
Oscillation
Stabilization
Time (MAX.)
TOST (ms)
C1 (pF)
C2 (pF)
Rd (kΩ)
MIN. (V)
MAX. (V)
4.0
On-chip
On-chip
0
3.0
3.6
0.6
4.0
On-chip
On-chip
0
3.0
3.6
0.6
5.0
On-chip
On-chip
0
3.0
3.6
0.6
5.0
On-chip
On-chip
0
3.0
3.6
0.6
6.6
On-chip
On-chip
0
3.0
3.6
0.6
6.6
On-chip
On-chip
0
3.0
3.6
0.6
(CSTLS4M00G56-B0)
CSTCR4M00G55-R0
Note
CSTS0500MG06
(CSTLS5M00G56-B0)
CSTCR5M00G55-R0
Note
CSTS066MG06
(CSTLS6M60G56-B0)
CSTCR6M60G55-R0
Note The part number will be changed to the part number in the parentheses from June 2001.
Cautions
1. Connect the oscillator as close to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
16
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(ii) TDK (TA = −40 to +85°°C)
X1
X2
Rd
C1
Manufacturer
TDK
Part Number
Oscillation
Frequency
fXX (MHz)
C2
Recommended Circuit Constant
C1 (pF)
C2 (pF)
Rd (kΩ)
Oscillation
Voltage Range
MIN. (V) MAX. (V)
Oscillation
Stabilization Time
(MAX.) TOST (ms)
FCR4.0MC5
4.0
On-chip
On-chip
0
3.0
3.6
0.73
FCR5.0MC5
5.0
On-chip
On-chip
0
3.0
3.6
0.68
FCR6.0MC5
6.0
On-chip
On-chip
0
3.0
3.6
0.58
Cautions
1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
(iii) Kyocera Corporation (TA = −20 to +80°°C)
X1
X2
Rd
C1
Type
Lead
SMD
Part Number
Oscillation
Frequency
fXX (MHz)
C2
Recommended Circuit Constant
Oscillation
Voltage Range
C1 (pF)
C2 (pF)
Rd (kΩ)
MIN. (V)
MAX. (V)
Oscillation
Stabilization Time
(MAX.) TOST (ms)
KBR-4.0MKC
4.0
On-chip
On-chip
0
3.0
3.6
0.80
KBR-5.0MKC
5.0
On-chip
On-chip
0
3.0
3.6
0.70
KBR-6.0MKC
6.0
On-chip
On-chip
0
3.0
3.6
0.76
PBRC4.00HR
4.0
On-chip
On-chip
0
3.0
3.6
0.80
PBRC5.00HR
5.0
On-chip
On-chip
0
3.0
3.6
0.70
PBRC6.00HR
6.0
On-chip
On-chip
0
3.0
3.6
0.76
Cautions
1. Connect the oscillator as close to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
Preliminary Data Sheet U15390EJ1V0DS
17
µPD703130
(b) External clock input (TA = –40 to +85°°C)
X1
X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
18
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
DC Characteristics (TA = –40 to +85°°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V)
Parameter
Input voltage, high
Symbol
Condition
MAX.
Unit
2.2
HVDD + 0.3
V
0.8HVDD
HVDD + 0.3
V
Except Note 1 and Note 2
−0.5
+0.8
V
Note 1
−0.5
0.2HVDD
V
Except Note 1
VIH
Note 1
Input voltage, low
MIN.
VIL
TYP.
Clock input voltage, high
VXH
X1 pin
0.8VDD
VDD + 0.3
V
Clock input voltage, low
VXL
X1 pin
−0.3
0.15VDD
V
Schmitt-triggered input
threshold voltage
Output voltage, high
+
Note 1, rising edge
3.0
V
HVT−
Note 1, falling edge
2.0
V
VOH
IOH = −2.5 mA
0.7HVDD
V
IOH = −100 µA
HVDD − 0.4
V
HVT
Output voltage, low
VOL
IOL = 2.5 mA
0.45
V
Input leakage current, high
ILIH
VI = HVDD, except Note 2
10
µA
Input leakage current, low
ILIL
VI = 0 V, except Note 2
−10
µA
Output leakage current, high
ILOH
VO = HVDD
10
µA
Output leakage current, low
ILOL
VO = 0 V
−10
µA
Power supply
current
Normal
mode
IDD1
HALT mode
IDD2
IDLE mode
STOP
mode
IDD3
IDD4
VDD + CVDD
2.0 × fx
3.0 × fx
mA
HVDD
1.5 × fx
2.5 × fx
mA
VDD + CVDD
1.4 × fx
1.8 × fx
mA
HVDD
0.7 × fx
1.2 × fx
mA
VDD + CVDD
1.4
2.5
mA
HVDD
20
100
µA
VDD + CVDD
20
100
µA
HVDD
10
50
µA
Notes 1. P20/NMI, MODE0, MODE2, CKSEL, RESET
2. When the P70/ANI0 to P73/ANI3 pins are used as analog input.
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode: fX = 10 to 33 MHz
PLL mode: fX = 20 to 33 MHz
3. The unit for fX is MHz.
Preliminary Data Sheet U15390EJ1V0DS
19
µPD703130
Data Hold Characteristics (TA = –40 to +85°°C)
Parameter
Symbol
Data hold voltage
VDDDR
HVDDDR
Condition
MIN.
STOP mode, VDD = VDDDR
STOP mode,
HVDD = HVDDDR
MAX.
Unit
1.5
3.6
V
VDDDR
5.5
V
150
µA
VDD = VDDDR
TYP.
Data hold current
IDDDR
30
Power supply voltage rise
time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold
time (from STOP mode
setting)
tHVD
0
ms
STOP mode release signal
input time
tDREL
0
ns
Data hold input voltage, high
VIHDR
P20/NMI, MODE0, MODE2,
CKSEL, RESET
0.8HVDDDR
HVDDDR
V
Data hold input voltage, low
VILDR
P20/NMI, MODE0, MODE2,
CKSEL, RESET
0
0.2HVDDDR
V
Remark TYP. values are reference values for when TA = 25°C.
STOP mode setting
3.0 V
VDDDR
VDD
tFVD
tRVD
tHVD
tDREL
HVDD
RESET (Input)
NMI (Input)
(Released by falling edge)
VIHDR
VIHDR
NMI (Input)
(Released by rising edge)
VILDR
20
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
AC Characteristics (TA = –40 to +85°°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 ±10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Test Points
(a) P20/NMI, MODE0, MODE2, CKSEL, RESET
HVDD
0.8HVDD
Input signal
0V
0.8HVDD
Test
points
0.2HVDD
0.2HVDD
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
Input signal
0.4 V
2.2 V
Test
points
0.8 V
0.8 V
AC Test Output Test Points
2.4 V
Output signal
2.4 V
Test
points
0.8 V
0.8 V
Load Condition
DUT
(Device under test)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device's load capacitance 50 pF.
Preliminary Data Sheet U15390EJ1V0DS
21
µPD703130
(1) Clock timing
Parameter
Symbol
X1 input cycle
<1>
X1 input high-level width
<2>
X1 input low-level width
<3>
X1 input rise time
<4>
X1 input fall time
<5>
tCYX
tWXH
tWXL
tXR
tXF
Condition
MIN.
MAX.
Unit
Direct mode
15
50
ns
PLL mode
150
250
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
5
ns
PLL mode
50
ns
Direct mode
4
ns
PLL mode
10
ns
Direct mode
4
ns
PLL mode
10
ns
100
ns
CLKOUT output cycle
<6>
tCYK
30
CLKOUT high-level width
<7>
tWKH
0.5T – 7
ns
CLKOUT low-level width
<8>
tWKL
0.5T – 4
ns
CLKOUT rise time
<9>
tKR
5
ns
CLKOUT fall time
<10>
tKF
5
ns
Remark T = tCYK
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<2>
<3>
<4>
X1
(Direct mode)
<5>
CLKOUT (Output)
<9>
<10>
<7>
<8>
<6>
22
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(2) Output waveform (other than X1, CLKOUT)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Output rise time
<12>
tOR
10
ns
Output fall time
<13>
tOF
10
ns
<12>
<13>
Signals other than X1, CLKOUT
(3) Reset timing
Parameter
Symbol
Condition
RESET high-level width
<14>
tWRSH
RESET low-level width
<15>
tWRSL
MIN.
MAX.
Unit
500
ns
When power supply is on, and
STOP mode has been released
500 + TOS
ns
Other than when power supply is
on, and STOP mode has been
released
500
ns
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (Input)
Preliminary Data Sheet U15390EJ1V0DS
23
µPD703130
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Address, CSn output delay time (from
CLKOUT ↓)
<16>
tDKA
2
10
ns
Address, CSn output hold time (from
CLKOUT ↓)
<17>
tHKA
2
10
ns
RD, IORD ↓ delay time
(from CLKOUT ↑)
<18>
tDKRDL
2
14
ns
RD, IORD ↑ delay time
(from CLKOUT ↑)
<19>
tHKRDH
2
14
ns
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
<20>
tDKWRL
2
10
ns
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
<21>
tHKWRH
2
10
ns
BCYST ↓ delay time (from CLKOUT
↓)
<22>
tDKBSL
2
10
ns
BCYST ↑ delay time (from CLKOUT
↓)
<23>
tHKBSH
2
10
ns
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time
(to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time
(from CLKOUT ↑)
<27>
tHKID
2
ns
Data output delay time
(from CLKOUT ↓)
<28>
tDKOD
2
10
ns
Data output hold time
(from CLKOUT ↓)
<29>
tHKOD
2
10
ns
Remarks 1. Maintain at least one of the data input hold times tHKID and tHRDID.
2. n = 0, 3 to 5
24
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<17>
A0 to A23 (Output)
CSn (Output)
<22>
<23>
BCYST (Output)
<18>
<19>
<20>
<21>
RD, IORD (Output)
[Read time]
UWR, LWR, IOWR (Output)
[Write time]
<26>
<27>
D0 to D15 (I/O)
[Read time]
<28>
<29>
D0 to D15 (I/O)
[Write time]
<25>
<24>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
25
µPD703130
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to address)
<30>
tSAID
(1.5 + wD + w)T – 28
ns
Data input setup time (to RD)
<31>
tSRDID
(1 + wD + w)T – 32
ns
RD, IORD low-level width
<32>
tWRDL
(1 + wD + w)T – 10
ns
RD, IORD high-level width
<33>
tWRDH
T – 10
ns
Delay time from address, CSn to RD,
IORD ↓
<34>
tDARD
0.5T – 10
ns
Delay time from RD, IORD ↑ to
address
<35>
tDRDA
(0.5 + i)T – 10
ns
Data input hold time (from RD, IORD ↑)
<36>
tHRDID
0
ns
Delay time from RD, IORD ↑ to data
output
<37>
tDRDOD
(0.5 + i)T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
0
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wD: The number of waits due to the DWC1 and DWC2 registers.
4. i: The number of idle states that are inserted when a write cycle follows a read cycle.
5. Maintain at least one of the data input hold times, tHKID or tHRDID.
6. n = 0, 3 to 5
26
Preliminary Data Sheet U15390EJ1V0DS
ns
µPD703130
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
UWR, LWR, IOWR (Output)
<33>
<32>
<35>
RD, IORD (Output)
<34>
<31>
<30>
<37>
<36>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
27
µPD703130
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
Delay time from address, CSn to
UWR, LWR, IOWR ↓
<41>
Address setup time (to UWR, LWR,
IOWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w)T – 10
ns
Delay time from UWR, LWR, IOWR ↑
to address
<43>
tDWRA
0.5T – 10
ns
UWR, LWR, IOWR high-level width
<44>
tWWRH
T – 10
ns
UWR, LWR, IOWR low-level width
<45>
tWWRL
(1 + wD + w)T – 10
ns
Data output setup time
(to UWR, LWR, IOWR ↑)
<46>
tSODWR
(1.5 + wD + w)T – 10
ns
Data output hold time
(from UWR, LWR, IOWR ↑)
<47>
tHWROD
0.5T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wD: The number of waits due to the DWC1 and DWC2 registers.
4. n = 0, 3 to 5
28
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
<41>
<42>
<45>
<43>
<44>
UWR, LWR, IOWR (Output)
<46>
<47>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
29
µPD703130
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
RD low-level width
<32>
tWRDL
(1 + wD + wF + w)T
– 10
ns
RD high-level width
<33>
tWRDH
T – 10
ns
Delay time from address, CSn to RD ↓
<34>
tDARD
0.5T – 10
ns
Delay time from RD ↑ to address
<35>
tDRDA
(0.5 + i)T – 10
ns
Delay time from RD ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
Delay time from address to IOWR ↓
<41>
Address setup time (to IOWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w)T – 10
ns
Delay time from IOWR ↑ to address
<43>
tDWRA
0.5T – 10
ns
IOWR high-level width
<44>
tWWRH
T – 10
ns
IOWR low-level width
<45>
tWWRL
(1 + wD + w)T – 10
ns
Delay time from IOWR ↑ to RD ↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
Delay time from DMAAKm ↓ to IOWR ↓
<49>
tDDAWR
0.5T – 10
ns
Delay time from IOWR ↑ to DMAAKm ↑
<50>
tDWRDA
(0.5 + wF)T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wD: The number of waits due to the DWC1 and DWC2 registers.
4. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: The number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0, 3 to 5, m = 0 to 3
30
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<33>
<32>
<35>
RD (Output)
<34>
<48>
UWR, LWR (Output)
DMAAKm (Output)
<49>
<50>
IORD (Output)
<42>
<41>
<43>
<45>
<44>
IOWR (Output)
<37>
D0 to D15 (I/O)
<38>
<24>
<25>
<25>
<24>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
31
µPD703130
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
IORD low-level width
<32>
tWRDL
(1 + wD + wF + w)T
– 10
ns
IORD high-level width
<33>
tWRDH
T – 10
ns
Delay time from address, CSn to
IORD ↓
<34>
tDARD
0.5T – 10
ns
Delay time from IORD ↑ to address
<35>
tDRDA
(0.5 + i)T – 10
ns
Delay time from IORD ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
WAIT setup time (to address)
<38>
tSAW
Note
T – 25
ns
WAIT setup time (to BCYST ↓)
<39>
tSBSW
Note
T – 25
ns
WAIT hold time (from BCYST ↑)
<40>
tHBSW
Note
Delay time from address to UWR,
LWR ↓
<41>
Address setup time (to UWR, LWR ↑)
0
ns
tDAWR
0.5T – 10
ns
<42>
tSAWR
(1.5 + wD + w)T – 10
ns
Delay time from UWR, LWR to
address
<43>
tDWRA
0.5T – 10
ns
UWR, LWR high-level width
<44>
tWWRH
T – 10
ns
UWR, LWR low-level width
<45>
tWWRL
(1 + wD + w)T – 10
ns
Delay time from UWR, LWR↑ to IORD ↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
Delay time from DMAAKm ↓ to IORD ↓
<51>
tDDARD
0.5T – 10
ns
Delay time from IORD ↑ to DMAAKm ↑
<52>
tDRDDA
0.5T – 10
ns
Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wD: The number of waits due to the DWC1 and DWC2 registers.
4. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. i: The number of idle states that are inserted when a write cycle follows a read cycle.
6. n = 0, 3 to 5, m = 0 to 3
32
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<41>
<42>
<45>
<43>
<44>
UWR, LWR (Output)
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output)
<34>
<33>
<32>
<35>
IORD (Output)
<37>
D0 to D15 (I/O)
<38>
<24>
<25>
<25>
<24>
WAIT (Input)
<40>
<39>
BCYST (Output)
Remarks 1. This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and wF = 0.
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
33
µPD703130
(5) Page ROM access timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time
(to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time
(from CLKOUT ↑)
<27>
tHKID
2
ns
Off-page data input setup time (to
address)
<30>
tSAID
(1.5 + wD + w)T – 28
ns
Off-page data input setup time (to RD)
<31>
tSRDID
(1 + wD + w)T – 32
ns
Off-page RD low-level width
<32>
tWRDL
(1 + wD + w)T – 10
ns
RD high-level width
<33>
tWRDH
0.5T – 10
ns
Data input hold time (from RD)
<36>
tHRDID
0
ns
Delay time from RD ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
On-page RD low-level width
<53>
tWORDL
(1.5 + wPR + w)T
– 10
ns
On-page data input setup time
(to address)
<54>
tSOAID
(1.5 + wPR + w)T – 28
ns
On-page data input setup time (to RD)
<55>
tSORDID
(1.5 + wPR + w)T – 32
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wD: The number of waits due to the DWC1 and DWC2 registers.
4. wPR: The number of waits due to the PRC register.
5. i: The number of idle states that are inserted when a write cycle follows a read cycle.
6. Maintain at least one of the data input hold times, tHKID or tHRDID.
34
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1
TPRW
TW
TO2
CLKOUT (Output)
Off-page addressNote
CSn (Output)
On-page addressNote
<26>
<30>
<54>
UWR, LWR (Output)
<33>
<32>
<53>
<55>
<31>
<37>
RD (Output)
<36>
<36>
<26>
<27>
<27>
D0 to D15 (I/O)
<25>
<24>
<25>
<24>
<25>
<24>
<24>
<25>
WAIT (Input)
BCYST (Output)
Note On-page and off-page addresses are as follows.
PRC Register
MA5
MA4
MA3
On-page Addresses
Off-page Addresses
0
0
0
A0, A1
A2 to A23
0
0
1
A0 to A2
A3 to A23
0
1
1
A0 to A3
A4 to A23
1
1
1
A0 to A4
A5 to A23
Remarks 1. This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW): 1
2. The broken lines indicate high impedance.
3. n = 0, 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
35
µPD703130
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Delay time from OE ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + w)T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + w)T
– 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS pulse time
<62>
tRAS
(2.5 + wRH + wDA + w)T
– 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + w)T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wDA + w)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + w)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP)T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + w)T
– 10
ns
WE setup time
<68>
tRCS
(2 + wRP + wRH)T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH)T – 10
ns
Output enable access time
<72>
tOEA
(2 + wRP + wRH + wDA + w)T
– 28
ns
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)T
– 28
ns
Access time from column address
<74>
tAA
(1.5 + wDA + w)T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA + w)T – 28
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: The number of idle states that are inserted when a write cycle follows a read cycle.
36
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
RAS column address delay time
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
ns
Remarks 1. T = tCYK
2. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Preliminary Data Sheet U15390EJ1V0DS
37
µPD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
<58>
<56>
<57>
<59>
Row address
A0 to A23 (Output)
Column address
<63>
<64>
<76>
<61>
<62>
RASn (Output)
<60>
<77>
<65>
<66>
<67>
UCAS (Output)
LCAS (Output)
<69>
<71>
<73>
<68>
<75>
<70>
WE (Output)
<79>
<74>
<27>
<72>
<37>
OE (Output)
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
38
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
39
µPD703130
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Delay time from OE ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
Column address setup time
<58>
tASC
(0.5 + wCP)T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA)T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA)T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA)T – 10
ns
WE setup time (to CAS ↓)
<68>
tRCS
(1 + wCP)T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
T – 10
ns
Output enable access time
<72>
tOEA
(1 + wCP + wDA)T – 28
ns
Access time from column address
<74>
tAA
(1.5 + wCP + wDA)T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA)T – 28
ns
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
ns
Access time from CAS precharge
<80>
tACP
CAS precharge time
<81>
tCP
(1 + wCP)T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA)T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA)T – 10
ns
(2 + wCP + wDA)T – 28
ns
Remarks 1. T = tCYK
2. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. i: The number of idle states that are inserted when a write cycle follows a read cycle.
40
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
<58>
<59>
A0 to A23 (Output)
Column address
<63>
<64>
RASn (Output)
<83>
<81>
<65>
<82>
UCAS (Output)
LCAS (Output)
<69>
<68>
<70>
WE (Output)
<75>
<72>
<79>
<26>
<37>
OE (Output)
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
41
µPD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + w)T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + w)T
– 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS pulse time
<62>
tRAS
(2.5 + wRH + wDA + w)T
– 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + w)T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wDA + w)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + w)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRH)T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + w)T
– 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH)T – 10
ns
RAS column address delay time
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
WE setup time (to CAS ↓)
<84>
tWCS
(1 + wRP + wRH )T
– 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA + w)T – 10
ns
Data setup time (to CAS ↓)
<86>
tDS
(1.5 + wRP + wRH)T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(1.5 + wDA + w)T – 10
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
42
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
T2
TDAW
TW
T3
CLKOUT (Output)
<58>
<56>
<57>
<59>
Row address
A0 to A23 (Output)
Column address
<63>
<64>
<76>
<61>
<62>
RASn (Output)
<60>
<77>
<66>
<65>
<67>
UCAS (Output)
LCAS (Output)
<71>
OE (Output)
<84>
<85>
WE (Output)
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<25>
<24>
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
43
µPD703130
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Column address setup time
<58>
tASC
(0.5 + wCP)T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA)T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA)T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wCP + wDA)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA)T – 10
ns
CAS precharge time
<81>
tCP
(1 + wCP)T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA)T
– 10
ns
WE setup time (to CAS ↓)
<84>
tWCS
wCPT – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA)T – 10
ns
Data setup time (to CAS ↓)
<86>
tDS
(0.5 + wCP)T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(1.5 + wDA)T – 10
ns
WE read time (from RAS ↑)
<88>
tRWL
wCP = 0
(1.5 + wDA)T – 10
ns
WE read time (from CAS ↑)
<89>
tCWL
wCP = 0
(1 + wDA)T – 10
ns
Data setup time (to WE ↓)
<90>
tDSWE
wCP = 0
0.5T – 10
ns
Data hold time (from WE ↓)
<91>
tDHWE
wCP = 0
(1.5 + wDA)T – 10
ns
WE pulse width
<92>
tWP
wCP = 0
(1 + wDA)T – 10
ns
wCP ≥ 1
Remarks 1. T = tCYK
2. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
44
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
<58>
A0 to A23 (Output)
<59>
Column address
<63>
<64>
RASn (Output)
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
<84>
<85>
<92>
WE (Output)
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
45
µPD703130
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Data input setup time (to CLKOUT ↑)
<26>
tSKID
18
ns
Data input hold time (from CLKOUT ↑)
<27>
tHKID
2
ns
Delay time from OE ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(0.5 + wDA)T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
Column address read time (from RAS ↑)
<64>
tRAL
(2 + wCP + wDA)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP)T – 10
ns
CAS hold time
<67>
tCSH
(1.5 + wRH + wDA)T – 10
ns
WE setup time (to CAS ↓)
<68>
tRCS
(2 + wRP + wRH)T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
1.5T – 10
ns
RAS access time
<73>
tRAC
(2 + wRH + wDA)T – 28
ns
Access time from column address
<74>
tAA
(1.5 + wDA)T – 28
ns
CAS access time
<75>
tCAC
(1 + wDA)T – 28
ns
Delay time from RAS to column address
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
Output buffer turn-off delay time (from
OE)
<78>
tOEZ
0
ns
Access time from CAS precharge
<80>
tACP
CAS precharge time
<81>
tCP
(0.5 + wCP)T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2 + wCP + wDA)T – 10
ns
Read cycle time
<93>
tHPC
(1 + wDA + wCP)T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA)T – 10
ns
CAS pulse width
<95>
tHCAS
(0.5 + wDA)T – 10
ns
Off-page
<96>
tOCH1
(2 + wRH + wDA)T – 10
ns
On-page
<97>
tOCH2
(0.5 + wDA)T – 10
ns
<98>
tDHC
0
ns
CAS hold time from OE
Data input hold time (from CAS ↓)
(1.5 + wCP + wDA)T – 28
ns
Remarks 1. T = tCYK
2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. i: The number of idle states that are inserted when a write cycle follows a read cycle.
46
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) Read timing (EDO DRAM) (2/3)
Parameter
Output enable access
time
Symbol
Condition
MIN.
MAX.
Unit
Off-page
<99>
tOEA1
(2 + wRP + wRH + wDA)T
– 28
ns
On-page
<100>
tOEA2
(1 + wCP + wDA)T – 28
ns
Remarks 1. T = tCYK
2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10
to 13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
Preliminary Data Sheet U15390EJ1V0DS
47
µPD703130
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<56>
A0 to A23 (Output)
<57>
Row address
<59>
Column address
Column address
<64>
<76>
<74>
<94>
<61>
RASn (Output)
<67>
<66>
<83>
<77>
<95>
<81>
<75>
UCAS (Output)
LCAS (Output)
<68>
<93>
<69>
<95>
<80>
<70>
WE (Output)
<97>
<96>
<100>
<26>
Note
OE (Output)
<75>
<74>
<98>
<27>
<27>
<78>
<26>
D0 to D15 (I/O)
Data
<73>
<99>
BCYST (Output)
WAIT (Input)
Note For on-page access from another cycle during the RASn low-level signal.
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
48
Preliminary Data Sheet U15390EJ1V0DS
Data
<37>
µPD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
49
µPD703130
(f) Write timing (EDO DRAM) (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(0.5 + wDA)T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA)T – 10
ns
Column address read time
(from RAS ↑)
<64>
tRAL
(2 + wCP + wDA)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP)T – 10
ns
CAS hold time
<67>
tCSH
(1.5 + wRH + wDA)T – 10
ns
Delay time from RAS to column address
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
CAS precharge time
<81>
tCP
(0.5 + wCP)T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2 + wCP + wDA)T – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA)T – 10
ns
Data hold time (from CAS ↓)
<87>
tDH
(0.5 + wDA)T – 10
ns
WE read time
(from RAS ↑)
On-page
<88>
tRWL
wCP = 0
(1.5 + wDA)T – 10
ns
WE read time
(from CAS ↑)
On-page
<89>
tCWL
wCP = 0
(0.5 + wDA)T – 10
ns
WE pulse width
On-page
<92>
tWP
wCP = 0
(1 + wDA)T – 10
ns
Write cycle time
<93>
tHPC
(1 + wDA + wCP)T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA)T – 10
ns
CAS pulse width
<95>
tHCAS
(0.5 + wDA)T – 10
ns
Off-page
<101>
tWCS1
(1 + wRP + wRH)T – 10
ns
On-page
<102>
tWCS2
wCPT – 10
ns
Off-page
<103>
tDS1
(1.5 + wRP + wRH)T – 10
ns
On-page
<104>
tDS2
(0.5 + wCP)T – 10
ns
WE setup time
(to CAS ↓)
Data setup time
(to CAS ↓)
wCP ≥ 1
Remarks 1. T = tCYK
2. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
50
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW
TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<56>
<57>
<59>
Row address
A0 to A23 (Output)
<58>
Column address
<59>
Column address
<76>
<64>
<61>
<94>
RASn (Output)
<67>
<66>
<77>
<83>
<95>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<95>
<89>
<88>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
<103>
D0 to D15 (I/O)
<87>
<104>
Data
<87>
Data
BCYST (Output)
WAIT (Input)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
51
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
Delay time from OE ↑ to data output
<37>
tDRDOD
(0.5 + i)T – 10
ns
Delay time from address to IOWR ↓
<41>
tDAWR
(0.5 + wRP)T – 10
ns
Address setup time (to IOWR ↑)
<42>
tSAWR
(2 + wRP + wRH + wDA +
w)T – 10
ns
Delay time from IOWR ↑ to address
<43>
tDWRA
0.5T – 10
ns
Delay time from IOWR ↑ to RD ↑
<48>
tDWRRD
wF = 0
0
ns
wF = 1
T – 10
ns
IOWR low-level width
<50>
tWWRL
(2 + wRH + wDA + w)T
– 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + wF + w)T
– 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF + w)T – 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + wF + w)T
– 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA + wF +
w)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + wF + w)T
– 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP)T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + wF +
w)T – 10
ns
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: The number of idle states that are inserted when a write cycle follows a read cycle.
52
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WE setup time (to CAS ↓)
<68>
tRCS
(2 + wRP + wRH)T – 10
ns
WE hold time (from RAS ↑)
<69>
tRRH
0.5T – 10
ns
WE hold time (from CAS ↑)
<70>
tRCH
1.5T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH)T – 10
ns
Delay time from RAS to column address
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH)T – 10
ns
Output buffer turn-off delay time (from
OE ↑)
<78>
tOEZ
0
ns
Output buffer turn-off delay time (from
CAS ↑)
<79>
tOFF
0
ns
CAS precharge time
<81>
tCP
(0.5 + wCP)T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA + wF + w)T
– 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA + wF + w)T
– 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA + wF + w)T
– 10
ns
Off-page
<96>
tOCH1
(2.5 + wRP + wRH + wDA +
wF + w)T – 10
ns
On-page
<97>
tOCH2
(1.5 + wCP + wDA + wF + w)T
– 10
ns
Delay time from DMAAKm ↓ to CAS ↓
<105>
tDDACS
(1.5 + wRH)T – 10
ns
Delay time from IOWR ↓ to CAS ↓
<106>
tDRDCS
(1 + wRH)T – 10
ns
CAS hold time from OE
(from CAS ↑)
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
53
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW
T1
T2
TRHW
TDAW
TW
T3
TCPW TO1 TDAW
TW
TO2
CLKOUT (Output)
<58>
<56>
A0 to A23 (Output)
<57>
<59>
Row address
Column address
Column address
<76>
<64>
<61>
<94>
<60>
RASn (Output)
<77>
<65>
<66>
<69>
<83>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<70>
<82>
<96>
<79>
RD (Output)
OE (Output)
<48>
<105>
<97>
DMAAKm (Output)
<68>
WE (Output)
IORD (Output)
<106>
<42>
<41>
<43>
<78>
<37>
<50>
IOWR (Output)
<24>
D0 to D15 (I/O)
Data
<25>
<24>
Data
<24>
<25>
<25>
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 3 to 5, m = 0 to 3
54
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WAIT setup time (to CLKOUT ↓)
<24>
tSWK
15
ns
WAIT hold time (from CLKOUT ↓)
<25>
tHKW
2
ns
IORD low-level width
<32>
tWRDL
(2 + wRH + wDA + wF + w)T – 10
ns
IORD high-level width
<33>
tWRDH
T – 10
ns
Delay time from address to IORD ↑
<34>
tDARD
0.5T – 10
ns
Delay time from IORD ↑ to address
<35>
tDRDA
(0.5 + i)T – 10
ns
Row address setup time
<56>
tASR
(0.5 + wRP)T – 10
ns
Row address hold time
<57>
tRAH
(0.5 + wRH)T – 10
ns
Column address setup time
<58>
tASC
0.5T – 10
ns
Column address hold time
<59>
tCAH
(1.5 + wDA + wF)T – 10
ns
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA + wF + w)T
– 10
ns
RAS precharge time
<61>
tRP
(0.5 + wRP)T – 10
ns
RAS hold time
<63>
tRSH
(1.5 + wDA + wF)T – 10
ns
Column address read time for RAS
<64>
tRAL
(2 + wCP + wDA + wF + w)T – 10
ns
CAS pulse width
<65>
tCAS
(1 + wDA + wF)T – 10
ns
CAS-RAS precharge time
<66>
tCRP
(1 + wRP)T – 10
ns
CAS hold time
<67>
tCSH
(2 + wRH + wDA + wF + w)T – 10
ns
CAS precharge time
<71>
tCPN
(2 + wRP + wRH + w)T – 10
ns
Delay time from RAS to column address
<76>
tRAD
(0.5 + wRH)T – 10
ns
RAS-CAS delay time
<77>
tRCD
(1 + wRH + w)T – 10
ns
CAS precharge time
<81>
tCP
(0.5 + wCP + w)T – 10
ns
High-speed page mode cycle time
<82>
tPC
(2 + wCP + wDA + wF + w)T – 10
ns
RAS hold time for CAS precharge
<83>
tRHCP
(2.5 + wCP + wDA + w)T – 10
ns
WE hold time (from CAS ↓)
<85>
tWCH
(1 + wDA)T – 10
ns
WE read time (from RAS ↑)
<88>
tRWL
(1.5 + wDA + w)T – 10
ns
wCP = 0
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. i: The number of idle states that are inserted when a write cycle follows a read cycle.
Preliminary Data Sheet U15390EJ1V0DS
55
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
WE read time (from CAS ↑)
<89>
tCWL
wCP = 0
(1 + wDA + w)T – 10
ns
WE pulse width
<92>
tWP
wCP = 0
(1 + wDA + w)T – 10
ns
RAS pulse width
<94>
tRASP
(2.5 + wRH + wDA + wF + w)T – 10
ns
Off-page
<101>
tWCS1
wCP = 0
(1 + wRH + wRP + w)T – 10
ns
On-page
<102>
tWCS2
wCP ≥ 1
wCPT – 10
ns
Delay time from DMAAKm ↓ to CAS
↓
<105>
tDDACS
(1.5 + wRH + w)T – 10
ns
Delay time from IORD ↓ to CAS ↓
<106>
tDRDCS
(1 + wRH + w)T – 10
ns
Delay time from WE ↑ to IORD ↑
<107>
tDWERD
wF = 0
0
ns
wF = 1
T – 10
ns
WE setup time
(to CAS ↓)
Remarks 1. T = tCYK
2. w: The number of waits due to WAIT.
3. wRH: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wDA: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
5. wRP: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6. wCP: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7. wF: The number of waits that are inserted for a source-side access during a DMA flyby transfer.
8. m = 0 to 3
56
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW
T1
TRHW
TW
T2
TDAW
T3
TCPW
TW
TO1
TDAW
TO2
CLKOUT (Output)
<56>
A0 to A23 (Output)
<57>
<58>
Row address
<59>
Column address
Column address
<76>
<64>
<61>
<94>
<60>
RASn (Output)
<77>
<66>
<65>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<82>
<83>
RD (Output)
OE (Output)
<101>
<102>
<88>
<89>
<85>
WE (Output)
<92>
<105>
DMAAKm (Output)
IOWR (Output)
<106>
<107>
<35>
<34>
IORD (Output)
<32>
<25>
<33>
D0 to D15 (I/O)
Data
<24>
<24>
Data
<24>
<25>
<25>
WAIT (Input)
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 3 to 5, m = 0 to 3
Preliminary Data Sheet U15390EJ1V0DS
57
µPD703130
(i) CBR refresh timing
Parameter
Symbol
RAS precharge time
<61>
Condition
MIN.
tRP
MAX.
(1.5 + wRRW )T – 10
Unit
ns
RAS pulse width
<62>
tRAS
(1.5 + wRCW
Note
CAS hold time
<108>
tCHR
(1.5 + wRCW
Note
RAS precharge CAS hold time
<110>
tRPC
(0.5 + wRRW )T – 10
ns
CAS setup time
<113>
tCSR
T – 10
ns
)T – 10
ns
)T – 10
ns
Note At least one clock cycle is inserted by default for wRCW regardless of the settings of the RCW0 to RCW2
bits of the RWC register.
Remarks 1. T = tCYK
2. wRRW : The number of waits due to the RRW0 and RRW1 bits of the RWC register.
3. wRCW : The number of waits due to the RCW0 to RCW2 bits of the RWC register.
TRRW
T1
T2
TRCWNote
TRCW
T3
TI
CLKOUT (Output)
<61>
<62>
RASn (Output)
<110>
<110>
<113>
<108>
UCAS (Output)
LCAS (Output)
Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
2. n = 3 to 5
58
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(j) CBR self-refresh timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
CAS hold time
<114>
tCHS
−5
ns
RAS precharge time
<115>
tRPS
(1 + 2wSRW )T – 10
ns
Remarks 1. T = tCYK
2. wSRW : The number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (Output)
<115>
RASn (Output)
<114>
UCAS (Output)
LCAS (Output)
Output signals
other than above
Remarks 1. This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
2. The broken lines indicate high impedance.
3. n = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
59
µPD703130
(7) DMAC timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
DMARQn setup time (to CLKOUT ↑)
<116>
tSDRK
15
ns
DMARQn hold time (from CLKOUT ↑)
<117>
tHKDR1
2
ns
<118>
tHKDR2
Until DMAAKn ↓
ns
DMAAKn output delay time
(from CLKOUT ↓)
<119>
tDKDA
2
10
ns
DMAAKn output hold time
(from CLKOUT ↓)
<120>
tHKDA
2
10
ns
TCn output delay time
(from CLKOUT ↓)
<121>
tDKTC
2
10
ns
TCn output hold time
(from CLKOUT ↓)
<122>
tHKTC
2
10
ns
Remark n = 0 to 3
CLKOUT (Output)
<117>
<116>
<118>
DMARQn (Input)
<116>
<119>
<120>
DMAAKn (Output)
<122>
<121>
TCn (Output)
Remark n = 0 to 3
60
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
[MEMO]
Preliminary Data Sheet U15390EJ1V0DS
61
µPD703130
(8) Bus hold timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
HLDRQ setup time (to CLKOUT ↑)
<123>
tSHRK
15
ns
HLDRQ hold time (from CLKOUT ↑)
<124>
tHKHR
2
ns
Delay time from CLKOUT ↓ to HLDAK
<125>
tDKHA
2
HLDRQ high-level width
<126>
tWHQH
T + 17
ns
HLDAK low-level width
<127>
tWHAL
T–8
ns
Delay time from CLKOUT ↓ to bus float
<128>
tDKCF
Delay time from HLDAK ↑ to bus output
<129>
tDHAC
0
ns
Delay time from HLDRQ ↓ to HLDAK ↓
<130>
tDHQHA1
2.5T
ns
Delay time from HLDRQ ↑ to HLDAK ↑
<131>
tDHQHA2
0.5T
Remark T = tCYK
62
Preliminary Data Sheet U15390EJ1V0DS
10
10
1.5T
ns
ns
ns
µPD703130
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (Output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
HLDRQ (Input)
<125>
<125>
<130>
<131>
HLDAK (Output)
<127>
<128>
A0 to A23 (Output)
D0 to D15 (I/O)
Address
<129>
Undefined
Data
CSn/RASm (Output)
BCYST (Output)
RD (Output)
WE (Output)
UCAS (Output)
LCAS (Output)
WAIT (Input)
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 3 to 5, m = 3 to 5
Preliminary Data Sheet U15390EJ1V0DS
63
µPD703130
(9) Interrupt timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
NMI high-level width
<132>
tWNIH
500
ns
NMI low-level width
<133>
tWNIL
500
ns
INTPn high-level width
<134>
tWITH
4T + 10
ns
INTPn low-level width
<135>
tWITL
4T + 10
ns
Remarks 1. n = 100 to 103, 110 to 113, 130
2. T = tCYK
<132>
<133>
<134>
<135>
NMI (Input)
INTPn (Input)
Remark n = 100 to 103, 110 to 113, 130
(10) RPU timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
TI13 high-level width
<136>
tWTIH
3T + 18
ns
TI13 low-level width
<137>
tWTIL
3T + 18
ns
TCLR1n high-level width
<138>
tWTCH
3T + 18
ns
TCLR1n low-level width
<139>
tWTCL
3T + 18
ns
Remarks 1. n = 0 to 2
2. T = tCYK
<136>
<137>
<138>
<139>
TI13 (Input)
TCLR1n (Input)
Remark n = 0 to 2
64
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<140>
tCYSK0
Output
250
ns
SCKn high-level width
<141>
tWSK0H
Output
0.5tCYSK0 – 20
ns
SCKn low-level width
<142>
tWSK0L
Output
0.5tCYSK0 – 20
ns
RXDn setup time (to SCKn ↑)
<143>
tSRXSK
30
ns
RXDn hold time (from SCKn ↑)
<144>
tHSKRX
0
ns
TXDn output delay time (from SCKn ↓)
<145>
tDSKTX
TXDn output hold time (from SCKn ↑)
<146>
tHSKTX
20
0.5tCYSK0 – 5
ns
ns
Remark n = 0, 1
<140>
<142>
<141>
SCKn (I/O)
<143>
RXDn (Input)
<144>
Input data
<145>
TXDn (Output)
<146>
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
Preliminary Data Sheet U15390EJ1V0DS
65
µPD703130
(12) CSI0, CSI1 timing
(a) Master mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
tCYSK1
Output
100
ns
SCKn high-level width
<148>
tWSK1H
Output
0.5tCYSK1 – 20
ns
SCKn low-level width
<149>
tWSK1L
Output
0.5tCYSK1 – 20
ns
SIn setup time (to SCKn ↑)
<150>
tSSISK
30
ns
SIn hold time (from SCKn ↑)
<151>
tHSKSI
0
ns
SOn output delay time (from SCKn ↓)
<152>
tDSKSO
SOn output hold time (from SCKn ↑)
<153>
tHSKSO
20
0.5tCYSK1 – 5
ns
ns
Remark n = 0, 1
(b) Slave mode
Parameter
Symbol
Condition
MIN.
MAX.
Unit
SCKn cycle
<147>
tCYSK1
Input
100
ns
SCKn high-level width
<148>
tWSK1H
Input
30
ns
SCKn low-level width
<149>
tWSK1L
Input
30
ns
SIn setup time (to SCKn ↑)
<150>
tSSISK
10
ns
SIn hold time (from SCKn ↑)
<151>
tHSKSI
10
ns
SOn output delay time (from SCKn ↓)
<152>
tDSKSO
SOn output hold time (from SCKn ↑)
<153>
tHSKSO
30
tWSK1H
Remark n = 0, 1
<147>
<149>
<148>
SCKn (I/O)
<150>
Sln (Input)
<151>
Input data
<152>
SOn (Output)
<153>
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
66
Preliminary Data Sheet U15390EJ1V0DS
ns
ns
µPD703130
A/D Converter Characteristics ( TA = –40 to +85°°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V ±10%, VSS = 0 V,
HVDD – 0.5 V ≤ AVDD ≤ HVDD, output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
10
Unit
Resolution
–
Overall error
–
±4
LSB
Quantization error
–
±1/2
LSB
10
µs
Conversion time
tCONV
5
Sampling time
tSAMP
Conversion
Note
clock
/6
bit
ns
Zero scale error
–
±4
LSB
Scale error
–
±4
LSB
Linearity error
–
±3
LSB
AVREF + 0.3
V
Analog input voltage
VIAN
Analog input resistance
RAN
AVREF input voltage
AVREF
AVREF input current
AVDD current
−0.3
2
AVREF = AVDD
4.5
MΩ
5.5
V
AIREF
2.0
mA
AIDD
6
mA
Note Conversion clock is the number of clocks set by the ADM1 register.
Preliminary Data Sheet U15390EJ1V0DS
67
µPD703130
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C D
Q
R
26
25
100
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
16.00±0.20
B
14.00±0.20
C
14.00±0.20
D
16.00±0.20
F
1.00
G
1.00
H
0.22 +0.05
−0.04
I
J
0.08
0.50 (T.P.)
K
1.00±0.20
L
0.50±0.20
M
0.17 +0.03
−0.07
N
0.08
P
1.40±0.05
Q
0.10±0.05
R
3° +7°
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
68
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
5. RECOMMENDED SOLDERING CONDITIONS
TBD
Preliminary Data Sheet U15390EJ1V0DS
69
µPD703130
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Reference materials
Electrical Characteristics for Microcomputer (U15170J
Note
)
Note This document number is that of Japanese version.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MS1, V850E/MS2, and V850 Family are trademarks of NEC Corporation.
70
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
Preliminary Data Sheet U15390EJ1V0DS
71
µPD703130
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
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• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
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of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
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Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8