Revised April 2002 CD4029BC Presettable Binary/Decade Up/Down Counter General Description Features The CD4029BC is a presettable up/down counter which counts in either binary or decade mode depending on the voltage level applied at binary/decade input. When binary/ decade is at logical “1”, the counter counts in binary, otherwise it counts in decade. Similarly, the counter counts up when the up/down input is at logical “1” and vice versa. ■ Wide supply voltage range: A logical “1” preset enable signal allows information at the “jam” inputs to preset the counter to any state asynchronously with the clock. The counter is advanced one count at the positive-going edge of the clock if the carry in and preset enable inputs are at logical “0”. Advancement is inhibited when either or both of these two inputs is at logical “1”. The carry out signal is normally at logical “1” state and goes to logical “0” state when the counter reaches its maximum count in the “up” mode or the minimum count in the “down” mode provided the carry input is at logical “0” state. 3V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS ■ Parallel jam inputs ■ Binary or BCD decade up/down counting All inputs are protected against static discharge by diode clamps to both VDD and VSS. Ordering Code: Order Number Package Number Package Description CD4029BCWM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide CD4029BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4029BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View © 2002 Fairchild Semiconductor Corporation DS005960 www.fairchildsemi.com CD4029BC Presettable Binary/Decade Up/Down Counter October 1987 CD4029BC Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) (Note 2) −0.5V to +18 VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.5V to VDD + 0.5 VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW Symbol IDD VOL VOH VIL VIH IOL IOH IIN Parameter Quiescent Device Current Note 2: VSS = 0V unless otherwise specified. 260°C DC Electrical Characteristics −55°C to +125°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15 VDC Input Voltage (VIN) (Note 2) −55°C Conditions Min +25°C Max Min Typ +125°C Max Min Max VDD = 5V 5 5 150 VDD = 10V 10 10 300 VDD = 15V 20 20 600 LOW Level |IO| < 1 µA Output Voltage VDD = 5V 0.05 0 0.05 0.05 VDD = 10V 0.05 0 0.05 0.05 VDD = 15V 0.05 0 0.05 0.05 HIGH Level |IO| < 1 µA Output Voltage VDD = 5V 4.95 4.95 5 VDD = 10V 9.95 9.95 10 9.95 VDD = 15V 14.95 14.95 15 14.95 µA V 4.95 V LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 Input Voltage VDD = 10V, VO = 1V or 9V 3.0 3.0 3.0 VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0 1.5 HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5 Input Voltage VDD = 10V, VO = 1V or 9V 7.0 7.0 7.0 VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0 LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 Current (Note 3) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9 VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4 HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 Current (Note 3) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9 VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4 Input Current Units V V 0.36 mA mA VDD = 15V, VIN = 0V −0.1 −10−5 −0.1 −1.0 VDD = 15V, VIN = 15V 0.1 10−5 0.1 1.0 µA Note 3: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4029BC Absolute Maximum Ratings(Note 1) CD4029BC AC Electrical Characteristics (Note 4) TA = 25°C, CL = 50 pF, RL = 200k, Input trCL = tfCL = 20 ns, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units CLOCKED OPERATION tPHL or tPLH tPHL or tPLH tPHL or tPLH Propagation Delay Time VDD = 5V 200 400 to Q Outputs VDD = 10V 85 170 VDD = 15V 70 140 Propagation Delay Time VDD = 5V 320 640 to Carry Output VDD = 10V 135 270 VDD = 15V 110 220 Propagation Delay Time tTHL or tTLH tWH or tWL trCL or tfCL tSU VDD = 5V 285 570 120 240 VDD = 15V 95 190 Transition Time/Q VDD = 5V 100 200 or Carry Output VDD = 10V 50 100 VDD = 15V 40 80 Minimum Clock VDD = 5V 160 320 Pulse Width VDD = 10V 70 135 VDD = 15V 55 110 fCL Maximum Clock Rise VDD = 5V 15 and Fall Time VDD = 10V 10 VDD = 15V 5 Minimum Set-Up Time Maximum Clock Frequency ns CL = 15 pF VDD = 10V to Carry Output ns ns ns ns µs VDD = 5V 180 360 VDD = 10V 70 140 VDD = 15V 55 110 VDD = 5V 1.5 3.1 VDD = 10V 3.7 7.4 VDD = 15V 4.5 9 ns MHz CIN Average Input Capacitance Any Input 5 CPD Power Dissipation Capacitance Per Package (Note 5) 65 7.5 Propagation Delay Time VDD = 5V 285 570 to Q output VDD = 10V 115 230 VDD = 15V 95 195 pF pF PRESET ENABLE OPERATION tPHL or tPLH tPHL or tPLH tWH tREM Propagation Delay Time VDD = 5V 400 800 to Carry Output VDD = 10V 165 330 VDD = 15V 135 260 Minimum Preset Enable VDD = 5V 80 160 Pulse Width VDD = 10V 30 60 VDD = 15V 25 50 Minimum Preset Enable VDD = 5V 150 300 Removal Time VDD = 10V 60 120 VDD = 15V 50 100 Propagation Delay Time VDD = 5V 265 530 to Carry Output VDD = 10V 110 220 VDD = 15V 90 180 ns ns ns ns CARRY INPUT OPERATION tPHL or tPLH tPHL, tPLH Propagation Delay Time to Carry Output ns CL = 15 pF VDD = 5V 200 400 VDD = 10V 85 170 VDD = 15V 70 140 ns Note 4: *AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 74C Family Characteristics application note, AN-90. www.fairchildsemi.com 4 CD4029BC Logic Waveforms Decade Mode Binary Mode 5 www.fairchildsemi.com CD4029BC Switching Time Waveforms Cascading Packages Parallel Clocking Ripple Clocking Carry out lines at the 2nd or later stages may have a negative-going spike due to differential internal delays. These spikes do not affect counter operation, but if the carry out is used to trigger external circuitry the carry out should be gated with the clock. www.fairchildsemi.com 6 CD4029BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M16B 7 www.fairchildsemi.com CD4029BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 CD4029BC Presettable Binary/Decade Up/Down Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com