Revised January 2005 MM74HC393 Dual 4-Bit Binary Counter General Description Features The MM74HC393 counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology. The MM74HC393 contains two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter. ■ Typical operating frequency: 50 MHz Each of the two 4-bit counters is incremented on the HIGHto-LOW transition (negative edge) of the clock input, and each has an independent clear input. When clear is set HIGH all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations. ■ Low quiescent supply current: 80 µA maximum (74HC Series) ■ Typical propagation delay: 13 ns (Ck to QA) ■ Wide operating supply voltage range: 2–6V ■ Low input current: <1 µA ■ Fanout of 10 LS-TTL loads Each of the counters outputs can drive 10 low power Schottky TTL equivalent loads. This counter is functionally as well as pin equivalent to the 74LS393. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number Package Package Description Number MM74HC393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC393SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC393MTC MM74HC393N MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 2005 Fairchild Semiconductor Corporation DS005337 www.fairchildsemi.com MM74HC393 Dual 4-Bit Binary Counter September 1983 MM74HC393 Absolute Maximum Ratings Recommended Operating Conditions (Note 2) (Note 1) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA Storage Temperature Range (TSTG) Min Max Units 2 6 V 0 VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT ) Operating Temperature Range (TA) Input Rise or Fall Times −65°C to +150°C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Lead Temperature (TL) DC Electrical Characteristics Symbol VIH VIL VOH Parameter Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. 260°C (Soldering 10 seconds) Conditions (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA Supply Current IOUT = 0 µA VIN = VIH or VIL IIN Maximum Input Current ICC Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 MM74HC393 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns Symbol Parameter Conditions Guaranteed Typ Units Limit fMAX Maximum Operating Frequency 50 30 MHz tPHL, tPLH Maximum Propagation Delay, Clock A to QA 13 20 ns tPHL, tPLH Maximum Propagation Delay, Clock A to QB 19 35 ns tPHL, tPLH Maximum Propagation Delay, Clock A to QC 23 42 ns tPHL, tPLH Maximum Propagation Delay, Clock A to QD 27 50 ns tPHL Maximum Propagation Delay, Clear to any Q 15 28 ns tREM Minimum Removal Time −2 5 ns tW Minimum Pulse Width Clear or Clock 10 16 ns AC Electrical Characteristics CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol fMAX Parameter Conditions Maximum Operating Frequency tPHL, tPLH Maximum Propagation Delay Clock A to QA tPHL, tPLH Maximum Propagation Delay Clock A to QB tPHL, tPLH Maximum Propagation Delay Clock A to QC tPHL, tPLH Maximum Propagation Delay Clock to QD tPHL Maximum Propagation Delay Clear to any Q tREM tW TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0V 5 4 3 4.5V 27 21 18 MHz 6.0V 31 24 20 MHz 2.0V 45 120 150 180 ns 4.5V 15 24 30 35 ns 6.0V 13 21 26 31 ns 2.0V 68 190 240 285 ns 4.5V 23 38 47 57 ns 6.0V 20 32 40 48 ns 2.0V 90 240 300 360 ns 4.5V 30 48 60 72 ns 6.0V 26 41 51 61 ns 2.0V 100 290 360 430 ns 4.5V 35 58 72 87 ns 6.0V 30 50 62 75 ns 2.0V 54 165 210 250 ns 4.5V 18 33 41 49 ns 6.0V 15 28 35 42 ns 2.0V 25 25 25 ns Removal Time 4.5V 5 5 5 ns 6.0V 5 5 5 ns Minimum Pulse Width 2.0V 30 80 100 120 ns Clear or Clock 4.5V 10 16 20 24 ns 6.0V 9 14 18 20 ns 2.0V 30 75 95 110 ns Rise and Fall Time CPD TA = 25°C Typ Minimum Clear tTHL, tTLH Maximum Output tr, tf VCC 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns Maximum Input 1000 1000 1000 ns Rise and Fall Time 500 500 500 ns 400 400 400 ns Power Dissipation (per counter) 42 pF Capacitance (Note 5) CIN Maximum Input Capacitance 5 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC. 3 www.fairchildsemi.com MM74HC393 Logic Timing Waveforms www.fairchildsemi.com 4 MM74HC393 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A 5 www.fairchildsemi.com MM74HC393 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D www.fairchildsemi.com 6 MM74HC393 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 7 www.fairchildsemi.com MM74HC393 Dual 4-Bit Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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