Revised August 2001 74VHC161 4-Bit Binary Counter with Asynchronous Clear General Description Features The VHC161 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC161 is a high-speed synchronous modulo16 binary counter. This device is synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The VHC161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ High Speed: fMAX = 185 MHz (typ) at TA = 25°C ■ Synchronous counting and loading ■ High-speed synchronous expansion ■ Low power dissipation: ICC = 4 µA (max) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (min) ■ Power down protection provided on all inputs ■ Low noise: VOLP = 0.8V (max) ■ Pin and function compatible with 74HC161 Ordering Code: Order Number 74VHC161M 74VHC161SJ 74VHC161MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 74VHC161N N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2001 Fairchild Semiconductor Corporation DS011635 www.fairchildsemi.com 74VHC161 4-Bit Binary Counter with Asynchronous Clear August 1993 74VHC161 Connection Diagram Pin Descriptions Pin Names Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Asynchronous Master Reset Input P0–P3 Parallel Data Inputs PE Parallel Enable Inputs Q0–Q3 Flip-Flop Outputs TC Terminal Count Output Functional Description nous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The VHC161 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the VHC161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs—Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET)—determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. The VHC161 uses D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchro- FIGURE 1. Multistage Counter with Ripple Carry FIGURE 2. Multistage Counter with Lookahead Carry www.fairchildsemi.com 2 74VHC161 State Diagram Mode Select Table Action on the Rising PE CET CEP Clock Edge ( MR L X X X Reset (Clear) H L X X Load (Pn→Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) ) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74VHC161 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC ) −0.5V to +7.0V DC Input Voltage (VIN) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±50 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150 °C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260 °C (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL VOL TA = 25°C Min TA = −40°C to +85°C Typ Max Min 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH VCC (V) Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 VIN = VIH IOH = −50 µA 2.0 0.0 0.1 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 Input Leakage Current Quiescent Supply Current or VIL IOH = −4 mA V LOW Level ICC V V Output Voltage IIN Conditions V 3.0 − 5.5 HIGH Level Units IOH = −8 mA VIN = VIH IOL = 50 µA V or VIL IOL = 4 mA 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND V IOL = 8 mA Noise Characteristics Symbol Parameter VOLP Quiet Output Maximum (Note 3) Dynamic VOL VOLV Quiet Output Minimum (Note 3) Dynamic VOL VIHD Minimum HIGH Level (Note 3) Dynamic Input Voltage VILD Maximum LOW Level (Note 3) Dynamic Input Voltage TA = 25°C VCC Conditions Typ Limits 5.0 0.4 0.8 V CL = 50 pF 5.0 −0.4 −0.8 V CL = 50 pF 5.0 3.5 V CL = 50 pF 5.0 1.5 V CL = 50 pF Note 3: Parameter guaranteed by design. www.fairchildsemi.com Units (V) 4 Symbol Parameter tPLH Propagation Delay tPHL Time (CP–Qn) TA = 25°C VCC (V) Min 3.3 ± 0.3 Max Min Max 8.3 12.8 1.0 15.0 10.8 16.3 1.0 18.5 4.9 8.1 1.0 9.5 6.4 10.1 1.0 11.5 8.7 13.6 1.0 16.0 11.2 17.1 1.0 19.5 5.0 ± 0.5 tPLH Propagation Delay tPHL Time (CP–TC, Count) 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay tPHL Time (CP–TC, Load) 3.3 ± 0.3 Propagation Delay tPHL Time (CET–TC) 3.3 ± 0.3 Propagation Delay Time (MR –Qn) 3.3 ± 0.3 Propagation Delay Time (MR –TC) 3.3 ± 0.3 Maximum Clock Frequency 3.3 ± 0.3 5.0 ± 0.5 9.5 1.0 11.5 17.2 1.0 20.0 1.0 23.5 6.2 10.3 1.0 12.0 7.7 12.3 1.0 14.0 7.5 12.3 1.0 14.5 10.5 15.8 1.0 18.0 4.9 8.1 1.0 9.5 6.4 10.1 1.0 11.5 8.9 13.6 1.0 16.0 11.2 17.1 1.0 19.5 5.5 9.0 1.0 10.5 7.0 11.0 1.0 12.5 8.4 13.2 1.0 15.5 10.9 16.7 1.0 19.0 5.0 ± 0.5 fMAX 1.0 10.1 20.7 5.0 ± 0.5 tPHL 8.1 6.4 11.0 5.0 ± 0.5 tPHL 4.9 13.5 5.0 ± 0.5 tPLH TA = −40° to +85°C Typ 5.0 8.6 1.0 10.0 6.5 10.6 1.0 12.0 80 130 70 55 85 50 135 185 115 95 125 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 23 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz 85 10 Units 10 Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 4) Note 4: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC. When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ∆ICC which is obtained from the following formula: CQ0–C Q3 and CTC are the capacitances at Q0–Q3 and TC, respectively. F CP is the input frequency of the CP. 5 www.fairchildsemi.com 74VHC161 AC Electrical Characteristics 74VHC161 AC Operating Requirements Symbol tS tS tS tH tH tH Parameter VCC (Note 5) (V) TA = 25°C Typ TA = −40°C to +85°C Guaranteed Minimum Minimum Setup Time 3.3 5.5 6.5 (Pn–CP) 5.0 4.5 4.5 Minimum Setup Time 3.3 8.0 9.5 (PE –CP) 5.0 5.0 6.0 Minimum Setup Time 3.3 7.5 9.0 (CEP or CET–CP) 5.0 5.0 6.0 Minimum Hold Time 3.3 1.0 1.0 (Pn–CP) 5.0 1.0 1.0 Minimum Hold Time 3.3 1.0 1.0 (PE –CP) 5.0 1.0 1.0 Minimum Hold Time 3.3 1.0 1.0 (CEP or CET–CP) 5.0 1.0 1.0 tW(L) Minimum Pulse Width 3.3 5.0 5.0 tW(H) CP (Count) 5.0 5.0 5.0 tW(L) Minimum Pulse Width 3.3 5.0 5.0 (MR) 5.0 5.0 5.0 tREC Minimum Removal 3.3 2.5 2.5 Time 5.0 1.5 1.5 Note 5: VCC is 3.3 ± 0.3V or 5.0 ± 0.5V www.fairchildsemi.com 6 Units ns ns ns ns ns ns ns ns ns 74VHC161 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com 74VHC161 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 8 74VHC161 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 9 www.fairchildsemi.com 74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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