a CMOS Low Voltage 4 V Dual SPST Switches ADG721/ADG722/ADG723 FEATURES +1.8 V to +5.5 V Single Supply 4 V (Max) On Resistance Low On-Resistance Flatness –3 dB Bandwidth >200 MHz Rail-to-Rail Operation 8-Lead mSOIC Package Fast Switching Times tON 20 ns tOFF 10 ns Low Power Consumption (<0.1 mW) TTL/CMOS Compatible FUNCTIONAL BLOCK DIAGRAMS ADG722 ADG721 S1 S1 IN1 IN1 D1 D1 D2 IN2 D2 IN2 S2 S2 ADG723 APPLICATIONS Battery Powered Systems Communication Systems Sample Hold Systems Audio Signal Routing Video Switching Mechanical Reed Relay Replacement S1 IN1 D1 D2 IN2 S2 SWITCHES SHOWN FOR A LOGIC "0" INPUT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG721, ADG722 and ADG723 are monolithic CMOS SPST switches. These switches are designed on an advanced submicron process that provides low power dissipation yet gives high switching speed, low On resistance and low leakage currents. 1. +1.8 V to +5.5 V Single Supply Operation. The ADG721, ADG722 and ADG723 offers high performance, including low on resistance and fast switching times and is fully specified and guaranteed with +3 V and +5 V supply rails. The ADG721, ADG722 and ADG723 are designed to operate from a single +1.8 V to +5.5 V supply, making them ideal for use in battery powered instruments and with the new generation of DACs and ADCs from Analog Devices. 2. Very Low RON (4 Ω max at 5 V, 10 Ω max at 3 V). At 1.8 V operation, RON is typically 40 Ω over the temperature range. The ADG721, ADG722 and ADG723 contain two independent single-pole/single-throw (SPST) switches. The ADG721 and ADG722 differ only in that both switches are normally open and normally closed respectively. While in the ADG723, Switch 1 is normally open and Switch 2 is normally closed. 3. Low On-Resistance Flatness. 4. –3 dB Bandwidth >200 MHz. 5. Low Power Dissipation. CMOS construction ensures low power dissipation. 6. Fast tON /tOFF. 7. 8-Lead µSOIC. Each switch of the ADG721, ADG722 and ADG723 conducts equally well in both directions when on. The ADG723 exhibits break-before-make switching action. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADG721/ADG722/ADG723–SPECIFICATIONS1 (VDD = +5 V 6 10%, GND = 0 V. All specifications –408C to +858C, unless otherwise noted.) Parameter B Version – 408C to +258C +858C ANALOG SWITCH Analog Signal Range On Resistance (RON) 4 On Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) 0 V to VDD 5 V Ω max 1.0 Ω typ Ω max Ω typ Ω max 0.3 0.85 1.5 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) ± 0.01 ± 0.25 ± 0.01 ± 0.25 ± 0.01 ± 0.25 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 14 Units VS = 0 V to VDD, IS = –10 mA, Test Circuit 1 VS = 0 V to VDD, IS = –10 mA VS = 0 V to VDD, IS = –10 mA VDD = +5.5 V VS = 4.5 V/1 V, VD = 1 V/4.5 V Test Circuit 2 VS = 4.5 V/1 V, VD = 1 V/4.5 V Test Circuit 2 VS = VD = 1 V, or VS = VD = 4.5 V Test Circuit 3 ± 0.35 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 µA typ µA max VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V, Test Circuit 5 VS = 2 V; RS = 0 Ω, CL = 1 nF, Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 8 RL = 50 Ω, CL = 5 pF, Test Circuit 9 ± 0.35 ± 0.35 tOFF 6 Break-Before-Make Time Delay, tD (ADG723 Only) Charge Injection 7 2 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –60 –80 dB typ dB typ Channel-to-Channel Crosstalk –77 –97 dB typ dB typ Bandwidth –3 dB CS (OFF) CD (OFF) CD, CS (ON) 200 7 7 18 MHz typ pF typ pF typ pF typ 20 10 1 POWER REQUIREMENTS IDD Test Conditions/Comments µA typ µA max 0.001 1.0 VDD = +5.5 V Digital Inputs = 0 V or 5 V NOTES 1 Temperature ranges are as follows: B Version, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG721/ADG722/ADG723 1 SPECIFICATIONS (V DD = +3 V 6 10%, GND = 0 V. All specifications –408C to +858C, unless otherwise noted.) Parameter B Version – 408C to +258C +858C ANALOG SWITCH Analog Signal Range On Resistance (RON) 6.5 On Resistance Match Between Channels (∆RON) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) Test Conditions/Comments 10 V Ω typ Ω max VS = 0 V to VDD, IS = –10 mA Test Circuit 1 1.0 3.5 Ω typ Ω max Ω typ VS = 0 V to VDD, IS = –10 mA ± 0.35 nA typ nA max nA typ nA max nA typ nA max VDD = +3.3 V VS = 3 V/1 V, VD = 1 V/3 V Test Circuit 2 VS = 3 V/1 V, VD = 1 V/3 V Test Circuit 2 VS = VD = 1 V, or 3 V Test Circuit 3 2.0 0.4 V min V max ± 0.1 µA typ µA max VIN = VINL or VINH RL = 300 Ω, CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 2 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 2 V, Test Circuit 5 VS = 1.5 V; RS = 0 Ω, CL = 1 nF, Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 8 RL = 50 Ω, CL = 5 pF, Test Circuit 9 0 V to VDD 0.3 On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Units ± 0.01 ± 0.25 ± 0.01 ± 0.25 ± 0.01 ± 0.25 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH 0.005 DYNAMIC CHARACTERISTICS2 tON 16 ± 0.35 ± 0.35 tOFF 7 Break-Before-Make Time Delay, tD (ADG723 Only) Charge Injection 7 2 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –60 –80 dB typ dB typ Channel-to-Channel Crosstalk –77 –97 dB typ dB typ Bandwidth –3 dB 200 MHz typ CS (OFF) CD (OFF) CD, CS (ON) 7 7 18 pF typ pF typ pF typ 24 11 1 POWER REQUIREMENTS IDD µA typ µA max 0.001 1.0 NOTES 1 Temperature ranges are as follows: B Version, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 –3– VS = 0 V to VDD, IS = –10 mA VDD = +3.3 V Digital Inputs = 0 V or 3 V ADG721/ADG722/ADG723 ABSOLUTE MAXIMUM RATINGS 1 TERMINOLOGY (TA = +25°C unless otherwise noted) VDD GND S D IN RON ∆RON Most Positive Power Supply Potential. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Ohmic resistance between D and S. On resistance match between any two channels i.e., RON max – RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source leakage current with the switch “OFF.” IS (OFF) ID (OFF) Drain leakage current with the switch “OFF.” ID, IS (ON) Channel leakage current with the switch “ON.” VD (VS) Analog voltage on terminals D, S. CS (OFF) “OFF” Switch Source Capacitance. CD (OFF) “OFF” Switch Drain Capacitance. CD, CS (ON) “ON” Switch Capacitance. tON Delay between applying the digital control input and the output switching on. tOFF Delay between applying the digital control input and the output switching off. tD “OFF” time or “ON” time measured between the 90% points of both switches, When switching from one address state to another. (ADG723 Only) Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Charge A measure of the glitch impulse transferred Injection during switching. VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog, Digital Inputs2 . . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C µSOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. Table I. Truth Table (ADG721/ADG722) ADG721 In ADG722 In Switch Condition 0 1 1 0 OFF ON Table II. Truth Table (ADG723) Logic Switch 1 Switch 2 0 1 OFF ON ON OFF PIN CONFIGURATION 8-Lead mSOIC (RM-8) S1 1 D1 2 ADG721/ 722/723 8 VDD 7 IN1 D2 TOP VIEW GND 4 (Not to Scale) 5 S2 IN2 3 6 ORDERING GUIDE Model Temperature Range Brand* Package Description Package Option ADG721BRM ADG722BRM ADG723BRM –40°C to +85°C –40°C to +85°C –40°C to +85°C S6B S7B S8B µSOIC µSOIC µSOIC RM-8 RM-8 RM-8 *Brand = Due to package size limitations, these three characters represent the part number. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG721/ADG722/ADG723 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics– ADG721/ADG722/ADG723 1m 6.0 5.5 TA = +258C VDD = +2.7V VDD = +5V 100m 5.0 4.5 VDD = +4.5V 10m VDD = +3.0V 3.5 ISUPPLY – A RON – V 4.0 3.0 2.5 VDD = +5.0V 2.0 1m 100n 1.5 10n 1.0 0.5 1n 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 100 10 5.0 1k 10k 100k FREQUENCY – Hz VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 4. Supply Current vs. Input Switching Frequency Figure 1. On Resistance as a Function of VD (V S) Single Supplies 6.0 –30 +858C VDD = +3V VDD = +3V, +5V –40 OFF ISOLATION – dB 5.0 RON – V 4.0 +258C 3.0 –408C 2.0 1.0 –50 –60 –70 –80 –90 –100 10k 0 0 0.5 1.0 1.5 2.0 2.5 3.0 100k VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures VDD = +3 V 1M 10M FREQUENCY – Hz 100M Figure 5. Off Isolation vs. Frequency 6.0 –30 VDD = +3V, +5V VDD = +5V 5.5 –40 5.0 4.5 +258C CROSSTALK – dB –50 4.0 RON – V 10M 1M +858C 3.5 3.0 2.5 2.0 –60 –70 –80 –408C 1.5 –90 1.0 –100 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –110 10k 5.0 VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures VDD = +5 V REV. 0 100k 10M 1M FREQUENCY – Hz Figure 6. Crosstalk vs. Frequency –5– 100M ADG721/ADG722/ADG723 –6 VDD = +5V ON RESPONSE – dB –7 –8 –9 –10 –11 –12 100 1k 10k 100k 1M FREQUENCY – Hz 100M 10M Figure 7. On Response vs. Frequency Test Circuits IDS V1 IS (OFF) S VS D A ID (OFF) S D VS RON = V1/IDS Test Circuit 1. On Resistance ID (ON) S A D VS VD Test Circuit 2. Off Leakage A VD Test Circuit 3. On Leakage VDD 0.1mF VIN ADG721 50% 50% VIN ADG722 50% 50% VDD S VS VOUT D RL 300V IN CL 35pF 90% VOUT 90% GND tOFF tON Test Circuit 4. Switching Times VDD 0.1mF VIN VDD VS1 VS2 S1 D1 S2 VIN VOUT1 VOUT2 D2 RL2 300V IN1, IN2 50% 0V RL1 300V CL1 35pF 50% 90% VOUT1 90% 0V CL2 35pF GND 90% VOUT2 90% 0V tD tD Test Circuit 5. Break-Before-Make Time Delay, tD (ADG723 Only) –6– REV. 0 ADG721/ADG722/ADG723 VDD SW ON SW OFF VDD RS VS S D VIN VOUT CL 1nF IN VOUT DVOUT QINJ = CL 3 DVOUT GND Test Circuit 6. Charge Injection VDD VDD 0.1mF 0.1mF VDD S VDD D S VOUT D RL 50V VS VIN IN VS GND VDD VDD NC 50V D VIN1 VIN2 S D GND VOUT RL 50V CHANNEL-TO-CHANNEL CROSSTALK = 20 3 LOG VS/VOUT Test Circuit 8. Channel-to-Channel Crosstalk REV. 0 IN Test Circuit 9. Bandwidth 0.1mF VS VIN GND Test Circuit 7. Off Isolation S VOUT RL 50V –7– ADG721/ADG722/ADG723 Off Isolation The ADG721/ADG722/ADG723 belongs to Analog Devices’ new family of CMOS switches. This series of general purpose switches have improved switching times, lower on resistance, higher bandwidths, low power consumption and low leakage currents. Off isolation is a measure of the input signal coupled through an off switch to the switch output. The capacitance, CDS, couples the input signal to the output load, when the switch is off as shown in Figure 9. C3294–8–4/98 APPLICATIONS INFORMATION CDS ADG721/ADG722/ADG723 Supply Voltages Functionality of the ADG721/ADG722/ADG723 extends from +1.8 V to +5.5 V single supply, which makes it ideal for battery powered instruments, where important design parameters are power efficiency and performance. S D VOUT VIN It is important to note that the supply voltage effects the input signal range, the on resistance and the switching times of the part. By taking a look at the typical performance characteristics and the specifications, the effects of the power supplies can be clearly seen. CD CLOAD RLOAD Figure 9. Off Isolation Is Affected by External Load Resistance and Capacitance The larger the value of CDS, larger values of feedthrough will be produced. The typical performance characteristic graph of Figure 5 illustrates the drop in off isolation as a function of frequency. From dc to roughly 1 MHz, the switch shows better than –80 dB isolation. Up to frequencies of 10 MHz, the off isolation remains better than –60 dB. As the frequency increases, more and more of the input signal is coupled through to the output. Off isolation can be maximized by choosing a switch with the smallest CDS as possible. The values of load resistance and capacitance also affect off isolation, as they contribute to the coefficients of the poles and zeros in the transfer function of the switch when open. For VDD = +1.8 V, on resistance is typically 40 Ω over the temperature range. On Response vs. Frequency Figure 8 illustrates the parasitic components that affect the ac performance of CMOS switches (the switch is shown surrounded by a box). Additional external capacitances will further degrade some performance. These capacitances affect feedthrough, crosstalk and system bandwidth. CDS S s(RLOAD CDS ) A(s) = s(RLOAD ) (CLOAD + CD + CDS ) + 1 D VOUT RON VIN CD CLOAD RLOAD Figure 8. Switch Represented by Equivalent Parasitic Components The transfer function that describes the equivalent diagram of the switch (Figure 8) is of the form (A)s shown below. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead mSOIC (RM-8) s(RON CDS ) + 1 A(s) = RT s(RON CT RT ) + 1 0.122 (3.10) 0.114 (2.90) CT = CLOAD + CD + CDS RT = RLOAD/(R LOAD + R ON) 8 5 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) 1 The signal transfer characteristic is dependent on the switch channel capacitance, CDS. This capacitance creates a frequency zero in the numerator of the transfer function A(s). Because the switch on resistance is small, this zero usually occurs at high frequencies. The bandwidth is a function of the switch output capacitance combined with CDS and the load capacitance. The frequency pole corresponding to these capacitances appears in the denominator of A(s). PRINTED IN U.S.A. where: 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33° 27° 0.028 (0.71) 0.016 (0.41) The dominant effect of the output capacitance, CD, causes the pole breakpoint frequency to occur first. Therefore, in order to maximize bandwidth a switch must have a low input and output capacitance and low on resistance. The On Response vs. Frequency plot for the ADG721/ADG722/ADG723 can be seen in Figure 7. –8– REV. 0