INFINEON HYS64V4120GU-10

3.3V 4M x 64-Bit 2 BANK SDRAM Module
3.3V 4M x 72-Bit 2 BANK SDRAM Module
HYS64V4120GU-10
HYS72V4120GU-10
168 pin unbuffered DIMM Modules
•
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module
for PC main memory applications
•
2 bank 4M x 64, 4M x 72 organisation
•
Optimized for byte-write non-parity or ECC applications
•
Fully PC66 layout compatible
•
JEDEC standard Synchronous DRAMs (SDRAM)
•
Performance:
-10
fCK
Max. Clock frequency
tAC
Max. access time from clock
66 MHz @ CL=2
100 MHz @ CL=3
9 ns @ CL=2
8 ns @ CL=3
•
Single +3.3V(± 0.3V ) power supply
•
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
•
Auto Refresh (CBR) and Self Refresh
•
Decoupling capacitors mounted on substrate
•
All inputs, outputs are LVTTL compatible
•
Serial Presence Detect with E 2PROM
•
Utilizes 16 / 18 2M x 8 SDRAMs in TSOPII-44 packages
•
4096 refresh cycles every 64 ms
•
Gold contact pad
•
Card Size: 133,35 mm x 29.21 mm x 4,00 mm for HYS64(72)V4120GU
Semiconductor Group
1
2.98
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
The HYS64(72)V4120GU-10 are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) which are organised as 4M x 64 and 4M x 72 in two banks high speed memory arrays
designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs
use 16 2M x 8 SDRAMs for the 4M x 64 organisation and additional two SDRAMs for the 4M x 72
organisation. Decoupling capacitors are mounted on the PC board.
The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I 2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm
long footprint. This SDRAM module is available with a board-height of 1,15“.
Ordering Information
Type
Package
Descriptions
Module
Height
HYS 64V4120GU-10
L-DIM-168-25
PC66 4M x 64 2 bank SDRAM module
1,15“
HYS 72V4120GU-10
L-DIM-168-25
PC66 4M x 72 2 bank SDRAM module
1,15“
Pin Names
A0-A10
BS (A11)
DQ0 - DQ63
CB0-CB7
RAS
CAS
WE
CKE0, CKE1
CLK0 - CLK3
DQMB0 - DQMB7
CS0 - CS3
Vcc
Vss
SCL
SDA
N.C.
Address Inputs( RA0 ~ RA10 / CA0 ~ CA8)
Bank Select
Data Input/Output
Check Bits (x72 organisation only)
Row Address Strobe
Column Address Strobe
Read / Write Input
Clock Enable
Clock Input
Data Mask
Chip Select
Power (+3.3 Volt)
Ground
Clock for Presence Detect
Serial Data Out for Presence Detect
No Connection
Address Format:
4M x 64
4M x 72
Part Number
HYS 64V4120GU
HYS 72V4120GU
Semiconductor Group
Rows
11
11
Columns
9
9
2
Bank Select
1
1
Refresh
4k
4k
Period
64 ms
64 ms
Interval
15,6 µs
15,6 µs
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC (CB0)
NC (CB1)
VSS
NC
NC
VCC
WE
DQMB0
DQMB1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10
NC
VCC
VCC
CLK0
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
PIN #
VSS
DU
CS2
DQMB2
DQMB3
DU
VCC
NC
NC
NC (CB2)
NC (CB3)
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
NC
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Note : Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
3
Symbol
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC (CB4)
NC (CB5)
VSS
NC
NC
VCC
CAS
DQMB4
DQMB5
CS1
RAS
VSS
A1
A3
A5
A7
A9
A11=BS
NC
VCC
CLK1
NC
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
VSS
CKE0
CS3
DQMB6
DQMB7
NC
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
DU
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
VCC
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
CS1
CS0
CS
CS
CS
CS
DQMB0
DQM
DQM
DQMB4
DQM
DQM
DQ0-DQ7
DQ0-DQ7
D0
DQ0-DQ7
D8
DQ32-DQ39
DQ0-DQ7
D4
DQ0-DQ7
D12
DQMB1
DQM
DQMB5
DQM
DQM
DQ8-DQ15
DQ0-DQ7
DQ0-DQ7
D1
D9
DQ40-DQ47
DQ0-DQ7
D5
DQ0-DQ7
D13
CS
CS
CS
CS
DQM
DQ0-DQ7
D16
DQ0-DQ7
D17
DQM
CB0-CB7
CS
DQM
CS
CS3
CS2
CS
CS
CS
CS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
DQ16-DQ23
DQ0-DQ7
D2
DQ0-DQ7
D10
DQ48-DQ55
DQ0-DQ7
D6
DQ0-DQ7
D14
DQMB3
DQM
DQM
DQMB7
DQM
DQM
DQ24-DQ31
DQ0-DQ7
D3
DQ0-DQ7
D11
DQ56-DQ63
DQ0-DQ7
D7
DQ0-DQ7
D15
CS
CS
CS
CS
E2PROM (256wordx8bit)
D0 - D15,(D16,D17)
A0-A10,BS
VDD
VSS
D0 - D15,(D16,D17)
SA0
SA1
SA2
SA0
SA1
SA2
C1-C15,(C16,C17)
SCL
SDA
D0 - D7,(D8)
RAS, CAS, WE
CKE0
D0 - D15,(D16,D17)
D0 - D7,(D16) CLK0
2 SDRAMs CLK1
2 SDRAMs
2 (3) SDRAMs
2 SDRAMs
CLK2
2 SDRAMs CLK3
2 SDRAMs
2 (3) SDRAMs
2 SDRAMs
VDD
10k
CKE1
D9 - D15,(D17)
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted.
Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4120GU)
Semiconductor Group
4
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
Unit
min.
max.
Input high voltage
VIH
2.0
Vcc+0.3
V
Input low voltage
VIL
– 0.5
0.8
V
Output high voltage ( IOUT = – 2.0 mA)
VOH
2.4
–
V
Output low voltage ( IOUT = 2.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 40
40
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
– 40
40
µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
max.
(x64)
max.
(x72)
Unit
Input capacitance (A0 to A11, RAS, CAS, WE)
CI1
80
90
pF
Input capacitance (CS0 -CS3, )
CI2
30
35
pF
Input capacitance ( CLK0 - CLK3)
CICL
38
38
pF
Input capacitance (CKE0, CKE1)
CI3
50
55
pF
Input capacitance (DQMB0 - DQMB7)
CI4
15
20
pF
Input / Output capacitance (DQ0-DQ63,CB0-CB7)
CIO
20
20
pF
Input Capacitance (SCL,SA0-2)
Csc
8
8
pF
Input/Output Capacitance
Csd
10
10
pF
Semiconductor Group
5
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
Standby and Refresh Currents (Ta = 0 to 70 oC, VCC = 3.3V ± 0.3V) 1)
Parameter
Symbol
Test Condition
Note
X64
X72
800
900
mA
CKE<=VIL(max), tck>=tck(min.)
24
27
mA
CKE<=VIL(max), tck=infinite
16
18
mA
160
180
mA CS=
High
CKE>=VIH(min), tck=infinite,
no input change
80
90
mA
CKE<=VIL(max), tck>=tck(min.)
24
27
mA
CKE<=VIL(max), tck=infinite
16
18
mA
CKE>=VIH(min), tck>=tck (min.)
input changed one time
200
225
mA CS=
High
Icc3NS
CKE=>VIH(min),tck=infinite,
no input change
120
135
mA
Burst Operating
Current
Icc4
Burst length = full page,
trc = infinite, CL = 3,
tck>=tck (min.), Io = 0 mA
2 banks activated
760
855
mA
1,2
Auto (CBR) Refresh
Current
Icc5
trc>=trc(min)
720
810
mA
1,2
Self Refresh Current
Icc6
CKE=<0,2V
16
18
mA
1,2
Operating Current
Precharged Standby
Current in Power
Down Mode
Precharged Standby
Current in Nonpower
Down Mode
Active Standby
Current in Power
Down Mode
Active Standby
Current in Nonpower Down Mode
Semiconductor Group
Icc1
Icc2P
Icc2PS
Icc2N
Icc2NS
Icc3P
Icc3PS
Icc3N
Burst length = 4, CL=3
trc>=trc(min.),
tck>=tck(min.), Io=0 mA
2 bank interleave operation
CKE>=VIH(min), tck>=tck (min.),
input changed once in 3 cycles
6
1,2
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
AC Characteristics 3)4)
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Limit Values
Symbol
Unit Note
-10
min
max
Clock and Clock Enable
tCK
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
10
15
30
ns
ns
ns
fCK
System Frequency
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
–
–
–
100
66
33
MHz
MHz
MHz
–
–
–
8
9
27
ns
ns
ns
tAC
Clock Access Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
5
Clock High Pulse Width
tCH
3.5
–
ns
Clock Low Pulse Width
tCL
3.5
–
ns
CKE Setup Time
tCKS
3
–
ns
6
CKE Hold Time
tCKH
1
–
ns
6
CKE Setup Time (Power down mode)
tCKSP
3
–
ns
6
CKE Setup Time (Self Refresh Exit)
tCKSR
8
–
ns
8
Transition time (rise and fall)
tT
1
30
ns
Command Setup time
tCS
3
–
ns
6
Command Hold Time
tCH
1
–
ns
6
Address Setup Time
tAS
3
–
ns
6
Address Hold Time
tAH
1
–
ns
6
RAS to CAS delay
tRCD
30
–
ns
Cycle Time
tRC
75
120k
ns
Active Command Period
tRAS
45
120k
ns
Precharge Time
tRP
30
–
ns
Bank to Bank Delay Time
tRRD
20
–
ns
Common Parameters
Semiconductor Group
7
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
Parameter
Limit Values
Symbol
Unit Note
-10
min
max
tCCD
1
–
CLK
Self Refresh Exit Time
tSREX
2Clk
+tRC
–
ns
8
Refresh Period (4096 cycles)
tREF
–
64
ms
7
Data Out Hold Time
tOH
3
–
ns
Data Out to Low Impedance Time
tLZ
0
–
ns
CAS to CAS delay time (same bank)
Refresh Cycle
Read Cycle
tHZ
Data Out to High Impedance Time
CAS Latency = 3
CAS Latency = 2
CAS Latency = 1
9
–
–
–
6
8
25
ns
ns
ns
tDQZ
2
–
CLK
Data In Setup Time
tDS
3
–
ns
Data In Hold Time
tDH
1
–
ns
Data input to Precharge
tDPL
2
–
CLK
Data In to Active/refresh
tDAL
5
–
CLK 10
DQM Write Mask Latency
tDQW
0
–
CLK
DQM Data Out Disable Latency
Write Cycle
Semiconductor Group
8
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
Notes:
1. The specified values are valid when addresses are changed no more than once during tck(min.)
and when No Operation commands are registered on every rising clock edge during tRC(min).
Values are shown per module bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns
with the AC output load circuit shown.
tCH
2.4 V
CLOCK
0.4 V
tCL
tSETUP
tT
+ 1.4 V
tHOLD
50 Ohm
1.4V
INPUT
Z=50 Ohm
I/O
tAC
tAC
tLZ
50 pF
tOH
1.4V
OUTPUT
fig.1
tHZ
5. If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter.
6. If tT is longen than 1 ns, a time (t T -1) nshas to be added to this parameter.
7. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“the device.
8. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
9. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
10.tDAL is equivalent to t DPL + tRP.
Semiconductor Group
9
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence
detect protocol ( I 2C synchronous 2-wire bus)
PD-Table:
Byte#
Description
SPD Entry Value
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x8 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access Time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
11
9
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back random column address
Burst Length supported
Number of SDRAM banks
Supported CAS Latencies
19
20
21
CS Latencies
WE Latencies
SDRAM DIMM module attributes
22
23
24
25
26
27
28
SDRAM Device Attributes :General
SDRAM Cycle Time at CL = 2
SDRAM Access Time from Clock at CL = 2
SDRAM Cylce Time at CL = 1
SDRAM Access Time from Clock at CL = 1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
Semiconductor Group
10
Hex
x64 x72
-10 -10
80
80
08
08
04
04
0B
0B
09
09
2
64 / 72
0
LVTTL
10.0 ns
8.0 ns
none / ECC
Self-Refresh,
15.6µs
x8
n/a / x8
tccd = 1 CLK
02
40
00
01
A0
80
00
80
02
48
00
01
A0
80
02
80
08
00
01
08
08
01
1, 2, 4, 8 & full page
2
CAS latency = 1, 2
& 3
CS latency = 0
Write latency = 0
non buffered/non
reg.
Vcc tol +/- 10%
15.0 ns
9.0 ns
30 ns
27 ns
30 ns
20 ns
8F
02
07
8F
02
07
01
01
00
01
01
00
06
F0
90
78
6C
1E
14
06
F0
90
78
6C
1E
14
HYS64(72)V4120GU-10
4M x 64/72 SDRAM-Module
SPD-Table (cont’d):
Byte#
Description
SPD Entry Value
29
30
31
32-61
Minimum RAS to CAS delay tRCD
Minimum Ras pulse width tRAS
Module Bank Density (per bank)
Superset information (may be used in
future)
62 SPD Revision
63 Checksum for bytes 0 - 62
64- Manufactures’s information (optional)
127 (FFh if not used)
128+ Unused storage locations
30 ns
45 ns
16 MByte
Revision 1
Hex
x64 x72
-10 -10
1E
1E
2D
2D
04
04
FF
FF
01
F4
FF
01
06
FF
FF
FF
L-DIM-168-25 HYS64(72)V4120GU-10
SDRAM DIMM Module package
133,35
127,35
3,0
1
10 11
40
84
41
17,78
x)
29.21
4,0
42,18
66,68
A
85
C
B
94 95
124
125
168
x)
6,35
6,35
2,0
Detail A
1,0 +
- 0.5
2,54 min.
3,125
3,125
1,27
2,0
0,2 +- 0,15
Detail C
Detail B
DM168-25.WMF
x) on ECC modules only
Semiconductor Group
11