Revised February 2001 SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin DDR-I memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed for compliance with the JEDEC DDR module and register specifications. ■ Compliant with DDR-I registered module specifications The device is fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V’s. ■ Industry standard 48 pin TSSOP package ■ Operates at 2.5V ± 0.2V VDD ■ SSTL-2 compatible input and output structure ■ Differential SSTL-2 compatible clock inputs ■ Low power mode when device is reset Ordering Code: Order Number Package Number Package Description SSTV16857MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Description Q1-Q14 SSTL-2 Compatible Output D1-D14 SSTL-2 Compatible Inputs RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input VREF Voltage Reference Pin for SSTL Level Inputs VDDQ Power Supply Voltage for Output Signals VDD Power Supply Voltage for Inputs Truth Table RESET Dn CK CK Qn L X or Floating X or Floating X or Floating L H L ↑ ↓ L H H ↑ ↓ H H X L H Qn H X H L Qn L = Logic LOW H = Logic HIGH X = Don’t Care, but not floating unless noted ↑ = LOW-to-HIGH Clock Transition ↓ = HIGH-to-LOW Clock Transition © 2001 Fairchild Semiconductor Corporation DS500387 www.fairchildsemi.com SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset September 2000 SSTV16857 Functional Description RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTV16857 is a 14-bit register with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16857 and other SSTL-2 compatible devices. When the LV-CMOS RESET signal is asserted LOW, all outputs and internal registers are asynchronously placed into the LOW logic state. In addition, the clock and data differential comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 3) Supply Voltage (VDDQ) −0.5V to +3.6V Supply Voltage (VDD) −0.5V to +3.6V Power Supply (VDDQ) Reference Voltage (VREF) −0.5V to +3.6V Power Supply (VDD) −0.5V to VDD + 0.5V Input Voltage (VI) 2.3V to 2.7V Operating Range Output Voltage (VO) VDDQ to 2.7V Reference Supply Outputs Active (Note 2) −0.5V to VDDQ + 0.5V (VREF = VDDQ/2) DC Input Diode Current (IIK) 1.15 to 1.35 VI < 0V −50 mA Input Voltage VI > VDD +50 mA Output Voltage (VO) VO < 0V −50 mA Output Current IOH/IOL VO > VDD +50 mA DC Output Diode Current (IOK) 0V to VDD Output in Active States 0V to VDDQ VDD = 2.3V to 2.7V DC Output Source/Sink Current ±20 mA 0°C to +70°C Free Air Operating Temperature (TA) ±50 mA (IOH/IOL) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VDD or Ground Current ±100 mA per Supply Pin (IDD or Ground) Storage Temperature Range (Tstg) VREF ± 40 mV Termination Voltage (VTT) −65°C to +150°C Note 2: IO Absolute Maximum Rating must be observed. Note 3: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. DC Electrical Characteristics Symbol (2.3V ≤ VDD ≤ 2.7V) Parameter Conditions VDD (V) Min Max Units VIKL Input LOW Clamp Voltage II = −18 mA 2.3 −1.2 V VIKH Input HIGH Clamp Voltage II = +18 mA 2.3 3.5 V VREF+310mV VIH-AC AC HIGH Level Input Voltage Data Inputs VIL-AC AC LOW Level Input Voltage Data Inputs VIH-DC DC HIGH Level Input Voltage Data Inputs VIL-DC DC LOW Level Input Voltage Data Inputs VIH HIGH Level Input Voltage RESET VIL LOW Level Input Voltage RESET VICR Common Mode Input Voltage Range CLK, CLK 0.97 VI(PP) Peak to Peak Input Voltage CLK, CLK 360 VOH HIGH Level Output Voltage IOH = −100 µA 2.3 to 2.7 VDD − 0.2 IOH = −16 mA 2.3 1.95 IOL = 100 µA 2.3 to 2.7 0.2 IOL = 16 mA 2.3 0.35 2.7 ±5.0 µA 10 µA 25 mA 90 µA/MHz 15 µA/MHz VOL LOW Level Output Voltage VREF+150mV VREF−150mV Input Leakage Current VI = VDD or GND Static Standby RESET = GND, IO = 0 Static Operating RESET = VDD, IO = 0 Dynamic Operating Current 1.53 V V mV V V 2.7 VI = VIH(AC) or VIL(AC) Clock Only V V 0.7 II V V 1.7 IDD IDDD V VREF−310mV RESET = VDD, IO = 0 VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Dynamic Operating Current RESET = VDD, IO = 0 per Data Input VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% 2.7 Data Input = ½ Clock Rate 50% Duty Cycle 3 www.fairchildsemi.com SSTV16857 Absolute Maximum Ratings(Note 1) SSTV16857 DC Electrical Characteristics Symbol (Continued) Parameter VDD Conditions Min Max Units (V) ROH Output HIGH On Resistance IOH = −20 mA 2.3 to 2.7 7 20 Ω ROL Output LOW On Resistance IOL = 20 mA 2.3 to 2.7 7 20 Ω RO∆ | ROH - ROL | IO = 20 mA, TA = 25°C 4 Ω 2.5 AC Electrical Characteristics (Note 4) TA = 0°C to +70°C, CL = 30 pF, RL = 50Ω Symbol VDD = 2.5V ± 0.2V; VDDQ = 2.5V ± 0.2V Parameter Min Units Max fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) 22 ns 22 ns tINACT Differential Inputs De-activation Time, (Note 5) data and clock inputs must be held at valid levels (not floating) after RESET LOW tS tH Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5) 0.75 Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5) 0.75 Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 tPHL, tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 tPHL tSK(Pn-Pn) ns ns ns 2.8 ns Propagation Delay RESET to Qn (Figure 6) 5.0 ns Output to Output Skew 200 ps Note 4: Refer to Figure 1 through Figure 7. Note 5: This parameter is not production tested. Note 6: For data signal input slew rate ≥ 1 V/ns. Note 7: For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. Note 8: For CK, CK signals input slew rates are ≥ 1 V/ns. Capacitance (Note 9) Symbol CIN Max Units Data Pin Input Capacitance Parameter Min 2.0 Typ 3.0 pF VDD = 2.5V, VI = VREF ± 350 mV CK, CK - Input Capacitance 2.5 3.5 pF VDD = 2.5V, VICR = 1.25V, VI(PP) = 360 mV RESET 2.5 3.5 pF VDD = 2.5V, VI = VDD to GND Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. www.fairchildsemi.com 4 Conditions SSTV16857 AC Loading and Waveforms (See Notes A through F below) Note: CL includes probe and jog capacitance FIGURE 2. Voltage Waveforms - Pulse Duration FIGURE 1. AC Test Circuit Note: IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. FIGURE 3. Voltage and Current Waveforms Inputs Active and Inactive Times FIGURE 4. Voltage Waveforms Propagation Delay Times FIGURE 5. Voltage Waveforms - Setup and Hold Times FIGURE 6. Voltage Waveforms RESET Propagation Delay Times Note A: All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z0 = 50Ω, input slew rate = 1V/ns ± 20% (unless otherwise specified). Note B: The outputs are measured one at a time with one transition per measurement. Note C: VTT = VREF = VDD/2. Note D: VIH = VREF +310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. Note E: VIL = VREF −310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Note F: Removal time (tREM) is tested with one data input held active HIGH. The propagation time from CK to the corresponding output must meet valid timing specifications for the measurement to be accurate. FIGURE 7. Voltage Waveforms RESET Removal Delay Times 5 www.fairchildsemi.com SSTV16857 14-Bit Register with SSTL-2 Compatible I/O and Reset 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6