Revised September 2001 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description Features The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module register specifications. ■ Compliant with DDR-I registered module specifications The device has been fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V’s. ■ Low power mode when device is reset ■ Operates at 2.5V ± 0.2V VDD ■ SSTL-2 compatible input structure ■ SSTL-2 compliant output structure ■ Differential SSTL-2 compatible clock inputs ■ Industry standard 64 pin TSSOP package ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number SSTV16859GX (Note 1) SSTV16859MTD (Note 2) Package Number BGA96A MTD64 Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2001 Fairchild Semiconductor Corporation DS500414 www.fairchildsemi.com SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset March 2001 SSTV16859 Connection Diagrams Pin Descriptions Pin Name Pin Assignment for TSSOP Description Q1A-Q13A SSTL-2 Compatible Register Outputs Q1B-Q13B D1-D13 SSTL-2 Compatible Register Inputs RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input VREF Voltage Reference Pin for SSTL level inputs VDDQ Power Supply Voltage for Output Signals VDD Power Supply Voltage for Inputs NC Electrically Isolated No Connect FBGA Pin Assignments Pin Assignment for FBGA 1 2 3 4 5 6 A NC NC NC NC NC NC B Q12A Q13A GND GND NC NC C Q10A Q11A GND GND NC NC D Q8A Q9A VDDQ VDDQ D13 D12 E Q6A Q7A VDDQ VDD D11 D10 F Q4A Q5A VDDQ VDD D9 D8 G Q2A Q3A GND GND D7 RESET H Q1A Q13B GND GND NC CK J Q12B Q11B GND VREF NC CK K Q10B Q9B VDDQ VDD NC NC L Q8B Q7B VDDQ VDD D5 D6 M Q6B Q5B VDDQ VDDQ D3 D4 N Q4B Q3B GND GND D1 D2 P Q2B Q1B GND GND NC NC R NC NC NC NC NC NC T NC NC NC NC NC NC Truth Table RESET Dn CK CK Qn L X or Floating X or Floating X or Floating L H L ↑ ↓ L H H ↑ ↓ H H X L H Qn-1 H X H L Qn-1 L = Logic LOW H = Logic HIGH X = Don’t Care but not floating unless noted ↑ = LOW-to-HIGH Clock Transition ↓ = HIGH-to-LOW Clock Transition Qn-1 = Output Remains in Previously Clocked State (Top Thru View) www.fairchildsemi.com 2 The SSTV16859 is a 13-bit dual register with SSTL-2 compatible inputs and outputs. Input data is transferred to output data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW all outputs are placed into the LOW logic state and all input comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram For n = 1 to 13 3 www.fairchildsemi.com SSTV16859 Functional Description SSTV16859 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions (Note 5) Supply Voltage (VDDQ) −0.5V to +3.6V Supply Voltage (VDD) −0.5V to +3.6V Power Supply (VDDQ) Reference Voltage (VREF ) −0.5V to +3.6V Power Supply (VDD) −0.5V to VDD +0.5V Input Voltage (VI) Operating Range Output Voltage (VO) Outputs Active (Note 4) VDDQ to 2.7V Reference Supply −0.5V to VDDQ + 0.5V (VREF = VDDQ/2) DC Input Diode Current (IIK) 1.15 to 1.35 VREF ± 40 mV Termination Voltage (VTT) VI < 0V −50 mA Input Voltage VI > VDD +50 mA Output Voltage (VO) VO < 0V −50 mA Output Current IOH/IOL VO > VDDQ +50 mA DC Output Diode Current (IOK) 0 to VDD Output in Active States 0V to VDDQ VDD = 2.3V to 2.7V DC Output Source/Sink Current ±20 mA 0°C to +70°C Free Air Operating Temperature (TA) ±50 mA (IOH/IOL) Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VDD or Ground Current ±100 mA per Supply Pin (IDD or Ground) Storage Temperature Range (Tstg) 2.3V to 2.7V −65°C to +150°C ≥ 7000V ESD (Human Body Model) Note 4: IO Absolute Maximum Rating must be observed. Note 5: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. DC Electrical Characteristics (2.3V ≤ VDD ≤ 2.7V) Symbol Parameter VDD Conditions (V) Min Typ Max Units VIKL Input LOW Clamp Voltage II = −18 mA 2.3 −1.2 V VIKH Input HIGH Clamp Voltage II = +18 mA 2.3 3.5 V VREF+310mV VIH-AC AC HIGH Level Input Voltage Data Inputs VIL-AC AC LOW Level Input Voltage Data Inputs VIH-DC DC HIGH Level Input Voltage Data Inputs VIL-DC DC LOW Level Input Voltage Data Inputs VIH HIGH Level Input Voltage RESET VIL LOW Level Input Voltage RESET VICR Common Mode Input Voltage Range CK, CK 0.97 VI(PP) Peak to Peak Input Voltage 360 VOH HIGH Level Output Voltage VOL LOW Level Output Voltage VREF+150mV 1.7 V V mV IOH = −100 µA 2.3 to 2.7 VDD − 0.2 2.3 1.95 IOL = 100 µA 2.3 to 2.7 0.2 IOL = 16 mA 2.3 0.35 2.7 ±5.0 µA 10 µA 25 mA 120 µA/MHz 15 µA/MHz Input Leakage Current VI = VDD or GND Static Standby RESET = GND, IO = 0 Static Operating RESET = VDD, IO = 0 V V 2.7 VI = VIH(AC) or VIL(AC) Dynamic Operating Current 1.53 IOH = −16 mA II Clock Only V V 0.7 CK, CK V V VREF−150mV IDD IDDD V VREF−310mV RESET = VDD, IO = 0 VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Dynamic Operating Current RESET = VDD, IO = 0 per Data Input VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Data Input = ½ Clock Rate 50% Duty Cycle www.fairchildsemi.com 4 2.7 Symbol Parameter (Continued) VDD Conditions Min Typ Max Units Ω (V) ROH Output HIGH On Resistance IOH = −20 mA 2.3 to 2.7 7 20 ROL Output LOW On Resistance IOL = 20 mA 2.3 to 2.7 7 20 Ω RO∆ | ROH - ROL | IO = 20 mA, TA = 25°C 4 Ω 2.5 AC Electrical Characteristics (Note 6) TA = 0°C to +70°C, CL = 30 pF, RL = 50Ω Symbol VDD = 2.5V ± 0.2V; VDDQ = 2.5V ± 0.2V Parameter Min Typ Units Max fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, (Note 7) data inputs must be LOW after RESET HIGH (Figure 3) 22 ns 22 ns tINACT Differential Inputs De-activation Time, (Note 7) data and clock inputs must be held at valid levels (not floating) after RESET LOW tS tH Setup Time, Fast Slew Rate (Note 8)(Note 9) (Figure 5) 0.75 Setup Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) 0.9 Hold Time, Fast Slew Rate (Note 8)(Note 10) (Figure 5) 0.75 Hold Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 tPHL, tPLH Propagation Delay CK, CK to Qn (Figure 4) 1.1 tPHL Propagation Delay RESET to Qn (Figure 6) ns ns ns 2.8 ns 5.0 ns Note 6: Refer to Figure 1 through Figure 7. Note 7: This parameter is not production tested. Note 8: For data signal input slew rate ≥ 1 V/ns. Note 9: For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. Note 10: For CK, CK signals input slew rates are ≥ 1 V/ns. Capacitance (Note 11) Symbol CIN Max Units Data Pin Input Capacitance Parameter Min 2.2 Typ 3.2 pF VDD = 2.5V, VI = VREF ± 310 mV Conditions CK, CK - Input Capacitance 2.2 3.2 pF VDD = 2.5V, VICR = 1.25, VI(PP) = 360 mV RESET 2.3 3.3 pF VDD = 2.5V, VI = VDD or GND Note 11: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. 5 www.fairchildsemi.com SSTV16859 DC Electrical Characteristics SSTV16859 AC Loading and Waveforms (See Notes A through F below) Note: CL includes probe and jog capacitance FIGURE 2. Voltage Waveforms - Pulse Duration FIGURE 1. AC Test Circuit Note: IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. FIGURE 3. Voltage and Current Waveforms Inputs Active and Inactive Times FIGURE 4. Voltage Waveforms Propagation Delay Times FIGURE 5. Voltage Waveforms - Setup and Hold Times FIGURE 6. Voltage Waveforms RESET Propagation Delay Times Note A: All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z0 = 50Ω, input slew rate = 1V/ns ± 20% (unless otherwise specified). Note B: The outputs are measured one at a time with one transition per measurement. Note C: VTT = VREF = VDD/2. Note D: VIH = VREF +310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. Note E: VIL = VREF −310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Note F: Removal time (tREM) is tested with one data input held active HIGH. The propagation time from CK to the corresponding output must meet valid timing specifications for the measurement to be accurate. FIGURE 7. Voltage Waveforms RESET Removal Delay Times www.fairchildsemi.com 6 SSTV16859 Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A 7 www.fairchildsemi.com SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8