ETC TQ8318

T
R
I
Q
VSYMX
1
VLEVEL
2
GND
3
N.C.
4
N.C.
5
U
I
N
T
S E M I C O N D U C T O R, I N C .
*
VEE
28
VEE
TQ8318/19
27
VEE
PRELIMINARY DATA SHEET
26
GND
25
BIAS
OC192/STM64
E/O Driver
24
DRIVEGND
Features
23
DRIVEGND
22
NDOUT
• High performance fully backterminated 20mA/1V to 60mA/
3V modulation output driver
(TQ8318)
21
DOUT
20
DRIVEGND
19
DRIVEGND
18
VEE
17
VEE
16
N.C.
• Output can drive direct coupled
Electro-Absorptive Modulator
(EAM/EML), or AC coupled
differential
Mach-Zehnder
modulator or Direct Modulated
Laser (DML)
15
GND
• NRZ data rates to 10.8Gbs
50Ω
GND
6
DIN
7
NDIN
8
50Ω
50Ω
GND
9
VTT
10
VDD
11
GND
12
VSEN10
13
VSEN1
14
50Ω
VEE
50Ω
5Ω
* Downset paddle is GND
• Also available without backterminations for 25 ohm, 40 mA
to 120mA applications (TQ8319)
• Output symmetry adjust
• 0 to 1.0V output offset control
• 32ps max output risetime
The TQ8318/TQ8319 is a low jitter, high performance electro-optic driver
intended for directly interfacing CML outputs from a multiplexer or clock
recovery device to various EO devices, including cooled and uncooled DFB and
FP lasers, high power VCSEL arrays, EA modulators and differential MachZehnder (MZ) modulators. The TQ8318 and the TriQuint TGA1328/8652 can
be used in combination for single ended 9V MZ drive applications. The
TQ8318/19’s symmetry and level controls, low additive jitter, and excellent
rise/fall times while driving significant loads allow the highest system level
performance at low cost. The devices also include an offset control to allow
adjustment of DC bias between 0V and -1V for EAM/EML, or 0-40mA for laser
threshold, applications. The 28 pin TSSOP footprint and low jitter makes the
devices particularly suitable for high port count WDM circuit packs and
modules, and for optical modules. These devices are compatible with
CMOS, SiGe or GaAs muxes with CML, eLVDS, or LVPECL outputs.
• +3.3V CML direct coupled input
can be AC coupled for eLVDS
and LVPECL inputs
• 28 pin TSSOP small outline
package or die
• 0°C to +110°C case operating
temperature range
Applications
• DML with drive to 120mA
• Single-ended 50 ohm 1.0-3.0V
EAM/EML driver (DC coupled with
integral 0 to -1V offset)
• 6V differential 50 ohm MachZehnder driver (AC coupled)
1
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
10.8Gb/s Output Driver
These devices are extremely well suited to driving
a variety of Electro-optical devices that utilize a
grounded case. A +3.3V/-5V family of devices is
available for applications where the driven device
does not utilize a grounded case or where these
drivers are used in die form.
input common mode range of (Isource*50 ohm) above VEE. The
choice of the external current source also sets the output voltage
swing. For example, to achieve the maximum swing of 3.0V into
25 ohm (50 ohm internal back-terminated impedance in parallel
with a 50 ohm forward load), a 12mA source must be used
(Isource*10*25 ohm =120mA*25 ohm = 3.0V). Note that
feedback with a back facet monitor or PiN diode provides a more
ideal method to control optical output power and extinction ratio,
if available. Figure 1 depicts a DML application, though similar
considerations can be made for either EAM/EML or differential
MZM applications.
The TQ8318’s 50 ohm back-terminated high power
cascoded output stage drives between 1.0V and
3.0V of modulation into a single ended 50 ohm
external load (6.0V peak-peak in differential mode),
or between 20mA and 60mA for DML applications.
A variant without the back-terminations, the
TQ8319, may be used in 25 ohm external load Figure1. Level Control Circuit
applications to modulate up to 120 mA. The
separate power supply pins for the output stage are
DRIVEGND
DRIVEGND = 0V and VEE = -7.5V. Note that outputs
may be driven as differential or single ended signals
50Ω
50Ω
at DOUT and NDOUT and that a CML drive level is
possible by adjusting the output level control to an
DOUT
•
appropriate level. Unused output complements
•
NDOUT
must be tied as 50 ohm (TQ8318, 25 ohm for
TQ8319) to GND when direct coupling is used.
BIAS
•
The data amplitude may be adjusted using VLEVEL
and the crossing level of the output data eye can be
adjusted using VSYMX. Both of these levels are
preset internally if VLEVEL and VSYMX are left
open (N.C.). The DC offset, on DOUT and NDOUT
may be biased to a DC level with a voltage control
on BIAS from 0V/0mA to -1.0V/40mA (25 ohms).
The output current level and voltage amplitude at
DOUT and NDOUT may be set using an external
feedback control loop. To set the output current
level, connect an external current source, Isource,
equal to 20% of the desired output, to VSEN10.
Connect VLEVEL, VSEN10 and VSEN1 to an
amplifier, as shown in Figure 1, with a minimum
2
Pre Amp
Grounded Case
25 ohm typ
50 ohm
VLEVEL
VSEN1
Isource
5Ω
50Ω
VSEN10
•
Vee
-7.5V
4mA - 12mA
DML
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
Type
Pin Number
Description
DIN
NDIN
CML Input
CML Input
7
8
DOUT
NDOUT
High Drive Output
High Drive Output
21
22
VSYMX
Analog Input
1
Serial data input. Internally terminated by 50 Ohms to VTT
Complement of DIN. Internally terminated by 50 Ohms to
VTT
High power differential driver modulated output.
Complement of DOUT. If unused must be terminated in the
same manner as DOUT.
Rise/fall time symmetry adjust control signal input. Input
impedance is typically 10k Ohm.
VLEVEL
Analog Input
2
VSEN10
Analog I/O
13
VSEN1
Analog Output
14
BIAS
Power Pins
Signal
VTT
VDD
GND
VEE
DRIVEGND
NC
Analog Input
25
Description
Input Termination Supply
Pre-drive and I/O VDD Supply
Ground Supply
Output Stage Neg. Supply (-7.5V)
Output Stage Pos. Supply (0V)
Do Not Connect
TELECOM
PRODUCTS
Signal
SONET/SDH/ATM
PRODUCTS
Table 1. TQ8318/19 Pin Descriptions
Output data amplitude adjust control signal input. Input
impedance is typically 10k Ohm.
Output current level reference pin. When driven with an
external current source at exactly 1/5 the output current of
the TQ8318 (1/10 for the TQ8319) level, the voltage at
Vsen10 is equal to that at Vsen1. Can be used to implement a
control loop.
Output current level sensing pin. Vsen1 voltage is directly
proportional to the output current level. Connects internally
to 5 Ohm resistor in differential driver current tail.
Output offset control input
Pin Number
10
11
3, 6, 9, 12, 26, 15, Package Down Paddle (required)
28, 27, 18, 17
24, 23, 20, 19 (Note: These pins are unused in the TQ8319)
4, 5, 16
3
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Units
Supply voltage
VDD
GND-0.5
4.0
V
Output stage supply return
VEE
-8
GND+0.5
V
GND-0.5
VDD+0.5
V
CML inputs
Control signals
VEE-0.5
GND+0.5
V
Tstg, Storage Temperature
-55
150
oC
Tc, Maximum Case Operating Temperature
110
oC
Tj, Maximum junction temperature
150
oC
Electrostatic Discharge (100pF, 1.5kΩ)
1000
V
Notes:
1. All voltages with respect to GND.
Table 3. Operating Ranges
Signal
Symbol
VDD
VDD
IDD
VTT
VTT
VEE
VEE
IEE
DRIVEGNDVdrive
Idrive
Idrive
Tc
Pdiss
Pdiss
Notes:
Parameter
Min
Typ
Max
Units
Supply voltage range
Supply current (Note 2)
Input termination supply voltage range
Negative driver supply
Supply current (Notes 3 and 5)
Output stage power supply
TQ8318 supply current for output stage (50 ohm load)
TQ8319 supply current for output stage (25 ohm load)
Case temperature measured at the case paddle
Power dissipation (Note 4)
Power dissipation (Note 5)
3.14
3.3
55
VDD
-7.5
260
0
3.47
2.45
2.13
60
120
110
3.37
2.67
V
mA
V
V
mA
V
mA
mA
oC
W
W
-7.13
20
40
0
-7.87
1. Room Temperature condition
2. VDD at operating range.
3. VDD , VEE , and VTT at operating range.
4. Idrive into specified load and max modulation and 1V offset.
5. Idrive into specified load and max modulation and 0V offset.
Table 4. DC Characteristics—Differential CML Input
Symbol
Parameter
Min
Nom
Max
Unit
VICOM
VIDIFF
RIN
CIN
VESD
Input common mode voltage range
Input differential voltage, per side, pk-pk
Input termination resistance
Input capacitance
ESD breakdown rating
VDD-0.4
300
—
—
50
—
—
VDD-0.150
800
V
mV
ohm
pF
V
Notes
4
—
1000
TBD
—
1. For +3.3V CML operation inputs may be Direct Coupled. To interface LVPECL or to eLVDS, AC coupling is recommended. An internal
bias voltage is generated on-chip so VTT may be left open.
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
Symbol
Parameter
Min
VSYMX
Vdef
Vsymx
Zsymx
Default input level
VSYMX nominal operating range
VSYMX input impedance
Vdef-0.18
Vdef
Vlevel
Aamp
Zlevel
Default input level
VLEVEL nominal operating range
Output data amplitude adjust gain
VLEVEL input impedance
Vsen1
Zsen1
Output current sensing voltage level for TQ8318
Output current sensing voltage level for TQ8319
VSEN1 equivalent resistance
VEE+(2.5•Idrive)
VEE+(5•Idrive)
5
V
V
ohm
Vsen10
Zsen10
Isen10
Control current input voltage level
VSEN10 equivalent resistance
VSEN10 input current range
VEE+(50•Idrive)/5
50
12
V
ohm
mA
Vsenrat
VSEN10 to VSEN1 Ratio
9.9
VEE
Vdef
Nominal output offset control range
Default input level
VSEN1
VSEN10
BIAS
Notes:
Max
Units
Vdef+0.18
V
V
k ohm
0.73•VEE
10
0.83•VEE
VEE+0.8
VEE+2.1
1.54
10
4
10
10.1
VEE+1.65
VEE
TELECOM
PRODUCTS
Signal
VLEVEL
Typ
SONET/SDH/ATM
PRODUCTS
Table 5. Control Signal Specifications
V
V
V/V
k ohm
%
V
V
1. Refer to Figure 2. All specifications for output data apply under the following conditions:
Output Data Pattern:
223-1 PRBS, 9.95328Gbit/s
DOUT and NDOUT termination:
Direct Coupled external load is a 50 ohm termination to GND for the TQ8318;
Direct Coupled external load is a 25 ohm termination to GND for the TQ8319
Table 6. 10.8 Gb/s High Speed Output Signal Specifications
Signal
Symbol
DOUT
Tpw
N D O U T Trise
(Note 2) Tfall
Jpp
Vmean_max
Vmean_min
Xingmin
Xingmax
DXing
%over
%under
%ripple
RATE
Voffset
Tskew
Description
Min
Typ
Max
Units
Output data pulse width
Output data rise time
Output data fall time
Output data peak-peak jitter (Note 3)
Output data mean pk-pk for high output applications;
Vlevel =(VEE+2.1)V, Vdrive = 0 V, VEE= -7.5V
Output data mean pk-pk for low output applications;
Vlevel = (VEE+0.8)V, Vdrive = 0 V, VEE= -7.5V
Min. data crossing lvl. adjustment range with VSYMX
Max. data crossing lvl adjustment range with VSYMX
Absolute variation in output data crossing level over full
VLEVEL operating range
Overshoot
Undershoot
Ripple
NRZ data rate (Note 5)
Offset voltage referred to DRIVEGND (Note 6)
DOUT to NDOUT magnitude measured at common mode
95
16
16
100
25
25
3
105
32
32
5
%
ps
ps
ps
V
1.0
V
3.0
20
60
-5
-
40
80
+5
%
%
%
TBD
-1.0
-
10
10
10
10800
TBD
6
%
%
%
Mbs
V
ps
5
TQ8318/TQ8319
PRELIMINARY
Notes:
DATA SHEET
1. Refer to Figure 2. All specifications for output data apply under the following conditions:
Output Data Pattern:
223-1 PRBS, 9.95328Gbit/s
DOUT and NDOUT termination:
Direct Coupled external load is a 50 ohm termination to GND for the TQ8318;
Direct Coupled external load is a 25 ohm termination to GND for the TQ8319
Termination network return loss:
>20 dB, 0 to 4 GHz
(TQ8318 only)
>15 dB, 4 to 12 GHz
>6 dB, 12 to 20 GHz
Vlevel:
over specified operating range
VSYMX:
adjusted to give 50% data crossing
2. This specification applies to the Vmean measurement shown in Figure 2. Vlevel must be adjusted to the specified
level and VSYMX must be adjusted for optimum eye crossing level before making data eye measurements.
Maximum rise and fall times are measured with a 35ps input rise and fall time.
3. Measured at 223-1 PRBS, 9.95328 Gbit/s, eye crossings
4. Peak to Peak jitter is defined as the difference between the measured jitter on the device and the test system jitter.
Jitter is unfiltered broadband measurement.
5. Device will function down to DC however some specs in Table 6 may not be met.
6. Vmean full spec range is supported over Voffset range.
V offset
Figure 2. 10.8Gb/s Output Data Eye Diagram
Mean ‘1’
Level
DRIVEGND
T rise, Tfall
T rise, T fall
V ripple
V over
100%
80%
Vmean
V min
V max
Tpw
Data
Crossing
Meas.
20%
0%
J pp
J pp
V ripple
V under
Mean ‘0’
Level
Tpw =
Vmin =
Trise =
% over =
%ripple =
half of input waveform period
minimum peak-to-peak voltage (eye interior)
20% to 80% rise time, mean ‘0’ to mean ‘1’
Vover/Vmean X 100%
Vripple/Vmean X 100%
V max =
V mean =
Tfall =
%under =
Jpp =
maximum peak-to-peak voltage
Mean peak-to-peak voltage (mean eye opening)
20% to 80% fall time, mean ‘0’ to mean ‘1’
Vunder/Vmean X 100%
peak-to-peak data crossing jitter
Note: mimimum display persistence of 2s is assumed for the above measurements.
6
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
TELECOM
PRODUCTS
SONET/SDH/ATM
PRODUCTS
Figure 3. Tek TDS8000 Oscilloscope to cables to 12.5 Gbs HP BERT running at 10.7 Gb/s
Vert: 100mV/div Horiz: 15pS/div Rise: 18.30pS Fall:
20.40pS
Jitter:
10.20pS p-p
Figure 4. TQ8318 (in TSSOP) Tested with Instruments and Cables from Figure 3
Vert: 500 mV/div Horiz: 15 pS/div Rise: 22.80 pS Fall:
18.60 pS
Jitter:
14.10 pS p-p
7
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
Figure 5. Typical output at 12.5 Gb/s for TQ8318 TSSOP
Figure 6. TSSOP-28 Downpaddle Package Mechanical drawing
1.00
1.00 DIA.
C
B
3 2 1
B
E/2
1.00
MIN
A
A1
A2
b
b1
c
c1
D
E1
e
E
L
N
P
P1
NOM
.0254
.8500
.1900
.1900
.0900
.0900
9.6000
4.3000 4.4000
.6500
.6500
6.4000
.5000
.6000
28
5.5000
5.0000
3.0000
MAX
1.1262
.1500
1.0500
.3000
.2500
.2000
.1600
9.8000
4.5000
.6500
C
L
E
E1
SEE
DETAIL "A"
TOP VIEW
END VIEW
(b)
b1
b
.7000
A2
Note: All dimensions in millimeters (mm).
WITH PLATING
A
3.0100
aaa
e
A1
D
SIDE VIEW
C
c1
SEATING
PLANE
BASE METAL
SECTION "B-B"
(14o)
P
0.25
P1
(OC)
L
(1.00)
EXPOSED PAD VIEW
8
DETAIL 'A'
(14o )
(VIEW ROTATED 90oC.W.)
(c)
TQ8318/TQ8319
DATA SHEET
SONET/SDH/ATM
PRODUCTS
PRELIMINARY
TELECOM
PRODUCTS
Approximate Actual Size of Package Footprint
Ordering Information
TQ8318
10.7 Gb/s Backterminated EO Driver +3.3/-7.5V TSSOP Package
TQ8319
10.7 Gb/s Unterminated EO Driver +3.3/-7.5V TSSOP Package
TQ8318-DD
DC Tested TQ8318 Die
TQ8318-DA
AC Tested TQ8318 Die
TQ8319-DD
DC Tested TQ8319 Die
TQ8319-DA
AC Tested TQ8319 Die
Related Components:
TQ8317
10.7 Gb/s Backterminated EO Driver +3.3/-5V TSSOP Package
TQ8320
10.7 Gb/s Unterminated EO Driver +3.3/-5V TSSOP Package
TGA1328
Single ended 9V driver - die form
TGA8652
Single ended 9V driver - packaged form
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and
information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000 (Oregon, USA)
Fax: (503) 615-8900 (Oregon, USA)
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes
no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications
are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any
third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 2001 TriQuint Semiconductor, Inc. All rights reserved.
Revision 0.0.A August 2001
9
TQ8318/TQ8319
PRELIMINARY
DATA SHEET
Known Device Issues as of August 1, 2001
1.
There is a 20GHz oscillation that is “bias space” related. The oscillation is a free-running sine wave at
approximately 20GHz. No oscillations have been observed if Vbias is left at default (Vbias = Vee). The oscillations
have been observed to occur when Voffset is between -0.5V and -1.0V and VOUTpp is less than 2.5V.
2.
Vbias does not conform to the operation range shown in Table 1 “Absolute Maximum Ratings”. The Bias
pin is directly connected to the gate of the FET in the bias current generator. As such, voltages in excess of
Vee+2.5V may cause damage to the bias generator. Placing a 2.5k ohm resistor in series with the Vbias pin will
prevent damage to the part.
3.
10
The average measured full output voltage offset is -950mV.