MAXIM MAX3950EVKIT

19-1866; Rev 0; 12/00
MAX3950 Evaluation Kit
Features
♦ +3.3V Single Supply
♦ 9.95Gbps/10.7Gbps Evaluation
♦ Fully Assembled and Tested Surface-Mount
Board
Component List
DESIGNATION
QTY
Ordering Information
PART
DESCRIPTION
MAX3950EVKIT
TEMP. RANGE
IC-PACKAGE
-40°C to +85°C
68 QFN
C1, C10−C13
5
1000pF ±10% ceramic
capacitors (0402)
Murata GRM36X7R102K050A
C2, C6−C9,
C14–C17
9
0.01µF ±10% ceramic
capacitors (0402)
Murata GRM36X7R103K016A
C3
1
33µF ±10%, 10V min tantalum
capacitor, AVX TAJC336K035
C4
1
2.2µF ±10%, 16V min tantalum
capacitor, AVX TAJC225K016
C5
1
0.1µF ±10% ceramic capacitor
(0603)
Murata GRM39X7R104K016A
J1, J2, J7−J38
34
SMB connectors (PC mount)
PHONE
FAX
J3−J6
4
SMA connectors (edge mount)
AVX
843-448-9411
843-626-3123
J39, J40
2
Test points
Murata
770-684-7821
—
J41–J46
6
Not installed
J47
1
2 ×10 header (0.1in center)
L1
1
56nH inductor
Coilcraft 0805HS-560TKBC
R1−R17
17
Not installed
U1
1
MAX3950EGK 68-pin QFN
None
1
MAX3950 EV kit circuit board
None
1
MAX3950 data sheet
None
1
MAX3950 EV kit data sheet
Component Suppliers
SUPPLIER
Note: Please indicate that you are using the MAX3950 when
contacting the suppliers.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Evaluates: MAX3950
General Description
The MAX3950 evaluation kit (EV kit) is an assembled
surface-mount demonstration board that provides easy
evaluation of the MAX3950 10Gbps, 1:16 deserializer
with low-voltage differential signal (LVDS) outputs. All
components necessary to interface with 3.3V CML
inputs and LVDS outputs are included on the EV kit.
Detailed Description
The MAX3950 EV kit simplifies evaluation of the
MAX3950 1:16 deserializer. The EV kit operates from a
single +3.3V supply and includes all the external components necessary to interface with 3.3V CML inputs
and LVDS outputs. Transmission line test structures are
included on the evaluation board to allow for measurement of signal loss and dispersion of clock and data
signals at 10GHz.
Shunt Configuration of J47
The 2 ✕ 10 header on J47 should be shunted as shown
in Figure 1. Other jumper arrangements will cause the
IC to operate erroneously.
J47
Evaluates: MAX3950
MAX3950 Evaluation Kit
Applications information
Connecting LVDS Outputs to 50Ω
Oscilloscope Inputs
To monitor LVDS signals with 50Ω oscilloscope inputs,
set the inputs of the oscilloscope to “AC coupling” or
place a DC block in series with each output. If you are
observing only one output with a 50Ω probe, balance
the complementary output with a DC block and a 50Ω
terminator to ground.
Connecting LVDS Outputs to HighImpedance Oscilloscope Inputs
To monitor LVDS signals with high-impedance oscilloscope inputs, install 100Ω 0402 resistors on locations R1
through R17. Note that this does not provide as good a
termination scheme as using the 50Ω inputs on an oscilloscope and the resulting output will be degraded.
Figure 1. Shunt Arrangement for J47
Layout Consideration
The MAX3950’s performance can be greatly affected
by circuit-board layout and design. Use good high-frequency design techniques, including minimizing
ground inductances and using fixed-impedance transmission lines on the data and clock signals.
Exposed Pad Package
The 68-pin QFN package with exposed pad incorporates features that provide a very low thermal-resistance path for heat removal from the IC—either to a PC
board or to an external heatsink. The MAX3950’s
exposed pad must be soldered directly to a ground
plane with good thermal conductance.
2
_______________________________________________________________________________________
_______________________________________________________________________________________
J8
J5
J1
J3
J6
J7
J2
C14
0.01µF
C15
0.01µF
C16
0.01µF
C17
J4 0.01µF
J9
VCC
VCC
VCC
J10
SD+
SD-
7
8
17
GND
GND
J12
21
PD14+
19 20
PD14PD0+
PD0-
18
J11
GND
GND
PCLK-
14
16
GND
13
PCLK+
Vcc
12
15
SCLK-
11
SCLK+
Vcc
6
Vcc
GND
5
9
PD15+
10
PD15-
3
GND
GND
4
2
1
J13
22
PD13+
PD1-
62
23
J14
59
26
58 57
GNDIN
VCCIN
J15
27 28
MAX3950
U1
61 60
VCC
24 25
PD12+
PD2-
64 63
PD13PD1+
65
PD12PD2+
66
56
J39
J40
29
J16
30
55 54 53
J31
31
C3
33µF
PD11+
PD3
67
PD11PD3+
68
PD10+
PD4-
VCC
Vcc
Vcc
J32
PD10PD4+
J33
32
33
52
C4
2.2µF
VCC
J17
Vcc
Vcc
J34
Vcc
Vcc
J35
GND
GND
J36
GND
GND
J37
J30
GND
34
VCC
GND
GND
Vcc
PD5-
PD5+
PD6-
PD6+
GND
Vcc
PD7-
PD7+
PD8-
PD8+
PD9-
PD9+
Vcc
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
J29
L1
C1
C5
56nH 0.1µF 1000pF
J18
GND
C2
0.01µF
VCC
VCC
VCC
C6
0.01µF
C10
1000pF
C7
0.01µF
C11
1000pF
C80
0.01µF
C12
1000pF
J19
J22
J24
J26
J28
J20
J21
J23
J25
C9
0.01µF
C13
1000pF
J27
VCC
Evaluates: MAX3950
J38
MAX3950 Evaluation Kit
Figure 2. MAX3950 EV Kit Schematic
3
Evaluates: MAX3950
MAX3950 Evaluation Kit
1.0"
Figure 3. MAX3950 EV Kit PC Board Layout—Solder Side
1.0"
Figure 4. MAX3950 EV Kit PC Board Layout—Power Plane
4
_______________________________________________________________________________________
MAX3950 Evaluation Kit
Evaluates: MAX3950
1.0"
Figure 5. MAX3950 EV Kit PC Board Layout—Ground Plane
1.0"
Figure 6. MAX3950 EV Kit PC Board Layout—Component Side
_______________________________________________________________________________________
5
Evaluates: MAX3950
MAX3950 Evaluation Kit
1.0"
Figure 7. MAX3950 EV Kit Component Placement Guide—Component Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 ______________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.