http://www.qsdaz.com Revised January 1999 CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer General Description The CD4051BC, CD4052BC, and CD4053BC analog multiplexers/demultiplexers are digitally controlled analog switches having low “ON” impedance and very low “OFF” leakage currents. Control of analog signals up to 15Vp-p can be achieved by digital signal amplitudes of 3 − 15V. For example, if VDD = 5V, VSS = 0V and VEE = −5V, analog signals from −5V to +5V can be controlled by digital inputs of 0 − 5V. The multiplexer circuits dissipate extremely low quiescent power over the full VDD−VSS and VDD−VEE supply voltage ranges, independent of the logic state of the control signals. When a logical “1” is present at the inhibit input terminal all channels are “OFF”. CD4051BC is a single 8-channel multiplexer having three binary control inputs. A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned “ON” and connect the input to the output. CD4052BC is a differential 4-channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 or 4 pairs of channels to be turned on and connect the differential analog inputs to the differential outputs. CD4053BC is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole double-throw configuration. Features ■ Wide range of digital and analog signal levels: digital 3 – 15V, analog to 15Vp-p ■ Low “ON” resistance: 80Ω (typ.) over entire 15Vp-p signal-input range for VDD − VEE = 15V ■ High “OFF” resistance: channel leakage of ±10 pA (typ.) at VDD − VEE = 10V ■ Logic level conversion for digital addressing signals of 3 – 15V (VDD − VSS = 3 – 15V) to switch analog signals to 15 Vp-p (VDD − VEE = 15V) ■ Matched switch characteristics: ∆RON = 5Ω (typ.) for VDD − VEE = 15V ■ Very low quiescent power dissipation under all digitalcontrol input and supply conditions: 1 µ W (typ.) at VDD − VSS = VDD − VEE = 10V ■ Binary address decoding on chip Ordering Code: Order Number CD4051BCM CD4051BCMTC CD4051BCN Package Number M16A MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4052BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4052BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4052BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4053BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4053BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4053BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 1999 Fairchild Semiconductor Corporation DS005662.prf www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer November 1983 CD4051BC • CD4052BC • CD4053BC Connection Diagrams Pin Assignments for DIP and SOIC CD4051BC CD4052BC CD4053BC Truth Table INPUT STATES “ON” CHANNELS INHIBIT C B A CD4051B CD4052B CD4053B 0 0 0 0 0 0X, 0Y cx, bx, ax 0 0 0 1 1 1X, 1Y cx, bx, ay 0 0 1 0 2 2X, 2Y cx, by, ax 0 0 1 1 3 3X, 3Y 0 1 0 0 4 cy, bx, ax 0 1 0 1 5 cy, bx, ay 0 1 1 0 6 cy, by, ax 0 1 1 1 7 1 * * * NONE *Don’t Care condition. www.fairchildsemi.com 2 cx, by, ay cy, by, ay NONE NONE CD4051BC • CD4052BC • CD4053BC Logic Diagrams CD4051BC CD4052BC 3 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Logic Diagrams (Continued) CD4053BC www.fairchildsemi.com 4 DC Supply Voltage (VDD ) Input Voltage (VIN) Recommended Operating Conditions −0.5 VDC to +18 VDC −0.5 VDC to VDD +0.5 VDC Input Voltage (VIN) −65°C to +150°C Range (TS) 0V to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) CD4051BC/CD4052BC/CD4053BC Dual-In-Line 700 mW Small Outline 500 mW (soldering, 10 seconds) 260°C DC Electrical Characteristics Parameter −40°C to +85°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics tables provide conditions for actual device operation. Lead Temperature (TL) Symbol +5 VDC to +15 VDC DC Supply Voltage (VDD) Storage Temperature (Note 2) −40°C Conditions Min +25° Max Min Typ +85°C Max Min Units Max Control A, B, C and Inhibit IIN Input Current VDD = 15V, VEE = 0V VIN = 0V VDD = 15V, VEE = 0V VIN = 15V IDD Quiescent Device Current −0.1 −10−5 0.1 10−5 −0.1 −1.0 µA 0.1 1.0 µA VDD = 5V 20 20 150 µA VDD = 10V 40 40 300 µA VDD = 15V 80 80 600 µA Signal Inputs (VIS) and Outputs (VOS) RON “ON” Resistance (Peak RL = 10 kΩ VDD = 2.5V, for VEE ≤ VIS ≤ VDD) (any channel VEE = −2.5V selected) or VDD = 5V, 850 270 1050 1200 Ω 330 120 400 520 Ω 210 80 240 300 Ω VEE = 0V VDD = 5V, VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V 5 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Absolute Maximum Ratings(Note 1) CD4051BC • CD4052BC • CD4053BC DC Electrical Characteristics Symbol Parameter (Continued) −40°C Conditions Min ∆RON ∆ “ON” Resistance RL = 10 kΩ VDD = 2.5V, Between Any Two (any channel VEE = −2.5V Channels selected) or VDD = 5V, +25° Max Min Typ +85°C Max Min Units Max 10 Ω 10 Ω 5 Ω VEE = 0V VDD = 5V VEE = −5V or VDD = 10V, VEE = 0V VDD = 7.5V, VEE = −7.5V or VDD = 15V, VEE = 0V “OFF” Channel Leakage VDD=7.5V, VEE=−7.5V ±50 ±0.01 ±50 ±500 nA CD4051 ±200 ±0.08 ±200 ±2000 nA D4052 ±200 ±0.04 ±200 ±2000 nA CD4053 ±200 ±0.02 ±200 ±2000 nA Current, any channel “OFF” O/I=±7.5V, I/O=0V “OFF” Channel Leakage Inhibit = 7.5V Current, all channels VDD = 7.5V, “OFF” (Common VEE = −7.5V, OUT/IN) O/I = 0V I/O = ±7.5V Control Inputs A, B, C and Inhibit VIL LOW Level Input Voltage VEE = VSS RL = 1 kΩ to VSS IIS<2 µA on all OFF Channels VIS = VDD thru 1 kΩ VDD = 5V 1.5 1.5 1.5 V VDD = 10V 3.0 3.0 3.0 V VDD = 15V VIH IIN HIGH Level Input Voltage Input Current 4.0 VDD = 5 3.5 4.0 V 3.5 V VDD = 10 7 7 7 V VDD = 15 11 11 11 V VDD = 15V, VEE = 0V VIN = 0V VDD = 15V, VEE = 0V VIN = 15V Note 2: All voltages measured with respect to VSS unless otherwise specified. www.fairchildsemi.com 4.0 3.5 6 −0.1 −10−5 0.1 10−5 −0.1 0.1 −1.0 1.0 µA µA (Note 3) Symbol Typ Max Units Propagation Delay Time from VEE = VSS = 0V 5V 600 1200 ns tPZL Inhibit to Signal Output RL = 1 kΩ 10V 225 450 ns (channel turning on) CL = 50 pF 15V 160 320 ns Propagation Delay Time from VEE = VSS = 0V 5V 210 420 ns Inhibit to Signal Output RL = 1 kΩ 10V 100 200 ns (channel turning off) CL = 50 pF 15V 75 150 ns Control input 5 7.5 pF Signal Input (IN/OUT) 10 15 pF tPHZ, tPLZ CIN COUT Parameter Conditions VDD tPZH, Min Input Capacitance Output Capacitance (common OUT/IN) CD4051 10V 30 pF 10V 15 pF 10V 8 pF 0.2 pF CD4051 110 pF CD4052 140 pF CD4053 70 pF 10V 0.04 % 10V 40 MHz 10V 10 MHz 10V 3 MHz CD4052 VEE = VSS = 0V CD4053 CIOS Feedthrough Capacitance CPD Power Dissipation Capacitance Signal Inputs (VIS) and Outputs (VOS) Sine Wave Response (Distortion) RL = 10 kΩ fIS = 1 kHz VIS = 5 Vp-p VEE = VSI = 0V Frequency Response, Channel RL = 1 kΩ, VEE = 0V, VIS = 5Vp-p, “ON” (Sine Wave Input) 20 log10 VOS/VIS = −3 dB Feedthrough, Channel “OFF” RL = 1 kΩ, VEE = VSS = 0V, VIS = 5Vp-p, 20 log10 VOS/VIS = −40 dB Crosstalk Between Any Two RL = 1 kΩ, VEE = VSS = 0V, VIS(A) = 5Vp-p Channels (frequency at 40 dB) 20 log10 VOS(B)/VIS(A) = −40 dB (Note 4) tPHL Propagation Delay Signal VEE = VSS = 0V 5V 25 55 tPLH Input to Signal Output CL = 50 pF 10V 15 35 ns 15V 10 25 ns 10V 65 ns Control Inputs, A, B, C and Inhibit Control Input to Signal Crosstalk VEE = VSS = 0V, RL = 10 kΩ at both ends of channel. mV (peak) Input Square Wave Amplitude = 10V tPHL, Propagation Delay Time from VEE = VSS = 0V 5V 500 1000 ns tPLH Address to Signal Output CL = 50 pF 10V 180 360 ns 15V 120 240 ns (channels “ON” or “OFF”) Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: A, B are two arbitrary channels with A turned “ON” and B “OFF”. 7 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC AC Electrical Characteristics TA = 25°C, tr = tf = 20 ns, unless otherwise specified. CD4051BC • CD4052BC • CD4053BC Special Considerations switch must not exceed 0.6V at T A≤25°C, or 0.4V at TA>25°C (calculated from RON values shown). No VDD current will flow through RL if the switch current flows into OUT/IN pin. In certain applications the external load-resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into IN/OUT pin, the voltage drop across the bidirectional Typical Performance Characteristics “ON” Resistance vs Signal Voltage for TA=25°C “ON” Resistance as a Function of Temperature for VDD−VEE=10V “ON” Resistance as a Function of Temperature for VDD−VEE=15V “ON” Resistance as a Function of Temperature for VDD−VEE=5V www.fairchildsemi.com 8 CD4051BC • CD4052BC • CD4053BC Switching Time Waveforms 9 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 10 CD4051BC • CD4052BC • CD4053BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 11 www.fairchildsemi.com CD4051BC • CD4052BC • CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer • Dual 4-Channel Analog Multiplexer/Demultiplexer • Triple 2-Channel Analog Multiplexer/Demultiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual–In–Line Package (PDIP), JEDEC MS–001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.