DATA SHEET MOS INTEGRATED CIRCUIT µPD16654 150/154 OUTPUT TFT-LCD GATE DRIVE The µPD16654 is a TFT-LCD gate driver. Because this gate driver has a level shift circuit for logic input, it can output a high gate scanning voltage in response to a CMOS-level input. Moreover, it can also drive both the XGA/SXGA panel (154 outputs) and SVGA panel (150 outputs) by changing the number of outputs over between 150 and 154. FEATURES • High breakdown voltage output (ON/OFF range: VDD2-VEE2 = 40 V MAX.) • 3.3 V CMOS level input • Number of output select function (150/154 outputs) ORDERING INFORMATION Part Number µPD16654N-××× Package TCP (TAB package) The TCP’s external shape is customized. To order your TCP’s external shape, please contact an NEC salesperson. Document No. S11647EJ1V0DS00 (1st edition) Date Published May 1998 N CP(K) Printed in Japan © 1998 µPD16654 1. BLOCK DIAGRAM R/L LS Osel LS CLK LS STVR LS OE1 LS OE2 LS OE3 LS SR1 SR2 SR3 O1 O2 O3 154-bit shift register SR152 SR153 SR154 O152 O153 LS (level shifter): Interfaces between 3.3 V CMOS level and VDD2-VEE1 level. 2 O154 LS STVL µPD16654 2. PIN CONFIGURATION (µPD16654N-××× ×××) ××× S154 S153 S152 S151 VDD2 STVL OE1 OE2 OE3 CLK R/L VCC Osel VSS STVR VEE1 VEE2 (Cupper plated surface) S4 S3 S2 S1 Caution This figure does not specify the TCP package. 3 µPD16654 3. PIN FUNCTIONS Pin Symbol Pin Name Description O1 to O154 Driver output pins Scan signal output pins that drive the gate electrode of a TFT-LCD. The status of each output pin changes in synchronization with the rising edge of shift clock CLK. The output voltage of the driver is VDD2 to VEE2. STVR STVL Start pulse input/output pin Input/output pin of the internal shift register. Start pulse signal is read at the rising edge of shift clock CLK and a scan signal is output from the driver output pin. The interface of this terminal is CMOS of 3.3 V. When Osel signal is Low level, start pulse goes up to high level at the 154th falling edge of shift clock CLK and goes down to low level at the 155th falling edge. And when Osel signal is High level, start pulse goes up to high level at the 150th falling edge of shift clock CLK and goes down to low level at the 151st falling edge. The output level is VCC-VSS (logic level). CLK Shift clock input Shift clock input for the internal shift register. The contents of internal shift register is shifted at the rising edge of CLK. R/L Shift direction switching input Shift direction switching input pin of the internal shift register. R/L = H (right shift) : STVR → O1 → O2 ··· O153 → O154 → STVL R/L = L (left shift) STVL → O154 → O153 ··· O2 → O1 → STVR OE1 OE2 OE3 Enable input This pin fixes the driver output to the L level when it is high. However, the shift register is not cleared. And, output enable actuation is asynchronous in the clock. And, refer to “RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL“. Osel Number of output select input Selects the number of outputs. Osel = L : 154 outputs (SVGA) Osel = H: 150 outputs (VGA, XGA, SXGA) When Osel = H (150 outputs), O76 through O79 outputs of the shift register are fixed to the VEE2 level. Fix this pin to VCC (VDD2) or VSS (VEE1) on TCP. VDD2 Positive power supply for driver Shared with internal logic and driver VCC Reference power supply 3.3 V ± 0.3 V. Reference power supply for level shifter: LS VSS Ground (GND) Connect this pin to the system ground. VEE1 Negative power supply for internal logic Negative power supply for internal logic VEE2 Negative power supply for driver Negative power supply for driver Caution 1. Power ON/OFF sequence To prevent the µPD16654 from damage due to latch up, turn on power in the order VCC → VEE1, VEE2 and VDD2 → logic input. Turn off power in the reverse order. Observe these power sequences even during transition period. 4 µPD16654 Caution 2. Inserting bypass capacitor Because the internal logic operates at a high voltage (VDD2-VEE1), insert a bypass capacitor of about 0.1 µF between the respective power pins as shown below to secure the noise margin of VIH and VIL. VDD2 VCC 0.1 µ F 0.1 µ F 0.1 µ F 0.1 µ F VSS VEE2 VEE1 Do not input a switching signal to the Osel pin that selects the number of outputs. Connect this pin to VCC or VSS (VEE1). 5 µPD16654 4. RELATIONS OF ENABLE INPUT AND OUTPUT TERMINAL Switching is possible for 154/150 with µPD16654 by the Osel terminal. And, the output terminal which can be controlled by the enable signal changes as follows along with this function. 154 out TCP 6 150 out Mode 154 out Mode (Osel = L) 150 out Mode (Osel = H) 154 out Mode (Osel = L) 150 out Mode (Osel = H) O1 (OE1) O1 (OE1) O1 (OE1) O1 (OE1) O2 (OE2) O2 (OE2) O2 (OE2) O2 (OE2) O3 (OE3) O3 (OE3) O3 (OE3) O3 (OE3) O4 (OE1) O4 (OE1) O4 (OE1) O4 (OE1) O5 (OE2) O5 (OE2) O5 (OE2) O5 (OE2) O6 (OE3) O6 (OE3) O6 (OE3) O6 (OE3) • • • • • • • • • • • • O72 (OE3) O72 (OE3) O72 (OE3) O72 (OE3) O73 (OE1) O73 (OE1) O73 (OE1) O73 (OE1) O74 (OE2) O74 (OE2) O74 (OE2) O74 (OE2) O75 (OE3) O75 (OE3) O75 (OE3) O75 (OE3) O76 (OE1) Vout = VEE2 O77 (OE2) Vout = VEE2 O78 (OE3) Vout = VEE2 O79 (OE1) Vout = VEE2 O80 (OE2) O80 (OE1) O80 (OE2) O80 (OE1) O81 (OE3) O81 (OE2) O81 (OE3) O81 (OE2) O82 (OE1) O82 (OE3) O82 (OE1) O82 (OE3) • • • • • • • • • • • • O150 (OE3) O150 (OE2) O150 (OE3) O150 (OE2) O151 (OE1) O151 (OE3) O151 (OE1) O151 (OE3) O152 (OE2) O152 (OE1) O152 (OE2) O152 (OE1) O153 (OE3) O153 (OE2) O153 (OE3) O153 (OE2) O154 (OE1) O154 (OE3) O154 (OE1) O154 (OE3) µPD16654 5. TIMING CHART (1) 154 outputs, R/L = H Osel = L 1 2 3 153 154 155 156 157 CLK OE1 OE2 OE3 STVR O1 O2 O3 O153 O154 STVL O1 of next stage O2 of next stage 7 µPD16654 (2) 150 outputs, R/L = H Osel = H 1 2 3 CLK OE1 OE2 OE3 STVR O1 O2 O3 O153 O154 STVL O1 of next stage O2 of next stage O76 to O79 is L (VEE2) level fixation (150 output). 8 149 150 151 152 153 µPD16654 6. ELECTRIC SPECIFICATION Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Supply Voltage VDD2 –0.5 to +28 V Supply Voltage VCC –0.5 to +7.0 V Supply Voltage VDD2-VEE1/2 –0.5 to 42 V Supply Voltage VEE1 –16.5 to +0.5 V Supply Voltage VEE2 VEE1 – 0.5 to +0.5 V Input Voltage VI –0.5 to VCC + 0.5 V Input Current II ±10 mA Output Current IO ±10 mA Operating Temperature Range TA –20 to +70 °C Storage Temperature Range Tstg –55 to +125 °C Recommended Operating Condition (TA = –20 to +80°C, VSS1 = VSS2 = 0 V) Parameter Symbol MIN. Supply Voltage VDD2 Supply Voltage TYP. MAX. Unit 17 25 V VEE1 –15 –5.0 V Supply Voltage VEE2 VEE1 VEE1 + 6.0 V Supply Voltage VDD2 – VEE1 22 40 V Supply Voltage VCC 3.0 3.6 V 3.3 Electrical Specifications (TA = –20 to +70°C, VDD1 = 25 V, VDD2 = 3.3 V ± 0.3 V, VEE1 = VEE2 = –15 V, VSS = 0 V) Parameter Symbol Input voltage, high VIH Input voltage, low VIL Condition CLK, STVR (STVL), R/L, Osel, OE1-OE3 MIN. TYP. MAX. Unit 0.8 VCC VCC V VSS 0.2 VCC V VOH STVR (STVL), IOH = –40 µA Output voltage, low VOL STVR (STVL), IOL = +40 µA Output current, high InOH On, Vn = VDD2 – 1.0 V Output current, low InOL On, Vn = VEE2 + 1.0 V Output ON resistance Ron Vn = VEE2 + 1.0 V or VDD2 – 1.0 V 1.0 kΩ Input leakage current IIL VI = 0 V or 3.6 V ±1.0 µA IDD2 VDD2, fCLK = 30 kHz, no loads 400 µA ICC VCC1, fCLK = 30 kHz, no loads 600 µA IEE IEE1 + IEE2, fCLK = 30 kHz, no loads 800 µA Output voltage, high Dynamic current Note VCC – 0.4 Note VSS Note VCC V Note VSS + 0.4 –1.0 1.0 V mA mA Note The cascade output is at the driver level (VCC-VSS). 9 µPD16654 Switching Characteristics (TA = –20 to +70°C, VDD1 = 25 V, VDD2 = 3.3 V ± 0.3 V, VEE1 = VEE2 = –15 V, VSS = 0 V) Parameter Cascade output delay time Symbol Condition MIN. TYP. MAX. Unit tPHL1 CL = 20 pF 800 ns tPLH1 CLK → STVL (STVR) 800 ns tPHL2 CL = 300 pF 500 ns tPLH2 CLK → On 500 ns tPHL3 CL = 300 pF 500 ns tPLH3 OEn → On 500 ns Output rise time tTLH CL = 300 pF 450 ns Output fall time tTHL 450 ns Input capacitance CI 15 pF Driver output delay time 1 Driver output delay time 2 Maximum clock frequency fmax. TA = 25°C When connected in cascade 500 kHz Timing Requirement (TA = –20 to +70°C, VDD1 = 25 V, VDD2 = 3.3 V ± 0.3 V, VEE1 = VEE2 = –15 V, VSS = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse Low Period PWCLK(H) 500 ns Clock Pulse High Period PWCLK(L) 500 ns Enable Pulse low period PWOE 1.0 µs Data Setup Time tSETUP STVR (STVL) ↑ → CLK ↑ 200 ns Data Hold Time tHOLD CLK ↑ → STVR (STVL) ↓ 200 ns The rise and fall times of logic input must be tr = tf = 20 ns (10% to 90%). 10 µPD16654 7. SWITCHING CHARACTERISTICS WAVEFORM (R/L = H) 1/fmax. PWCLK(H) PWCLK(L) VCC CLK 50% 50% 50% 50% VSS tSETUP tHOLD VCC STVL1/2 (STVR1/2) 50% 50% VSS tPLH1 tPHL1 VCC STVR1/2 (STVL1/2) 50% 50% VSS tPLH2 tTLH tPHL2 90% On tTHL VDD2 90% 10% 10% VEE2 PWOE VCC 50% OEn 50% VSS tPLH3 tPHL3 VEE2 VDD2 90% On VEE1 10% VEE1 VEE2 11 µPD16654 8. RECOMMENDED MOUNTING CONDITIONS When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel. Mounting Condition Thermocompression Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 sec; pressure 100 g (per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C; pressure 3 to 8 kg/cm ; time 3 to 5 sec. 2 Real bonding 165 to 180°C; pressure 25 to 45 kg/cm , time 30 to 40 secs. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.) 2 Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Reference NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC’s Semiconductor Devices (C11531E) 12 µPD16654 [MEMO] 13 µPD16654 [MEMO] 14 µPD16654 [MEMO] 15 µPD16654 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5