ETC CY2890-F02

CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
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Revision History
Version
2.1
2.2
2.3
DATE
2007/09/30
2007/11/20
2008/12/02
2.4
2009/01/16
Description
P4, update package as LQFP64
P10, update pull-up/pull-down resistor as TYP 80K
P4, remove 5V tolerant function.
P35, remove CY2890-F01, Outline 10x10x1.4mm package
P4,P10 supply voltage update as 2.7 V ~ 3.6 V
Ordering Information
Part No.
CY2890-F02
Package
64pin LQFP, Green package
Descriptions
Outline as 7x7x1.4mm
1
DigiTron
CY2890-F02 Datasheet Version 2.4
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Content
1.
General Description ...................................................................................................... 4
2.
Features......................................................................................................................... 4
3.
Block Diagram ............................................................................................................... 5
4.
Pin Assignment.............................................................................................................. 6
5.
Pin Description .............................................................................................................. 7
6.
Function Description..................................................................................................... 9
7.
DC Characteristics....................................................................................................... 10
8.
AC Characteristics ....................................................................................................... 11
9.
Built-in Patterns........................................................................................................... 27
10.
Waveforms ................................................................................................................... 30
11.
Package Information................................................................................................... 35
2
DigiTron
CY2890-F02 Datasheet Version 2.4
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1.
General Description
The CY2890-F02 is a digital TFT-LCD timing controller with built-in “dithering”, “reverse”, “dual”, “flicker” and
“pattern generator” functions. The input signal is digital R/G/B with HSYNC/VSYNC or DE. User can use the
MODE pin to select input signal to be either HSYNC mode or DE mode. The R/G/B input is fixed to 8 bits data
width and the output is always 6 bits. The convert from 8 bits RGB to 6 bits RGB can be either directly truncated
or dithering depends on the “DITHER” function is on or off. When DITHER is on CY2890 will emulate 8 bits gray
level on 6 bits RGB bus. The users will have a more vivid picture with dither function on. The “Reverse” function
is designed for reducing EMI. The key is to lower down the R/G/B transition count. The “dual” function can set
the output HCLK to latch the output data at both edges. Set “dual” on can lower down the HCLK frequency to
half. With the “Reverse” and “dual” functions, the board level system design can be relaxed. We also have a
built-in test pattern generator for users to do a quick final test or aging burning test. The built-in test pattern
generator has 24 very popular patterns. It will be free running when MODE = 1, HSYNC = 1 or MODE = 0, DE = 1.
You can stop the free-running built-in test pattern at any time. The “flicker” function is used to reduce the
flicker phenomenon. Beside all the functions we just mentioned, we also support 8 different panel resolutions,
which can be selected by external strap resistors. Through CY2890, all the necessary horizontal and vertical
control signals to TFT-LCD are handled automatically. This includes the polarity invert control. There is a built-in
power-on reset circuit in the chip, no need for user to add external reset circuit. If users want to extend the
power-on reset, an external capacitor can be added.
2. Features
Supporting 8 kinds of different digital TFT-LCD panels
800 x 480 (*), 640 x 480, 800 x 600, 1024 x 600, 1024 x 768, 720 x 480, 320 x 240, 480 x 272
Input can be HSYNC mode or DE mode
Support 16.7M colors dither function
Support FLICKER reduction function.
Support DUAL edge function
Support up/down, left/right scan control
Support REVERSE function.
Built-in test pattern generator with 24 popular patterns
Built-In Power-On reset circuit
Built-in polarity inverted function.
Provide source and gate drivers control timing.
Master clock frequency: 70 MHz max.
Single supply voltage : +2.7V to +3.6V
Wide temperature operation range -40°C / +95°C
ESD meet class3 criteria
HBM 4KV, MM 400V, LATCH-UP 100mA
64 LQFP Green Package
3
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3. Block Diagram
4
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4. Pin Assignment
RI1
RI0
DCLK
HCLK
VSS VDD DIO1
RO0 RO1 RO2 RO3 RO4 RO5 GO0 GO1 GO2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
RI2
49
32
GO3
RI3
50
31
GO4
RI4
51
30
GO5
RI5
52
29
BO0
RI6
53
28
BO1
RI7
54
27
BO2
GI0
55
26
BO3
GI1
56
25
BO4
GI2
57
24
BO5
GI3
58
23
LD
GI4
59
22
REV
GI5
60
21
POL
GI6
61
20
OEV
GI7
62
19
CKV
UDC
63
18
STV1
17
VSS
CY2890-F02
text
LRC
64
1
2
3
4
5
6
7
8
9
10
BI0
BI1
BI2
BI3
BI4
BI5
BI6
BI7
DE
VDD
MODEDIO2 STV2 RESETB
HSYNC
VSYNC
5
11
12
13
14
15
16
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5. Pin Description
Pin No.
Symbol
I/O
1
2
3
4
5
6
7
8
BI0
BI1
BI2
BI3
BI4
BI5
BI6
BI7
I
I
I
I
I
I
I
I
9
DE / TEST
I
10
HSYNC /
TEST
I
11
VSYNC
I
12
MODE
I
13
DIO2
I/O
14
STV2
I/O
15
16
17
RESETB
VDD
VSS
I
I
I
18
STV1
I/O
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
CKV
OEV
POL
REV
LD
BO5
BO4
BO3
BO2
BO1
BO0
GO5
GO4
GO3
GO2
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Description
Internal
Blue color data input, bit0 (LSB)
Blue color data input, bit1
Blue color data input, bit2.
Blue color data input, bit3.
Blue color data input, bit4.
Blue color data input, bit5.
Blue color data input, bit6.
Blue color data input, bit7 (MSB).
MODE = H : Data enable signal input, active high
MODE = L : enable built-in patterns when
DE = H, Stop when DE = L
MODE = L : Negative polarity horizontal sync input
MODE = H :enable built-in patterns when
HSYNC = H, Stop when HSYNC = L
Negative polarity vertical sync input
DE / SYNC mode select
H : DE mode
L : SYNC mode
Source driver start pulse 2
LRC = 0, output
LRC = 1, Tri-state
Gate driver start pulse 2.
UDC = 0, output
UDC = 1, Tri-state
Active low system reset pin
Power supply voltage.
Power supply ground.
Gate driver start pulse 1.
UDC = 0, Tri-state
UDC = 1, Output
Gate driver shift clock.
Gate driver output enable
Source driver polarity select
Source driver data reverse control.
Source driver latch pulse and output enable.
Blue color data output, bit5 (MSB).
Blue color data output, bit4.
Blue color data output, bit3.
Blue color data output, bit2.
Blue color data output, bit1.
Blue color data output, bit0 (LSB).
Green color data output, bit5 (MSB).
Green color data output, bit4.
Green color data output, bit3.
Green color data output, bit2.
6
pull-down
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
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Pin No.
Symbol
I/O
34
35
GO1
GO0
O
O
36
RO5
I/O
37
RO4
I/O
38
RO3
I/O
39
RO2
I/O
40
RO1
I/O
41
RO0
I/O
42
HCLK
O
43
DIO1
I/O
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD
VSS
DCLK
RI0
RI1
RI2
RI3
RI4
RI5
RI6
RI7
GI0
GI1
GI2
GI3
GI4
GI5
GI6
GI7
UDC
LRC
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Internal
Green color data output, bit1.
Green color data output, bit0 (LSB).
Red data output, bit5 (MSB).
Reven on/off setting
Red color data output, bit4.
Dual on/off setting
Red color data output, bit3
Dither on /off setting
Red color data output, bit2.
Panel resolution select bit 2, RES[2],
Red color data output, bit1.
Panel resolution select bit 1, RES[1],
Red color data output, bit0. (LSB)
Panel resolution select bit 0, RES[0],
Source driver clock
Source driver start pulse 1
LRC = 0, Tri-state
LRC = 1, Output
Power supply voltage.
Power supply ground.
Clock signal; latch input data at DCLK falling edge.
Red color data input, bit0 (LSB)
Red color data input, bit1.
Red color data input, bit2.
Red color data input, bit3.
Red color data input, bit4.
Red color data input, bit5.
Red color data input, bit6.
Red color data input, bit7 (MSB).
Green color data input, bit0 (LSB)
Green color data input, bit1
Green color data input, bit2.
Green color data input, bit3.
Green color data input, bit4.
Green color data input, bit5.
Green color data input, bit6.
Green color data input, bit7 (MSB).
Up / Down scan control.
Left / Right scan control.
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-down
pull-down
pull-down
pull-down
pull-up
pull-up
7
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6. Function Description
Panel Select Table for CY2890-F02
CY2890 can support 8 different kind panel resolutions. To select different panel resolution users have to add an
external pull-up resistors at pin39, 40 or 41. At power-on, CY2890 will read in pin39, 40 and 41 as RES[2:0].
In the table below, we mark “x” mean don’t do anything. We mark “pull-down” mean you have to add an external
resistor to GROUND.
RES[2:0] ( RO[2:0] )
RESOLUTION
CONNECTED TO PIN EXTERNAL
PULL-DOWN RESISTOR VALUE
Value
Pin39
( RO2 )
Pin40
( RO1 )
Pin41
( RO0 )
0
x
x
x
800x480
1
x
x
Pull-down
640x480
10K
2
x
Pull-down
X
800x600
10K
3
x
Pull-down
Pull-down
1024x600
10K
4
Pull-down
x
X
1024x768
10K
5
Pull-down
x
Pull-down
720x480
10K
6
Pull-down
Pull-down
X
320x240
10K
7
Pull-down
Pull-down
Pull-down
480x272
10K
No External Resistors
Dither/Dual/Reven Enable or Disable Setting Table for CY2890-F02
The 3 major function blocks, dither, dual and reven. They can be enabled or disabled by using an external strap
resistor. This strap resistor will be read into CY2890 during the power-on reset period. That means once you
make a change, in order to make the change activated, you have to redo the power on step.
PIN
NUMBER
NAME
STRAP
FUNCTION
36
RO5
REVEN
37
RO4
DUAL
38
RO3
DITHER
DESCRIPTION
REVEN function enable/disable
No connect : enable (internal pull-up)
Connect Pull-down : disable
DUAL function enable/disable
No connect : enable (internal pull-up)
Connect Pull-down : disable
DITHER function enable/disable
No connect : disable (internal pull-up)
Connect Pull-down : enable
8
CONNECTED TO PIN
EXTERNAL PULL-DOWN
RESISTOR VALUE
10K
10K
10K
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7. DC Characteristics
Absolute maximum ratings
PARAMETER
SYMBOL
RATING
UNIT
Power supply
VDD
2.5 to 3.8
V
Input voltage
VIN
-0.3 to VDD +0.3
V
Output voltage
VOUT
-0.3 to VDD +0.3
V
TSTG
-40 to 125
℃
Storage temperature
Recommended operating conditions
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Power supply
VDD
2.7
3.3
3.6
V
Input voltage
VIN
0
-
VDD
V
TOPR
-40
-
95
℃
Operating temperature
DC Electrical characteristics
PARAMETER
SYMBOL
CONDITION
No pull-up or
pull-down
No pull-up or
pull-down
MIN.
TYP.
MAX.
UNIT
-1
-
1
µA
-1
-
1
µA
-10
-
10
µA
REMARK
Input low current
IIL
Input high current
IIH
Tri-state leakage current
IOZ
Logic input low voltage
VIL
CMOS
-
-
0.3VDD
V
Note 1
Schmitt input low voltage
VSIL
CMOS
-
-
0.3VDD
V
Note 2
Logic input high voltage
Schmitt input high
voltage
VIH
CMOS
0.7VDD
-
-
V
Note 1
VSIH
CMOS
0.7VDD
-
-
V
Note 2
Output low voltage
VOL
IOL = 4mA
-
-
0.3VDD
V
Note 3
Output high voltage
VOH
IOH = -4mA
0.7VDD
-
-
V
Note 3
Output low voltage
VOL
IOL = 8mA
-
-
0.3VDD
V
Note 4
Output high voltage
Input pull up / down
resistance
VOH
IOH = -8mA
0.7VDD
-
-
V
Note 4
RI
VIL = 0V or VIH = VDD
-
80
-
K
Note 5
Note 1: MODE, UDC, LRC, RI0~RI7, GI0~GI7, BI0~BI7.
Note 2: DCLK, HSYNC, VSYNC, DE, RESETB
Note 3: CKV, POL, REV, LD, DIO1, DIO2, STV1, STV2, OEV, AP, RO0~RO5, GO0~GO5, BO0~BO5.
Note 4: HCLK
Note 5: RESETB, HSYNC, VSYNC, DE, MODE, UDC, LRC, RI0, RI1, GI0, GI1, BI0, BI1, RO0~RO5
9
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8. AC Characteristics
SYNC mode Input signal characteristic, 800 x 480
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
2534-29.540
11.2-11.2---3
8909281600
-48-4088
800
THP – THW - THBP - THV
THP – THV
514525960
-329
480
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
2534
-29.5
11.211.2-0.450.50
55-820928
800
THP - THV
485525
480
TVP - TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 800 x 480
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
10
MAX
40
3
0.55
6
1600
960
6
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Output Signal Characteristics, 800 x 480
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN).
4 (MIN)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
66
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
11
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SYNC mode Input signal characteristic, 640 x 480
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
2534-29.540
11.2-11.2---3
7909001280
-96-48144
640
THP – THW - THBP - THV
THP – THV
518525960
-333
480
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
2534
-29.5
11.211.2-0.450.50
55-660800
640
THP - THV
485525
480
TVP - TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 640 x 480
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
12
MAX
40
3
0.55
6
1280
960
6
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Output Signal Characteristics, 640 x 480
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
66
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
13
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 800 x 600
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
2025-4050
99--3
89010001600
-48-4088
800
THP – THW - THBP - THV
THP – THV
6406601200
-336
600
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
2025
-40
99-0.450.50
55-8201000
800
THP – THV
605660
600
TVP - TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 800 x 600
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
14
MAX
50
3
0.55
6
1600
1200
6
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ;543158798 廖先生
Output Signal Characteristics, 800 x 600
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
100
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
15
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 1024 x 600
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
14.315.4-6570
6.56.5--3
119012802047
-80-80160
1024
THP – THW - THBP - THV
THP – THV
6406601200
-336
600
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
14.315.4
-65
6.5
6.5
-0.450.50
55-10441280
1024
THP – THV
605660
600
TVP - TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 1024 x 600
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
16
MAX
70
3
0.55
4
2047
1200
4
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ;543158798 廖先生
Output Signal Characteristics, 1024 x 600
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
160
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
17
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 1024 x 768
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
14.315.4-6570
6.56.5--3
119012802047
-80-80160
1024
THP – THW - THBP - THV
THP – THV
8128451536
-340
768
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
14.315.4
-65
6.5
6.5
-0.450.50
55-10441280
1024
THP – THV
773845
768
TVP – TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 1024 x 768
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
18
MAX
70
3
0.55
4
2047
1536
4
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
Output Signal Characteristics, 1024 x 768
PARAMETER
HCLK FREQUENCY
HCLK FREQUENCY
SYMBOL
FHCLK
1/2FHCLK
VALUE
1
0.5
UNIT
FCLK
FCLK
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
TSU
4 (MIN.)
NS
HCLK RISING TO DATA, REV, DIO VALID
POL PULSE WIDTH
THD
TPOL
4 (MIN.)
1
NS
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
160
0.5
THCLK
THP
TIME FROM LD TO CKV
TGS
1
THCLK
TIME FROM LD TO DIO
TIME FROM THE LAST DATA TO LD
TLDO
TED
THBK – 9
9
THCLK
THCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
NORMAL
DUAL
19
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 720 x 480
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
2534-29.540
11.2-11.2---3
8049001440
-40-4080
720
THP – THW - THBP - THV
THP – THV
515525960
-329
480
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
2534
-29.5
11.211.2-0.450.50
55-740900
720
THP – THV
485525
480
TVP – TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 720 x 480
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
20
MAX
40
3
0.55
6
1440
960
6
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
Output Signal Characteristics, 720 x 480
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
66
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
21
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 320 x 240
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
28.693-10.735
12.812.8--3
370416512
-26-2046
320
THP – THW - THBP - THV
THP – THV
260288360
-315
240
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
28.693
-10.7
12.8
12.8
-0.450.50
55-340416
320
THP – THV
245288
240
TVP – TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 320 x 240
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
22
MAX
35
3
0.55
6
512
360
6
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
Output Signal Characteristics, 320 x 240
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
50
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
23
DigiTron
CY2890-F02 Datasheet Version 2.4
cyti Confidential, DO NOT COPY
中国大陆区销售电话:0755-83015886
13641469108 QQ:543158798 廖先生
SYNC mode Input signal characteristic, 480 x 272
PARAMETER
CLOCK PERIOD
CLOCK FREQUENCY
CLOCK LOW LEVEL WIDTH
CLOCK HIGH LEVEL WIDTH
CLOCK RISE, FALL TIME
HSYNC PERIOD
HSYNC PULSE WIDTH
HSYNC BACK PORCH
HSYNC WIDTH + BACK PORCH
HORIZONTAL VALID DATA WIDTH
HSYNC FRONT PORCH
HORIZONTAL BLANK
VSYNC PERIOD
VSYNC PULSE WIDTH
VSYNC BACK PORCH
VERTICAL DATA VALID WIDTH
VSYNC FRONT PORCH
VERTICAL BLANK
DATA SETUP TIME
DATA HOLD TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, TCLKF
THP
THW
THBP
THW+ THBP
THV
THFP
THBK
TVP
TVW
TVBP
TW
TVFP
TVBK
TDS
TDH
MIN.TYP.MAX.
28.693-10.735
12.812.8--3
550600960
-36-3066
480
THP – THW - THBP - THV
THP – THV
297299544
-319
272
TVP – TVW - TVBP - TW
TVP – TW
5-5--
UNIT
NS
MHZ
NS
NS
NS
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
TCLK
THP
THP
THP
THP
THP
THP
NS
NS
REMARK
MINTYP
28.693
-10.7
12.8
12.8
-0.450.50
55-500600
480
THP – THV
277299
272
TVP – TW
55--
UNIT
NS
MHZ
NS
NS
NS
NS
NS
NS
TCLK
TCLK
TCLK
THP
THP
THP
NS
NS
NS
REMARK
DE mode Input signal characteristics, 480 x 272
PARAMETER
PERIOD
FREQUENCY
LOW LEVEL WIDTH
DCLK
HIGH LEVEL WIDTH
RISE, FALL TIME
DUTY
SETUP TIME
HOLD TIME
RISE, FALL TIME
HORIZONTAL PERIOD
HORIZONTAL VALID
HORIZONTAL BLANK
DE
VERTICAL PERIOD
VERTICAL VALID
VERTICAL BLANK
SETUP TIME
HOLD TIME
RISE, FALL TIME
SYMBOL
TCLK
FCLK
TWCL
TWCH
TCLKR, CLKF
TDES
TDEH
TDER, TDEF
THP
THV
THBK
TVP
TW
TVBK
TDS
TDH
TDR, TDF
DATA
24
MAX
35
3
0.55
6
960
544
6
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Output Signal Characteristics, 480 x 272
PARAMETER
SYMBOL
VALUE
UNIT
HCLK FREQUENCY
HCLK FREQUENCY
NORMAL
DUAL
FHCLK
1/2FHCLK
1
0.5
FCLK
FCLK
HCLK PERIOD
HCLK PERIOD
NORMAL
DUAL
THCLK
2THCLK
1
2
TCLK
TCLK
DATA, REV DIO VALID TO HCLK RISING
HCLK RISING TO DATA, REV, DIO VALID
TSU
THD
4 (MIN.)
4 (MIN.)
NS
NS
POL PULSE WIDTH
TPOL
1
THP
POL VALID TO LD RISING
LD RISING TO POL VALID
TPSU
TPHD
0.5 THP + 12
THP - TPSU
THCLK
THCLK
STV PULSE WIDTH
STV VALID TO CKV RISING
TSTV
TVSU
1
0.5
THP
THP
CKV RISING TO STV VALID
TVHD
0.5
THP
DIO PULSE WIDTH
LD PULSE WIDTH
TDIOW
TLDW
1
4
THCLK
THCLK
OEV PULSE WIDTH
CKV PULSE WIDTH
TOEV
TCKV
50
0.5
THCLK
THP
TIME FROM LD TO CKV
TIME FROM LD TO DIO
TGS
TLDO
1
THBK – 9
THCLK
THCLK
TIME FROM THE LAST DATA TO LD
TED
9
THCLK
25
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CY2890-F02 Datasheet Version 2.4
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9. Built-in Patterns
Pattern 00:
Black background with white cross line,
White line boundary./one pixel
Pattern 04:
Black and white checkerboard
four pixels
Pattern 01:
White cross hatch and dot
4 border lines
Left-red, right-green,up-blue,dn-yellow
Pattern 05:
Black and white checkerboard
two pixels
Pattern 02:
Black cross hatch and dot
4 border lines
Left-red, right-green,up-blue,dn-yellow
Pattern 06:
Black and white checkerboard
one pixel
Pattern 03:
Diagonal color
Pattern 07:
Vertical black and white bar
Two pixels
.
26
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Pattern 08:
2 gray levels, dither off => 61,62
8 gray levels, dither on => 240 to 247
Pattern 12:
256 green grayscale / two pixels
From 0 to 255
Pattern 09:
32 white gray levels
From 0 to 255
Pattern 13:
256 blue grayscale / two pixels
From 0 to 255
Pattern 10:
256 white grayscale / two pixels
From 0 to 255
Pattern 14:
Vertical colors bar.
Pattern 11:
256 red grayscale / two pixels
From 0 to 255
Pattern 15:
Horizontal colors bar.
27
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Pattern 16:
Black with white line boundary.
Pattern 20:
Blue with white line boundary.
Pattern 17:
White with red line boundary.
Pattern 21:
Yellow with white line boundary.
Pattern 18:
Red with white line boundary.
Pattern 22:
Magenta with white line boundary.
Pattern 19:
Green with white line boundary.
Pattern 23:
Cyan with white line boundary.
28
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10. Waveforms
Waveform 1: HSYNC mode input vertical timing - 1
Waveform 2: HSYNC mode input vertical timing - 2
29
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Waveform 3 : HSYNC mode, 800x480, Horizontal timing 1
Waveform 4 : HSYNC mode, 800x480, Horzontal timing 2
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Waveform 5 : DE mode, 800x480, Vertical timing
Waveform 6 : DE mode, 800x480, Horizontal timing
31
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Waveform 7: input clock, setup/hold time
32
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Waveform 8 : 800 x 480, Output timing – 1
33
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11. Package Information
CY2890-F02 : LQFP 64 pins (7x7x1.4mm)
34
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