ETC TMP90C801F

TOSHIBA
TLCS-90 Series
TMP90C800/801
CMOS 8–Bit Microcontrollers
TMP90C800N/TMP90C801N
TMP90C800F/TMP90C801F
1. Outline and Characteristics
The TMP90C800 is a high-speed advanced 8-bit microcontroller
applicable to a variety of equipment.
With its 8-bit CPU, ROM, RAM, timer/event counter and general-purpose serial interface integrated into a single CMOS chip,
the TMP90C800 allows the expansion of external
memories for programs and data (up to 56K bytes). The function of
TMP90C800 is exactly same as the TMP90C400 except the
internal ROM/RAM size.
The TMP90C801 is the same as the TMP90C800 but
without the ROM.
The TMP90C800N/801N is in a shrink Dual Inline Package
(SDIP64-P-750).
The TMP90C800F/801F is in a Quad Flat package
(QFP64-P-1420A)
The characteristics of the TMP90C800 include:
(1)
(2)
Powerful instructions: 163 basic instructions, including
Multiplication, division, 16-bit arithmetic operations, bit
manipulation instructions
Minimum instruction executing time: 320ns (at
12.5MHz oscillation frequency)
(3)
Internal ROM: 8K bytes (The TMP90C801 does not
have a built-in ROM)
(4)
Internal RAM: 256 bytes
(5)
Memory expansion
External memory: 56K bytes
(6)
General-purpose serial interface (1 channel)
Asynchronous mode, I/O interface mode
(7)
8-bit timers (4 channel): (2 external clock input)
(8)
Port with zero-cross detection circuit (4 input)
(9)
Input/Output ports (56 pins)
- Ports with programmable pull-up resistor (22 pins)
- Allows I/O selection on bit basis
- Multiplexer ports of address data bus
(10) Interrupt function: 7 internal interrupts and 3 external
interrupts
(11) Micro Direct Memory Access (DMA) function (8 channels)
(12) Standby function (4 HALT modes)
The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
TOSHIBA CORPORATION
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TMP90C800/801
Figure 1. TMP90C800 Block Diagram
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TMP90C800/801
2. Pin Assignment and Functions
This section describes the assignment of input/output pins, their
names and functions.
2.1 Pin Assignment
Figure 2.1 shows pin assignment of the TMP90C800N/801N.
Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package)
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TMP90C800/801
Figure 2.1 (2) shows Pin Assignment of the TMP90C800F/
801F.
Figure 2.1 (2). Pin Assignment (Flat Package)
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TMP90C800/801
2.2 Pin Names and Functions
The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
No. of pins
P00 ~ P07
/AD0 ~ AD7
8
P10 ~ P17
/A8 ~ A15
8
P20 ~ P23
4
I/O
1
P25
/WAIT
1
P27
/WR
3 states
I/O
P24
/NMI
P26
/RD
I/O 3 states
Output
Port 0: 8-bit I/O port that allows selection of input/output on byte basis
Address/Data bus: Functions as 8-bit bidirectional address/data bus for external memory (For 401, fixed to
address/data bus)
Port 1: 8-bit I/O port that allows selection on byte basis
Address bus: Functions as address bus (upper 8 bits) by EXT1 set for external memory (For 401, fixed to
address bus
I.O
Port 20 ~ 23: 4-bit I/O port with a pull-up resistor that can be programmed, and allows selection of
input/output on bit basis
I/O
Port 24: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of
input/output on bit basis
Non-maskable interrupt request pin: Falling edge interrupt register pin
Input
1
1
I/O
Port 25: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Input
Wait: Input pin for connecting slow speed memory of peripheral LSI
Output
Port 26: 1-bit output port
Output
Read: Generates strobe signal for reading external memory (For 401, fixed to RD)
Output
Port 27: 1-bit output port
Output
Read: Generates strobe signal for writing into external memory (For 401, fixed to WR)
I/O
P30
/INTO
Function
1
Port 30: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
Input
Port 31: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
P31
/INT1
1
P32
/TI0
1
P33
/TI2
1
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Input
I/O
Interrupt request pin 1: Rising edge interrupt request pin
Port 32: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Input
Timer input 0: Counter input pin for Timer 0
Output
Port 33: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Timer input 2: Counter input pin for Timer 2
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TMP90C800/801
Table 2.2 Pin Names and Functions (2/2)
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P35
/RxD
1
P36
/SCLK
1
P37
TxD
1
P40 ~ P47
8
I/O
Port 35: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
I/O
Receive serial data
I/O
Port 36: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Output
I/O
Output
Serial clock output
Port 37: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on
bit basis
Transmitter serial data
I/O
Port 4: 8-bit I/O port that allows I/O selection on bit basis
Port 5: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit
basis
P50 ~ P57
8
I/O
P60 ~ P67
8
I/O
Port 6: 8-bit I/O port that allows I/O selection on bit basis
ALE
1
Output
Address latch enable signal: The negative edge ALE supplies an address latch timing on AD0 ~ A07 for
external memory
EA
1
Input
External access: Connects with VCC pin in the TMP90C400 using internal ROM, and with GND pin in the
TMP90C401 with no internal ROM
CLK
1
Output
Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting.
RESET
1
Input
Reset: Initializes the TMP90C400/401 (Built-in pull-up resistor)
X1/X2
2
Input/Output
VCC
1
–
Power supply (+5V)
VSS
1
–
Ground (0V)
Pin for quartz crystal or ceramic resonator (1 ~ 12.5MHz)
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TMP90C800/801
3. Operation
(2)
This chapter describes the functions and the basic operations
of the TMP90C400/401 in every block.
The function of TMP90C800 is exactly same as that of
TMP90C400 except the internal ROM/RAM size. Refer to the
TMP90C400 except the function which are not described this
section.
The TMP90C800 also contains a 256-byte RAM,
which is allocated to the address space from FF80H to
FF7FH. The CPU allows the access to a certain RAM
area (FF00H to FF7FH, 256 bytes) by a short operation
code (opcode) in a “direct addressing mode”.
The addresses from FF20H to FF5FH in this RAM area
can be used as parameter area for micro DMA processing
(and for any other purposes when the micro DMA
function is not used).
3.1 CPU
The TMP90C800 includes a high performance 8-bit CPU. For
the function of the CPU, see the book TLCS Series CPU
Core Architecture concerning CPU operation.
3.2 Memory Map
The TMP90C800 supports a program memory of up to 56K
bytes.
The program and data memory may be assigned to the
address space from 0000H to FFFFH.
(1)
Internal ROM
The TMP90C800 internally contains an 8K-byte ROM.
The address space from 0000H to 1FFFH is provided
to the ROM. The CPU starts executing a program from
0000H by resetting.
The addresses 0010H to 005FH in this internal ROM area
are used for the entry area for the interrupt processing.
The TMP90C801 does not have a built-in ROM; therefore,
the address space 0000H to 1FFFH is used as external memory space.
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Internal RAM
(3)
Internal I/O
The TMP90C800 provides a 32-byte address space as
an internal I/O area, whose addresses range from FF80H
to FF9FH. This I/O area can be accessed by the CPU
using a short opcode in the “direct addressing mode”.
Figure 3.1 is a memory map indicating the areas
accessible by the CPU in the respective addressing
mode.
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TMP90C800/801
Figure 3.2 (a). Memory Map of TMP90C800
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TMP90C800/801
Figure 3.2 (b). Memory Map of TMP90C801
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TMP90C800/801
4. Electrical Characteristics (Preliminary)
TMP90C800N/TMP90C800F/
TMP90C801N/TMP90C801F
4.1 Absolute Maximum Ratings
Symbol
Parameter
VCC
Supply voltage
VIN
Input voltage
Unit
-0.5 ~ + 7
V
-0.5 ~ VCC + 0.5
V
F 500
Power dissipation (Ta = 85°C)
PD
Rating
mW
N 600
260
°C
TSTG
Storage temperature
-65 ~ 150
°C
TOPR
Operating temperature
-40 ~ 85
°C
TSOLDER
Soldering temperature (10s)
4.2 DC Characteristics
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
TA = -20 ~ 70°C (1 ~ 12.5MHz)
Symbol
VIL
Parameter
Input Low Voltage (P0)
Min
Max
Unit
Test Conditions
-0.3
0.8
V
–
VIL1
P1, P2, P3, P4, P5, P6
-0.3
0.3VCC
V
–
VIL2
RESET, NMI
-0.3
0.25VCC
V
–
VIL3
EA
-0.3
0.3
V
–
VIL4
X1
-0.3
0.2VCC
V
–
VIH
Input High Voltage (P0)
2.2
VCC + 0.3
V
–
VIH1
P1, P2, P3, P4, P5, P6
0.7VCC
VCC + 0.3
V
–
VIH2
RESET, NMI
0.75VCC
VCC + 0.3
V
–
–
VIH3
EA
VCC - 0.3
VCC + 0.3
V
VIH4
X1
0.8VCC
VCC + 0.3
V
VOL
Output Low Voltage
–
0.45
V
IOL = 1.6mA
VOH
VOH1
VOH2
Output High Voltage
2.4
0.75VCC
0.9VCC
–
V
V
V
IOH = -400µA
IOH = -100µA
IOH = -20µA
IDAR
Darlington Drive Current
(8 I/O pins) (Note)
-0.1
-3.5
mA
VEXT = 1.5V
REXT = 1.1kΩ
–
ILI
Input Leakage Current
0.02 (Typ)
±5
µA
0.0 ≤ Vin ≤ VCC
ILO
Output Leakage Current
0.05 (Typ)
± 10
µA
0.2 ≤ Vin ≤ VCC - 0.2
Operating Current (RUN)
Idle 1
Idle 2
20 (Typ)
1.5 (Typ)
6 (Typ)
40
5
15
mA
mA
mA
tosc = 10MHz
(25%Up @12.5MHz)
0.05 (Typ)
50
10
µA
µA
0.2 ≤ Vin ≤ VCC - 0.2
6
V
VIL2 = 0.2VCC,
VIH2 = 0.8VCC
ICC
STOP (TA = -40 ~ 85°C)
STOP (TA = 0 ~ 50°C)
VSTOP
Power Down Voltage (@STOP)
RRST
RESET Pull Up Register
50
150
KΩ
CIO
Pin Capacitance
–
10
pF
VTH
Schmitt width RESET, NMI
0.4
1.0 (Typ)
V
2
RAM BACK UP
–
testfreq = 1MHz
–
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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TMP90C800/801
4.3 AC Characteristics
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70°C (1 ~ 12.5MHz)
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
80
1000
100
–
80
–
ns
ns
tOSC
Oscillation cycle ( = x)
tCYC
CLK Period
4x
4x
400
–
320
–
tWH
CLK High width
2x - 40
–
160
–
120
–
ns
tWL
CLK Low width
2x - 40
–
160
–
120
–
ns
ns
tAL
A0 ~ 7 effective address→ALE fall
0.5x - 15
–
35
–
25
–
tLA
ALE fall →A0 ~ 7 hold
0.5x - 15
–
35
–
25
–
ns
tLL
ALE Pulse width
x - 40
–
60
–
40
–
ns
tLC
ALE fall RD/WR fall
0.5x - 30
–
20
–
10
–
ns
tCL
RD/WR →ALE rise
0.5x - 20
–
30
–
20
–
ns
tACL
A0 ~ 7 effective address →RD/WR fall
x - 25
–
75
–
55
–
ns
tACH
Upper effective address →RD/WR fall
1.5x - 50
–
100
–
70
–
ns
tCA
RD/WR fall →Upper address hold
0.5x - 20
–
30
–
20
–
ns
tADL
A0 ~ 7 effective address →Effective data input
–
3.0x - 35
–
265
–
205
ns
tADH
Upper effective address →Effective data input
–
3.5x - 55
–
295
–
225
ns
tRD
RD fall →Effective data input
tRR
RD Pulse width
tHR
RD rise →Data hold
tRAE
RD rise→ Address enable
tWW
WR pulse width
tDW
Effective data→WR rise
tWD
WR rise→Effective data hold
tACKH
–
2.0x - 50
–
150
–
110
ns
2.0x - 40
–
160
–
120
–
ns
0
–
0
–
0
–
ns
x - 15
–
85
–
65
–
ns
2.0x - 40
–
160
–
120
–
ns
2.0x - 50
–
150
–
110
–
ns
0.5x - 10
–
40
–
30
–
ns
Upper address→CLK fall
2.5x - 50
–
200
–
150
–
ns
tACKL
Lower address →CLK fall
2.0x - 50
–
150
–
110
–
ns
tCKHA
CLK fall→Upper address hold
1.5x - 80
–
70
–
40
–
ns
tCCK
RD/WR→CLK fall
x - 25
–
75
–
55
–
ns
tCKHC
CLK fall→RD/WR rise
x - 60
–
40
–
20
–
ns
tDCK
Valid data CLK fall
x - 50
–
50
–
30
–
ns
tCWA
RD/WR fall→Valid WAIT
–
x - 40
–
60
–
40
ns
tAWAL
Lower address →Valid WAIT
–
2.0x - 70
–
130
–
90
ns
tWAH
CLK fall →Valid WAIT hold
0
–
0
–
0
–
ns
tAWAH
Upper address →Valid WAIT
–
2.5x - 70
–
180
–
130
ns
tCPW
CLK fall →Port Data Output
–
x + 200
–
300
–
280
ns
tPRC
Port Data Input →CLK fall
200
–
200
–
200
–
ns
tCPR
CLK fall →Port Data hold
100
–
100
–
100
–
ns
AC Measuring Conditions
• Output level: High 2.2V/Low 0.8V, CL = 50pF
(However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR)
• Input level: High 2.4V/Low 0.45V (AD0 ~ AD7)
High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7)
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TMP90C800/801
4.4 Zero-Cross Characteristics
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
TA = -20 ~ 70°C (1 ~ 12.5MHz)
Symbol
Parameter
VZX
Zero-cross detection input
AZX
Zero-cross accuracy
FZX
Zero-cross detection input frequency
Condition
Min
Max
Unit
VAC p-p
AC coupling C = 0.1µF
1
1.8
50/60Hz sine wave
–
135
mV
–
0.04
1
kHz
4.5 Serial Channel Timing-I/O Interface Mode
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
CL = 50pF TA = -20 ~ 70°C (1 ~ 12.5MHz)
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tSCY
Serial Port Clock Cycle Time
8x
–
800
–
640
–
ns
tOSS
Output Data Setup SCLK Rising Edge
6x - 150
–
450
–
330
–
ns
tOHS
Output Data Hold After SCLK Rising Edge
2x - 120
–
80
–
40
–
ns
tHSR
Input Data Hold After SCLK Rising Edge
0
–
0
–
0
–
ns
tSRD
SCLK Rising Edge to Input DATA Valid
–
6x - 150
–
450
–
330
ns
4.6 8-bit Event Counter
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
TA = -20 ~ 70°C (1 ~ 12.5MHz)
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
tVCK
TI2 clock cycle
8x + 100
–
900
–
740
–
ns
tVCKL
TI2 Low clock pulse width
4x + 40
–
440
–
360
–
ns
tVCKH
TI2 High clock pulse width
4x + 40
–
440
–
360
–
ns
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TMP90C800/801
4.7 Interrupt Operation
VCC = 5V ± 10% TA = -40 ~ 85°C (1 ~ 10MHz)
TA = -20 ~ 70°C (1 ~ 12.5MHz)
Variable
Symbol
10MHz Clock
12.5MHz Clock
Parameter
Unit
Min
Max
Min
Max
Min
Max
4x
–
400
–
320
–
ns
4x
–
400
–
320
–
ns
8x + 100
–
900
–
740
–
ns
8x + 100
–
900
–
740
–
ns
NMI, INT0 Low level pulse width
tINTAL
tINTAH
NMI, INT0 High level pulse width
INT1, INT2 Low level pulse width
tINTBL
INT1, INT2 High level pulse width
tINTBH
4.8 I/O Interface Mode Timing
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TMP90C800/801
4.9 Timing Chart
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