9 81 51 44 71 85 ， QQ ： IT6610 ITE TECH. INC. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 Single-Link HDMI Transmitter www.ite.com.tw Aug-2009 Rev:1.2 1/27 IT6610 General Description 71 44 51 81 9 The IT6610 is a high-performance and low-cost single channel HDMI transmitter, fully compliant with HDMI 1.2, HDCP 1.1 and backward compatible to DVI 1.0 specifications. The IT6610 serves to provide the most cost-effective HDMI solution for DTV-ready consumer electronics such as settop boxes, DVD players and A/V receivers, as well as DTV-enriched PC products such as notebooks and desktops, without compromising the performance. Its backward compatibility to DVI standard allows connectivity to myriad video displays such as LCD and CRT monitors, in addition to the ever-so-flourishing flat panel TVs. 85 ， QQ ： Aside from the various video output formats supported, the IT6610 also supports 2 channels of I2S digital audio, with sampling rate up to 192kHz and sample size up to 24 bits. IT6610 also support S/PDIF input of up to 192kHz sampling rate. 18 66 43 41 5 By default the IT6610 comes with integrated HDCP ROMs which are pre-programmed with HDCP keys that ensures secure digital content transmission. Users need not worry about the procurement and maintainence of the HDCP keys. ， Features 深 圳 市 金 合 讯 科 技 有 限 公 司 Single channel HDMI transmitter Compliant with HDMI 1.2, HDCP 1.1 and DVI 1.0 specifications Supporting pixel rates from 25MHz to 165MHz DTV resolutions: 480i, 576i, 480p, 576p, 720p, 1080i up to 1080p PC resolutions: VGA, SVGA, XGA, SXGA up to UXGA Various video input interface supporting digital video standards such as: 24-bit RGB/YCbCr 4:4:4 16/20/24-bit YCbCr 4:2:2 8/10/12-bit YCbCr 4:2:2 (CCIR-656) 12-bit double data rate interface Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with programmable coefficients. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2 Dithering for conversion from 12-bit component and 8-bit Digital audio input interface supporting audio sample rate: 32~192 kHz sample size: 16~24 bits one I2S interface supporting 2-channel audio www.ite.com.tw Aug-2009 Rev:1.2 2/27 IT6610 51 44 71 ： QQ 85 ， 81 9 S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio transmission at up to 192kHz Compatible with IEC 60958 and IEC 61937 Software programmable HDMI output current, enabling user to optimize the performance for fixed-cable systems or those with pre-defined cable length MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK. Integrated pre-programmed HDCP keys Purely hardware HDCP engine increasing the robustness and security of HDCP operation Monitor detection through Hot Plug Detection and Receiver Termination Detection Intelligent, programmable power management 64-pin QFN package RoHS Compliant ( 100% Green available ) IT6610FN 0~70 Package Type Green/Pb free Option 64-pin QFN Green 18 66 Temperature Range 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Model 43 41 5 Ordering Information www.ite.com.tw Aug-2009 Rev:1.2 3/27 IT6610 TX2M AVCC TX1P TX1M AGND TX0P TX0M AVCC TXCP TXCM REXT PVCC1 PGND1 ENTEST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 TX2P 32 33 16 PCSCL 34 15 PCSDA 35 IVDD 36 OVDD 37 D23 38 D22 39 D21 40 D20 41 D19 42 D18 43 D17 44 D16 45 D15 46 D14 47 IVDD 48 DDCSCL 44 SYSRSTN 51 81 PCADR Pin Diagram QQ 58 59 60 61 62 63 64 D4 D3 D2 D1 D0 讯 科 57 14 HPD 13 INT# 12 IVDD 11 IVSS 10 OVDD 9 SCK 8 WS 7 I2S0 6 MCLK 5 SPDIF 4 IVDD 3 VSYNC 2 HSYNC 1 DE Figure 1. IT6610 pin diagram 深 圳 市 金 合 56 OVDD D10 55 D5 D11 54 D6 D12 53 D7 52 D8 51 PCLK 50 D9 49 D13 技 有 限 公 司 ， 18 66 43 41 5 HDMI-1.2 TX QFN-64 9X9 (Top View) 85 ， IT6610 ： 71 DDCSDA www.ite.com.tw Aug-2009 Rev:1.2 4/27 IT6610 Pin Description Digital Video Input Pins Pin Name Direction Description D[23:0] Input Digital video input pins. D[23:12] are only used in 24-bit Type Pin No. LVTTL 38-47, 49-53, be tied to ground. 55-58, 51 81 9 single-edged mode. In 12-bit, dual-edged mode D[23:12] should HSYNC Input Horizontal sync. signal VSYNC Input Vertical sync. signal PCLK Input Input data clock QQ 85 ， Description MCLK Input Audio master clock input SCK Input I2S serial clock input WS Input I2S word select input I2S0 Input I2S serial data input SPDIF Input S/PDIF audio input 1 LVTTL 2 LVTTL 3 LVTTL 54 Type Pin No. LVTTL 6 LVTTL 9 LVTTL 8 LVTTL 7 LVTTL 5 Type Pin No. 公 司 ， 18 66 Direction 43 41 5 Digital Audio Input Pins Pin Name LVTTL 44 Data enable 71 Input ： DE 60-64 限 Programming Pins Direction Description INT# Output Interrupt output. Default active-low (5V-tolerant) LVTTL 13 SYSRSTN Input Hardware reset pin. Active LOW (5V-tolerant) Schmitt 33 I C Clock for DDC (5V-tolerant) Schmitt 16 I2C Data for DDC (5V-tolerant) Schmitt 15 讯 科 技 有 Pin Name 2 I/O DDCSDA I/O PCSCL Input Serial Programming Clock for chip programming (5V-tolerant) Schmitt 34 I/O Serial Programming Data for chip programming (5V-tolerant) Schmitt 35 Input Serial programming device address select LVTTL 32 Input Hot Plug Detection (5V-tolerant) LVTTL 14 Input Must be tied low via a resistor. LVTTL 17 市 金 深 HPD 圳 PCSDA PCADR 合 DDCSCL ENTEST www.ite.com.tw Aug-2009 Rev:1.2 5/27 IT6610 HDMI front-end interface pins Pin No. HDMI Channel 2 positive output TMDS 31 TX2M Analog HDMI Channel 2 negative output TMDS 30 TX1P Analog HDMI Channel 1 positive output TMDS 28 TX1M Analog HDMI Channel 1 negative output TMDS 27 TX0P Analog HDMI Channel 0 positive output TMDS 25 TX0M Analog HDMI Channel 0 negative output TMDS 24 TXCP Analog HDMI Clock Channel positive output TMDS 22 TXCM Analog HDMI Clock Channel negative output TMDS 21 REXT Analog External resistor for setting TMDS output level. Default tied to Analog 20 81 Analog 51 TX2P 9 Type 44 Description 71 Direction ： Pin Name 85 ， QQ AVCC via a 475-Ohm SMD resistor. Power/Ground Pins Description IVDD Digital logic power (1.8V) IVSS Digital logic ground OVDD I/O Pin power (3.3V) AVCC HDMI analog frontend power (3.3V) AGND HDMI analog frontend ground PVCC1 HDMI core PLL power (3.3V) PGND1 HDMI core PLL ground ， 司 Type Pin No. Power 4, 12, 36, 48 Ground 11 Power 10, 37,59 Power 23, 29 Ground 26 Power 19 Ground 18 深 圳 市 金 合 讯 科 技 有 限 公 18 66 43 41 5 Pin Name www.ite.com.tw Aug-2009 Rev:1.2 6/27 IT6610 Functional Description IT6610 provides complete solutions for HDMI Source systems by implementing all the required HDMI functions. In addition, advanced processing algorithms are employed to optimize the performance of video processing such as color space conversion and up/down sampling. The following picture is the functional block digram of IT6610, which describes clearly the data flow. HSYNC DE D[23:0] MCLK SCK Audio Data Capture WS I2S0 71 DDCSDA HDCP Cipher & Encryption Enginer TX2P/M TMDS Transmitter (DVI/HDMI) TX1P/M TX0P/M TXCP/M 司 ， SPDIF DDCSCL QQ Color Space Conversion 4:2:2 4:4:4 Pixel Repeat 85 ， Video Data Capture & DE Generator I2C Master (HDCP Controller) 43 41 5 PCLK VSYNC I2C Master (to HDCP EEPROM) 18 66 PCADR I2C Slave (to host) ： Configuration Register Blocks SYSRSTN 44 51 81 9 PCSCL PCSDA ROMSCL ROMSDA Interrupt Controller HPD 公 INT 技 有 限 Figure 2. Functional block diagram of IT6610 Video Data Processing Flow 市 金 合 讯 科 Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most of the block enablings and path bypassings are controlled through register programming. Please refer to IT6610 Programming Guide for detailed and precise descriptions. 深 圳 As can be seen from Figure 3, the first step of video data processing is to prepare the video data (Data), data enable signal (DE), video clock (Clock), horizontal sync and vertical sync signals (H/VSYNC). While the video data and video clock are always readily available from input pins, the preparation of the data enable and sync signals require special extraction process (Embedded Ctrl. Signals Extraction & DE Generator) depending on the format of input video data. All the data then undergo a series of video processing including YCbCr up/down-sampling, color-space conversion and dithering. Depending on the selected input and output video formats, different processing blocks are either enabled or bypassed via register control. For the sake of www.ite.com.tw Aug-2009 Rev:1.2 7/27 IT6610 flexibility, this is all done in software register programming. Therefore, extra care should be taken in keeping the selected input-output format combination and the corresponding video processing block selection. Please refer to the IT6610 Programming Guide for suggested register setting. PCLK Clock H/VSYNC DE Generator 51 H/VSYNC Data 71 DE ： Embedded Ctrl. Signals Extraction DE 44 H/VSYNC 81 9 DE YCbCr422 to YCbCr444 YCbCr (upsampler) (CSC) Dithering 12-to-8 YCbCr444 to YCbCr422 43 41 5 ٛ 85 ， QQ D[23:0] RGB TX2 TX1 TX0 TXC 18 66 (downsampler) HDCP TMDS Driver ， Figure 3. Video data processing flow of IT6610 技 有 限 公 司 Designated as D[23:0], the input video data could take on bus width of 8 bits to 24 bits. This input interface could be configured through register setting to provide various data formats as listed in Table 1. 市 金 合 讯 科 Although not explicitly depicted in Figure 3, input video clock (PCLK) can be configured to be multiplied by 0.5, 2 or 4, so as to support special formats such as CCIR-656 and pixel-repeating. This is also enabled by software programming. General description of block functions is as follows: 深 圳 Extraction of embedded control signals (Embedded Ctrl. Signals Extraction) Input video formats with only embedded sync signals rely on this block to derive the proper Hsync, Vsync and DE signals. Specifically, CCIR-656 video streams includes Start of Active Video (SAV) and End of Active Video (EAV) that this block uses to extract the required control signals. Generation of data enable signal (DE Generator) DE signal defines the region of active video data. In cases where the video decoders supply no such DE signals to IT6610, this block is used to generate appropriate DE signal from Hsync, Vsync and Clock. Upsampling (YCbCr422 to YCbCr444) www.ite.com.tw Aug-2009 Rev:1.2 8/27 IT6610 In cases where input signals are in YCbCr 4:2:2 format and output is selected as 4:4:4, this block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during upsampling. Bi-directional Color Space Conversion (YCbCr ↔ RGB) Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order to offer full compatibility between various Source and Sink combination, this block offers bi-directional 44 51 81 9 RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the maxtrix coefficients of the CSC engine in IT6610 are fully programmable. Users of IT6610 could elect to employ their preferred conversion formula. 85 ， QQ ： 71 Dithering (Dithering 12-to-8) All the video processings in IT6610 are done in 12 bits per channel in order to minimize rounding errors and other computational residuals that occur during processing. For outputing to the 8-bits-per-channel formats, decimation from 12 bits to 8 bits is required. This block performs the necessary dithering for decimation to prevent visible artifacts from appearing. 18 66 43 41 5 Downsampling (YCbCr444 to YCbCr422) In cases where input signals are in YCbCr 4:4:4 format and output is selected as YCbCr 4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid visible artifacts generated during downsampling. 限 公 司 ， HDCP engine (HDCP) The HDCP engine in IT6610 handles all the processing requried by HDCP mechanism in hardware. Software intervention is not necessary except checking for revocation. Preprogrammed HDCP keys are also embedded in IT6610. Users need not worry about the purchasing and management of the HDCP keys as Chip Advanced Technology will take care of them. 深 圳 市 金 合 讯 科 技 有 TMDS driver (TMDS Driver) The final stop of the data processing flow is TMDS serializer. The TMDS driver serializes the input parallel data and drive out the proper electrical signals to the HDMI cable. The output current level is controlled through connecting a precision resistor of proper value to Pin 20 (REXT). www.ite.com.tw Aug-2009 Rev:1.2 9/27 IT6610 Supported Input Video Formats Table 1 lists the input video formats supported by IT6610. Input Pixel clock frequency (MHz) Video Input Bus Hsync/ Space Format Chs Width Vsync RGB 4:4:4 3 24 1 720p 1080i SXGA Separate 13.5 27 65 74.25 74.25 108 148.5 12 Separate 13.5 27 65 74.25 74.25 108 148.5 3 24 Separate 13.5 27 65 74.25 74.25 108 148.5 1 12 Separate 13.5 27 65 74.25 74.25 108 148.5 2 16/20/24 Separate 13.5 27 65 74.25 74.25 108 148.5 162 Embedded 13.5 27 65 74.25 74.25 108 148.5 162 1 8/10/12 Separate 27 54 130 148.5 148.5 Embedded 27 54 130 148.5 148.5 81 44 71 ： QQ 4:2:2 1080p 9 XGA 85 ， YCbCr 480p 43 41 5 4:4:4 480i 51 Color UXGA 162 162 Table 1. Input video formats supported by IT6610 限 公 司 ， 18 66 Notes: 1. Table cells that are left blanks are those format combinations that are not supported by IT6610. 2. Input channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are arranged. Refer to Video Data Bus Mappings starting page 17 for better understanding. 3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY. 4. The original pixel clock of 480i is 13.5MHz. HDMI standard mandates that a 27MHz pixel clock be used and pixel repeating is employed to keep the frequency range of the HDMI link within control. 技 有 Audio Data Capture and Processing 市 金 合 讯 科 IT6610 takes in one I2S input as well as one S/PDIF input of audio data. The I2S input allows transmission of 2-channel uncompressed audio data at up to 192kHz sample rate. The S/PDIF input allows transmission of uncompressed PCM data (IEC 60958) or compressed multi-channel data (IEC 61937) at up to 192kHz. 深 圳 Note that MCLK input is optional for IT6610. By default IT6610 generates the MCLK internally to process the audio. Neither I2S nor S/PDIF inputs requires MCLK input, coherent or not. However, if the user prefers inputing MCLK from external audio source, such configuration could be enabled through register setting. Refer to IT6610 Programming Guide for such setting. Interrupt Generation The system micro-controller should take in the interrupt signal output by IT6610 at PIN 13 (INT). IT6610 generates an interrupt signal with events involving the following signals or situations: 1. Hot-plug detection (Pin 14, HPD) experiences state changes. www.ite.com.tw Aug-2009 Rev:1.2 10/27 IT6610 81 9 2. Receiver detection circuit reports the presence or absence of an active termination at the TMDS Clock Channel (Register 0Eh[5], RxSENDetect) 3. DDC bus is hanged for any reasons 4. Audio FIFO overflows 5. HDCP authentication fails 6. Video data is stable or not 85 ， QQ ： 71 44 51 A typical initialization of HDMI link should be based on interrupt signal and appropriate register probing. Recommended flow is detailed in IT6610 Programming Guide. Simply put, the microcontroller should monitor the HPD status first. Upon valid HPD event, move on to check RxSENDetect register to see if the receiver chip is ready for further handshaking. When RxSENDetect is asserted, start reading EDID data through DDC channels and carry on the rest of the handshaking subsequently. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 If the micro-controller makes no use of the interrupt signal as well as the above-mentioned status registers, the link establishment might fail. Please do follow the suggested initialization flow recommended in IT6610 Programming Guide. www.ite.com.tw Aug-2009 Rev:1.2 11/27 IT6610 Configuration and Function Control 81 9 IT6610 includes two serial programming ports by default (i.e. with embedded HDCP keys): one for interfacing with micro-controller, the other for accessing the DDC channels of HDMI link. If the customer elects to use IT6610 with external HDCP keys, there's an additional serial programming port for interfacing with the HDCP ROM. 71 44 51 The serial programming interface for interfacing the micro-controller is a slave interface, comprising PCSCL (Pin 34) and PCSDA (Pin 35). The micro-controller uses this interface to monitor all the statuses and control all the functions. Two device addresses are available, depending on the input ： logic level of PCADR (Pin 32). If PCADR is pulled high by the user, the device address is 0x9A. If 85 ， QQ pulled low, 0x98. The I2C interface for accessing the DDC channels of the HDMI link is a master interface, comprising 43 41 5 DDCSCL (Pin 16) and DDCSDA (Pin 15). IT6610 uses this interface to read the EDID data and perform HDCP authentication protocol with the sink device over the HDMI cable. 司 ， 18 66 For temporarily storing the acquired EDID data, IT6610 includes a 32 bytes dedicated FIFO. The micro-controller may command IT6610 to acquire 32 bytes of EDID information, read it back and then continue to read the next 32 bytes until getting all neccessary EDID informations. 合 讯 科 技 有 限 公 The HDCP protocol of IT6610 is completely implemented in hardware. No software intervention is needed except for revocation list checking. Various HDCP-related statuses are stored in HDCP registers for the reference of micro-controller. Refer to IT6610 Programming Guide for detailed register descriptions. The HDCP Standard also specifies a special message read protocol other than the standard I2C protocol. See Figure 4 for checking HDCP port link integrity. Slave Addr (7) 市 金 S R A Read Data (8) A Read Data (8) A Read Data (8) NA P 深 圳 S=Start; R=Read; A=Ack; NA=No Ack; P=Stop Figure 4. HDCP port link integrity message read All serial programming interfaces conform to standard I2C transactions and operate at up to 100kHz. www.ite.com.tw Aug-2009 Rev:1.2 12/27 IT6610 Electrical Specifications Absolute Maximum Ratings Unit -0.3 2.5 V I/O pins supply voltage -0.3 4.0 V AVCC HDMI analog frontend supply voltage -0.3 4.0 V PVCC1 HDMI core PLL supply voltage -0.3 VI Input voltage -0.3 VO Output voltage -0.3 TJ Junction Temperature TSTG Storage Temperature ESD_HB Human body mode ESD sensitivity -65 81 OVDD 51 Core logic supply voltage 9 Max 4.0 V OVDD+0.3 V OVDD+0.3 V 125 °C 150 °C 44 IVDD Typ 71 Min. ： Parameter QQ Symbol V 85 ， 2000 18 66 43 41 5 ESD_MM Machine mode ESD sensitivity 200 V Notes: 1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device. 2. Refer to Functional Operation Conditions for normal operation. Functional Operation Conditions Parameter IVDD Core logic supply voltage OVDD I/O pins supply voltage AVCC HDMI analog frontend supply voltage PVCC1 HDMI core PLL supply voltage VCCNOISE Supply noise TA Ambient temperature 讯 科 技 有 限 公 司 ， Symbol Min. Typ Max Unit 1.71 1.8 1.89 V 2.97 3.3 3.63 V 3.135 3.3 3.465 V 3.135 3.3 3.465 V 100 mVpp 70 °C 40 °C/W 0 25 深 圳 市 金 合 Junction to ambient thermal resistance Θja Notes: 1. AVCC and PVCC1 should be regulated. 2. See System Design Consideration at page 24 for supply decoupling and regulation. www.ite.com.tw Aug-2009 Rev:1.2 13/27 IT6610 Operation Supply Current Specification Max 22.5 Unit mA HDMI-2 46.1 48.6 mA HDMI-3 80.9 86.0 mA HDMI-1 0.16 0.45 mA HDMI-2 0.10 0.47 mA HDMI-3 0.06 HDMI-1 8.6 HDMI-2 HDMI-3 AVCC current under normal operation PVCC1 current under normal operation 15.0 17.0 mA 26.0 29.0 mA 1.7 1.9 mA 4.3 4.6 mA HDMI-3 8.8 9.4 mA HDMI-1 72 87 mW HDMI-2 147 176 mW HDMI-3 261 310 mW HDMI-1 Total power consumption under normal operation3 43 41 5 85 ， HDMI-2 PWTOTAL_OP mA mA QQ IPVCC1_OP 0.49 9.5 ： IAVCC_OP 81 OVDD current under normal operation 9 Typ 21.0 51 IOVDD_OP Conditions HDMI-1 44 Parameter IVDD current under normal operation 71 Symbol IIVDD_OP 技 有 限 公 司 ， 18 66 Notes: 1. Typ: OVDD=AVCC=PVCC1= 3.3V, IVDD=1.8V Max: OVDD=AVCC=PVCC1= 3.6V, IVDD=1.98V 2. HDMI-1: 480p with 2-channel audio, PCLK=27MHz HDMI-2: 720p/1080i with 2-channel audio, PCLK=74.25MHz HDMI-3: 1080p with 2-channel audio, PCLK=148.5MHz 3. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items. Power Down/Standby Power Consumption 0.003 mA 0.003 mA 4.7404 mA 市 金 合 PVCC1 ( 3.3V ) IVDD ( 1.8V) Unit 讯 科 AVCC ( 3.3V ) Power Down Quiescent Current 深 圳 Notes: 1. Total Power Down / Standby Power Consumption is 8.5mW www.ite.com.tw Aug-2009 Rev:1.2 14/27 IT6610 DC Electrical Specification VIL Input low voltage1 LVTTL VT Switching threshold1 LVTTL VT- Schmitt trigger negative going threshold Schmitt Conditions Min. 2.0 Typ 0.8 V 1.1 V 51 Schmitt trigger positive going threshold 1.6 2.0 V 44 Schmitt 1 1 IIN Input leakage current IOZ Tri-state output leakage current1 Serial programming output sink current Vswing TMDS output single-ended swing3 LVTTL IOH=-2~-16mA all VIN=5.5V or 0 all VIN=5.5V or 0 Schmitt VOUT=0.2V TMDS 0.4 2.4 ±5 μA ±10 μA 4 16 mA 400 600 mA VLOAD VLOAD+ V -10mV 10mV 43 41 5 IOL 2 IOL=2~16mA ： Output high voltage LVTTL QQ 1 85 ， Output low voltage1 71 voltage VOH 0.8 V voltage VOL Unit V 1.5 1 VT+ Max 9 Pin Type LVTTL 81 Under functional operation conditions Symbol Parameter VIH Input high voltage1 RLOAD=50Ω 18 66 VLOAD=3.3V 3 TMDS ， VOHTMDS TMDS output high voltage REXT=475Ω 圳 市 金 合 讯 科 技 有 限 公 司 IOFF Single-ended standby output current3 TMDS VOUT=0 10 μA Notes: 1. Guaranteed by I/O design. 2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design under the condition of driving the output pin with 0.2V. In a real serial programming environment, multiple devices and pull-up resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that specified by the I2C Standard. When set at maximum current, the serial programming output ports of IT6610 are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher than default. Refer to IT6610 Programming Guide for proper register setting. 3. Limits defined by HDMI 1.2 standard 深 Audio AC Timing Specification Under functional operation conditions Symbol Parameter FS_I2S I2S sample rate FS_SPDIF S/PDIF sample rate www.ite.com.tw Conditions Up to 2 channels Min. 32 2 channels 32 Typ Max 192 Unit kHz 192 kHz Aug-2009 Rev:1.2 15/27 IT6610 Video AC Timing Specification FCDE PCLK dual-edged clock frequency TPDUTY PCLK clock duty cycle TPJ PCLK worst-case jitter 3 TS Video data setup time TH Video data hold time 3 TSDE Video data setup time3 165 MHz 13.47 40 ns 25 74.25 MHz 40% 60% Single-edged 1.5 clocking 0.7 Dual-edged clocking 2.0 1.5 ns ns ns ns QQ 3 25 9 Dual-edged clocking 2 Unit ns 81 PCLK dual-edged clock period2 Max 40 51 TCDE clocking Typ 44 PCLK pixel clock frequency1 Min. 6.06 71 Fpixel Conditions Single-edged ： Under functional operation conditions Symbol Parameter Tpixel PCLK pixel clock period1 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， THDE Video data hold time 0.7 ns Notes: 1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding pixel frequencies. 2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i. 3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user through register programming. www.ite.com.tw Aug-2009 Rev:1.2 16/27 IT6610 Video Data Bus Mappings IT6610 supports various input data mappings and formats, including those with embedded control signals only. Corresponding register setting is mandatory for any chosen input data mappings. Refer to IT6610 Programming Guide for detailed instruction. Clocking 3 24 Seperate 1X 1 12 Seperate Dual-edged 8 3 24 Seperate 1X 3 1 12 Seperate Dual-edged 8 2 16/20/24 1X 4 Embedded 1X 5 1 8/10/12 Seperate 2X 7 Embedded 2X 6 YCbCr 43 41 5 4:2:2 Seperate 81 51 44 4:4:4 Table 9 H/Vsync 71 4:4:4 Bus Width ： RGB Input Channels QQ Video Format 85 ， Color Space 3 Table 2. Input video format supported by IT6610 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 With certain input formats, not all 24 data input pins are used. In that case, it is recommended to tie the unused input pins to ground. www.ite.com.tw Aug-2009 Rev:1.2 17/27 IT6610 RGB 4:4:4 and YCbCr 4:4:4, 24 Bits with Separate Syncs These are the simpliest formats, with a complete definition of every pixel in each clock period. Timing diagram is depicted in Fig. 5 in the example of RGB. The timing of YCbCr 4:4:4 follow suits. 43 41 5 85 ， QQ ： 71 44 51 81 9 YCbCr Cb0 Cb1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Cr0 Cr1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 HSYNC VSYNC DE 18 66 RGB B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 HSYNC VSYNC DE ， 司 技 有 限 公 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 讯 科 Table 3. RGB & YCbCr 4:4:4 Mappings 合 blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... blank val Rpix0 Rpix1 Rpix2 Rpix3 Rpix4 Rpix5 Rpix6 .... val val val D[15:8] val Gpix0 Gpix1 Gpix2 Gpix3 Gpix4 Gpix5 Gpix6 .... val val val val Bpix0 Bpix1 Bpix2 Bpix3 Bpix4 Bpix5 Bpix6 .... val val val 深 圳 市 金 D[23:16] D[7:0] PCLK DE H/VSYNC Figure 5. RGB 4:4:4 Timing Diagram www.ite.com.tw Aug-2009 Rev:1.2 18/27 IT6610 YCbCr 4:2:2 with Separate Syncs YCbCr 4:2:2 24-bit Pixel#2N Pixel#2N+1 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 HSYNC HSYNC VSYNC VSYNC DE DE 18 66 43 41 5 85 ， QQ ： 71 44 51 YCbCr 4:2:2 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cb8 Cb9 Cb9 HSYNC HSYNC VSYNC VSYNC DE DE ， 司 公 限 技 有 讯 科 合 圳 市 金 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE YCbCr 4:2:2 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 HSYNC HSYNC VSYNC VSYNC DE DE 81 9 YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is given for every pixel, while the two chroma channels are given alternatively on every other clock period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each component could take on different lengths. The DE period should contain an even number of clock periods. Figure 6 gives a timing example of 16-bit YCbCr 4:2:2. The 20-bit and 24-bit versions are similar. Table 4. Mappings of YCbCr 4:2:2 with separate syncs blank Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 ... blank val Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] Cbpix6 [7:0] .... val val val D[15:8] val Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] Ypix6 [7:0] .... val val val 深 D[23:16] D[7:0] PCLK DE H/VSYNC Figure 6. 16-bit YCbCr 4:2:2 with separate syncs www.ite.com.tw Aug-2009 Rev:1.2 19/27 IT6610 YCbCr 4:2:2 with Embedded Syncs This is similar to the previous format. The only difference is that the syncs are embedded. Bus width could be 16-bit, 20-bit or 24-bit. Figure 7 gives a timing example of 16-bit YCbCr 4:2:2. The 20-bit and 24-bit versions are similar. 讯 科 技 有 限 公 ： 71 44 51 81 9 YCbCr 4:2:2 24-bit Pixel#2N Pixel#2N+1 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y10 Y10 Y11 Y11 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cr8 Cb9 Cr9 Cb10 Cr10 Cb11 Cr11 grounded grounded grounded grounded grounded grounded QQ 85 ， 43 41 5 18 66 司 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE YCbCr 4:2:2 20-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded Y0 Y0 Y1 Y1 grounded grounded grounded grounded Cb0 Cr0 Cb1 Cr1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 Cb8 Cb8 Cb9 Cb9 grounded grounded grounded grounded grounded grounded ， YCbCr 4:2:2 16-bit Pixel#2N Pixel#2N+1 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4 Cb5 Cr5 Cb6 Cr6 Cb7 Cr7 grounded grounded grounded grounded grounded grounded 市 金 合 Table 5. Mappings of YCbCr 4:2:2 with embedded syncs 圳 D[23:16] 深 D[15:8] SAV Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 ... blank val val val val Cbpix0 [7:0] Crpix0 [7:0] Cbpix2 [7:0] Crpix2 [7:0] Cbpix4 [7:0] Crpix4 [7:0] .... val FF 00 00 XY Ypix0 [7:0] Ypix1 [7:0] Ypix2 [7:0] Ypix3 [7:0] Ypix4 [7:0] Ypix5 [7:0] .... val D[7:0] PCLK DE H/VSYNC Figure 7. 16-bit YCbCr 4:2:2 with embedded syncs www.ite.com.tw Aug-2009 Rev:1.2 20/27 IT6610 CCIR-656 Format 合 圳 深 ： 71 44 CCIR-656 12-bit Pixel#2N Pixel#2N+1 C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y9 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded QQ 18 66 43 41 5 85 ， CCIR-656 10-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded ， 讯 科 技 有 限 公 司 CCIR-656 8-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded Table 6. Mappings of CCIR-656 市 金 Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 51 81 9 The CCIR-656 format is yet another variation of the YCbCr formats. The bus width is further reduced by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To compensate for the halving of data bus, PCLK is doubled. With the double-rate input clock, luminance channel (Y) and chroma channels (Cb or Cr) are alternated. IT6610 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at 148.5MHz. CCIR-656 format supports embedded syncs only. Figure 8 gives an example of 8-bit CCIR-656. 10-bit and 12-bit versions are similar. SAV Pixel0 Pixel1 Pixel2 ... blank D[23:16] D[15:8] FF 00 00 XY Cbpix0 [7:0] Ypix0 [7:0] Crpix0 [7:0] Ypix1 [7:0] Cbpix2 [7:0] Ypix2 [7:0] .... val D[7:0] PCLK DE H/VSYNC Figure 8. 8-bit CCIR-656 www.ite.com.tw Aug-2009 Rev:1.2 21/27 IT6610 CCIR-656 + separate syncs This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus separate syncs. ： 71 44 51 81 9 CCIR-656 12-bit Pixel#2N Pixel#2N+1 C0 Y0 C1 Y1 C2 Y2 C3 Y3 grounded grounded grounded grounded grounded grounded grounded grounded C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y9 C9 Y9 C10 Y10 C11 Y11 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE QQ 85 ， 43 41 5 18 66 司 公 限 技 有 CCIR-656 10-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded C0 Y0 C1 Y1 grounded grounded grounded grounded grounded grounded grounded grounded C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 C8 Y8 C9 Y9 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE ， CCIR-656 8-bit 1st PCLK 2nd PCLK grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded C0 Y0 C1 Y1 C2 Y2 C3 Y3 C4 Y4 C5 Y5 C6 Y6 C7 Y7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 市 金 合 讯 科 Table 7. Mappings of CCIR-656 + separate syncs blank Pixel0 Pixel1 Pixel2 ... blank D[23:16] 深 圳 D[15:8] val val val val Cbpix0 [7:0] Ypix0 [7:0] Crpix0 [7:0] Ypix1 [7:0] Cbpix2 [7:0] Ypix2 [7:0] .... val D[7:0] PCLK DE H/VSYNC Figure 9. 8-bit CCIR-656 + separate syncs www.ite.com.tw Aug-2009 Rev:1.2 22/27 IT6610 12-bit RGB and YCbCr 4:4:4 Using Dual-Edge Triggering 81 51 YCbCr 1st edge 2nd edge Cb0 Y4 Cb1 Y5 Cb2 Y6 Cb3 Y7 Cb4 Cr0 Cb5 Cr1 Cb6 Cr2 Cb7 Cr3 Y0 Cr4 Y1 Cr5 Y2 Cr6 Y3 Cr7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 RGB 1st edge 2nd edge B0 G4 B1 G5 B2 G6 B3 G7 B4 R0 B5 R1 B6 R2 B7 R3 G0 R4 G1 R5 G2 R6 G3 R7 grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded grounded HSYNC VSYNC DE Pin Name D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HSYNC VSYNC DE 9 This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus separate syncs. 讯 科 Table 8. Mappings of 12-bit 4:4:4 dual-edge triggered 合 blank Pixel0 Pixel1 Pixel2 ... blank D[11:8] val Gpix0 [3:0] Rpix0 [7:4] Gpix1 [3:0] Rpix1 [7:4] Gpix2 [3:0] Rpix2 [7:4] .... val val val val D[7:4] val Bpix0 [7:4] Rpix0 [3:0] Bpix1 [7:4] Rpix1 [3:0] Bpix2 [7:4] Rpix2 [3:0] .... val val val val D[3:0] val Bpix0 [3:0] Gpix0 [7:4] Bpix1 [3:0] Gpix1 [7:4] Bpix2 [3:0] Gpix2 [7:4] .... val val val val 深 圳 市 金 D[23:12] PCLK DE H/VSYNC Figure 10. 12-bit RGB 4:4:4 dual-edge triggered www.ite.com.tw Aug-2009 Rev:1.2 23/27 IT6610 System Design Consideration To get the optimum performance of IT6610, the system designers should follow the guideline below when designing the application circuits and PCB layout. 44 51 81 9 1. Pin 19 (PVCC1) should be supplied with clean power: ferrite-decoupled and capacitively- bypassed, since this is the power for the transmitter PLL, which is crucial in determining the TMDS output signal quality . Excess power noise might degrade the system performance. 85 ， QQ ： 71 2. The characteristic impedance of all differential PCB traces (TX2P/M, TX1P/M, TX0P/M, TXCP/M) should be kept 100Ω all the way from the HDMI connector to IT6610. This is very crucial to the system performance at high speeds. When layouting these 4 differential transmission lines (8 single-ended lines in total), the following guidelines should be followed: A. The signals traces should be on the outside layers (e.g. TOP layer) while beneath it there should 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 be a continuous ground plane in order to maintain the called micro-strip structure, giving stable and well-defined characteristic impedances. B. Cornering, through holes, crossing and any irregular signal routing should be avoided so as to prevent from disrupting the EM field and creating discontinuity in characteristic impedance. C. IT6610 should be placed as close to the HDMI connector as possible. Since the TMDS signal pins of IT6610 perfectly match the order of the connector pins, it is very convenient to route the signal directly into the chip, without through holes or angling. D. Carefully choose the width and spacing of the differential transmission lines as their characteristic impedance depends on various parameters of the PCB: trace width, trace spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM simulation is the best way to derive a correct dimension that enables a nominal 100Ω differential impedance. Please contact us directly for technical support of this issue. 深 圳 市 金 3. Special care should be taken when adding discrete ESD devices to all differential PCB traces (TX2P/M, TX1P/M, TX0P/M, TXCP/M). IT6610 is designed to provide ESD protection for up to 2kV at these pins. Adding discrete ESD diodes could enhance the ESD capability, but at the same time will inevitably add capacitive loads, therefore degrade the electrical performance at high speeds. If not chosen carefully, these diodes coupled with less-than-optimal layout could prevent the system from passing the SOURCE TMDS Data Eye Diagram test in the HDMI Compliance Test (Test ID 7-10). Besides, most general-purpose ESD diodes are relatively large in size, forcing the high-speed differential lines to corner several times and therefore introducing severe reflection. Carefully choosing an ESD diode that's designed for HDMI signalling could lead to a minimum loading as well as an optimized layout. Commercially available devices such as Semtech's RClamp0524p that take into consideration of all aspects are recommended. www.ite.com.tw Aug-2009 Rev:1.2 24/27 IT6610 (http://www.semtech.com/products/product-detail.jsp?navId=H0,C2,C222,P3028). An layout example is shown in Fig. 11, with referenced FR4 PCB structure included. Note that the ESD diodes should be placed as close to the HDMI connectors as possible to yield the best ESD performances.. DATA2+ GND 51 36 DATA2- GND DATA1+ 44 35 81 RClamp0524p 37 9 100ohm differentially 34 GND 33 71 DATA1- 32 DATA0+ ： 31 GND 29 85 ， 28 QQ 30 27 RClamp0524p 26 43 41 5 25 24 23 EXAMPLE: 20 19 18 W S W 18 66 21 1.8mil er=4.3 8mil GND DATA0CLOCK+ GND CLOCKCEC reserved SCL SDA GND +5V HPD 100 ohm: W=9mil, S=11mil ， 1.4mil 公 司 Figure 11. PCB layout example for high-speed transmission lines with RClamp0524p 深 圳 市 金 合 讯 科 技 有 限 4. Pin 20 (REXT) should be connected to AVCC via a 476Ω/1% precision SMD resistor. This resistor is used to calibrate the TMDS output current level to the nominal value of 10mA. The resistor should be placed as close to IT6610 as possible. 5. On PCM board, ground plane is needed to connect the IT6610 exposed die attached pad. www.ite.com.tw Aug-2009 Rev:1.2 25/27 IT6610 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 Package Dimensions Figure 13. 64-pin QFN Package Dimensions www.ite.com.tw Aug-2009 Rev:1.2 26/27 IT6610 Recommended Reflow Condition ( Pb-Free Package ) 250 (℃ ) 4 Peak 245 ℃ 81 9 3 51 200℃ 44 5 1 71 Temperature 2 200 150℃ QQ ： 150 43 41 5 85 ， 60 to 180 sec. Pre Heating Zone 100 60-150 sec. Soldering Zone 18 66 50 6 ， 25℃ to peak 限 公 司 Heating Time 技 有 Limits for IR Reflow Profile Characteristics of Package Leads Characteristic Description 1 Peak Lead Temperature in Preheat Zone 讯 科 Characteristics # Time maintained above 217 ℃ 3 Average ramp-up Rate Max 3℃/ Sec. 4 Peak Reflow Temperature 245 +0/-5 ℃ 10-30 sec. 5 Cooling rate of lead Max. 6℃ / Sec. 6 Time 25℃ to peak temperature 8 minutes max. 深 圳 市 金 合 2 Comment Limits 150 ~ 200 ℃ 60 - 180 sec. Min.─60sec. , Max.─150 sec. ITE qualify 260℃,10sec. Reference standard : IPC/JEDEC J-STD-020B. www.ite.com.tw Aug-2009 Rev:1.2 27/27