a 3 V Dual-Loop 50 Mbps to 1.25 Gbps Laser Diode Driver ADN2848 FEATURES 50 Mbps to 1.25 Gbps Operation Single 3.3 V Operation Bias Current Range 2 mA to 100 mA Modulation Current Range 5 mA to 80 mA Monitor Photo Diode Current 50 A to 1200 A 50 mA Supply Current at 3.3 V Closed-Loop Control of Power and Extinction Ratio Full Current Parameter Monitoring Laser Fail and Laser Degrade Alarms Automatic Laser Shutdown, ALS Optional Clocked Data Supports FEC Rates 32-Lead (5 mm × 5 mm) LFCSP Package GENERAL DESCRIPTION The ADN2848 uses a unique control algorithm to control both the average power and extinction ratio of the laser diode, LD, after initial factory setup. External component count and PCB area are low as both power and extinction ratio control are fully integrated. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). APPLICATIONS SONET OC-1/3/12 SDH STM-0/1/4 Fibre Channel Gigabit Ethernet GND IMODN CLKSEL VCC VCC DEGRADE FAIL ALS IMPDMON IMMON IBMON FUNCTIONAL BLOCK DIAGRAM VCC MPD VCC LD IMODP IMPD DATAP DATAN IMOD CLKP CLKN CONTROL PSET IBIAS IBIAS ASET GND ERSET ADN2848 GND GND ERCAP GND PAVCAP LBWSET GND REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADN2848–SPECIFICATIONS Parameter LASER BIAS (BIAS) Output Current IBIAS Compliance Voltage IBIAS During ALS ALS Response Time CCBIAS Compliance Voltage MODULATION CURRENT (IMODP, IMODN) Output Current IMOD Compliance Voltage IMOD During ALS Rise Time2 Fall Time2 Random Jitter2 Pulsewidth Distortion2 MONITOR PD (MPD) Current Compliance Voltage (VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1 Typical values as specified at 25C.) Min Typ 2 1.2 1.2 5 1.5 80 80 1 15 50 Max Unit 100 VCC 0.1 5 VCC mA V mA s V 80 VCC 0.1 170 170 1.5 mA V mA ps ps ps ps 1200 1.65 A V Average Current pF A V Average Current POWER SET INPUT (PSET) Capacitance Monitor Photodiode Current into RPSET Resistor Voltage 50 1.1 1.2 80 1200 1.3 EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage 1.2 1.1 1.2 25 1.3 kΩ V 25 1.3 kΩ V % ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis 1.2 1.1 CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN, CLKP, CLKN)3 V p-p (Single-Ended, Peak-to-Peak) Input Impedance (Single-Ended) tSETUP4 (see Figure 1) tHOLD4 (see Figure 1) 1.2 5 0.22 2.25 100 s s 500 50 50 100 LOGIC INPUTS (ALS, LBWSET, CLKSEL) VIH VIL 2.4 ALARM OUTPUTS (Internal 30 kΩ Pull-Up) VOH VOL 2.4 IBMON, IMMON, IMPDMON IMMON Division Ratio IMPDMON Compliance Voltage 0 SUPPLY ICC5 VCC6 3.0 0.8 V V 0.8 V V VCC – 1.2 A/A A/A V 3.6 mA V 100 1 50 3.3 mV Ω ps ps Conditions/Comments IBIAS < 10% of nominal RMS IMOD = 40 mA Low Loop Bandwidth Selection LBWSET = GND LBWSET = VCC Data and Clock Inputs Are AC-Coupled IBIAS = IMOD = 0 NOTES 1 Temperature range is as follows: –40°C to +85°C. 2 Measured into a 25 Ω load using a 0-1 pattern at 622 Mbps. 3 When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin. 4 Guaranteed by design and characterization. Not production tested. 5 ICCMIN for power calculation on page 6 is the typical I CC given. 6 All VCC pins should be shorted together. Specifications subject to change without notice. –2– REV. 0 ADN2848 ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V Digital Inputs (ALS, LBWSET, CLKSEL) . . . . . . . . . –0.3 V to VCC + 0.3 V IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 1.2 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150°C 32-Lead LFCSP Package Power Dissipation2 . . . . . . . . . . . . . . . . (TJ max – TA)/θJA W θJA Thermal Impedance3 . . . . . . . . . . . . . . . . . . . . . 32°C/W Lead Temperature (Soldering for 10 sec) . . . . . . . . . . 300°C Temperature Range Model ADN2848ACP-32 –40°C to +85°C ADN2848ACP-32-RL –40°C to +85°C ADN2848ACP-32-RL7 –40°C to +85°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Power consumption formulae are provided on Page 6. 3 θJA is defined when device is soldered in a 4-layer board. 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP SETUP HOLD tS tH DATAP/DATAN CLKP Figure 1. Setup and Hold Time CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2848 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 Package Description –3– ADN2848 24 IBMON 23 IMMON 22 GND3 21 VCC3 20 ALS 19 FAIL 18 DEGRADE 17 CLKSEL PIN CONFIGURATION ADN2848 TOP VIEW 16 CLKN 15 CLKP 14 GND1 13 DATAP 12 DATAN 11 VCC1 10 PAVCAP 9 ERCAP LBWSET 1 ASET 2 ERSET 3 PSET 4 IMPD 5 IMPDMON 6 GND4 7 VCC4 8 VCC2 25 IMODN 26 GND2 27 IMODP 28 GND2 29 GND2 30 IBIAS 31 CCBIAS 32 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 LBWSET ASET ERSET PSET IMPD IMPDMON GND4 VCC4 ERCAP PAVCAP VCC1 DATAN DATAP GND1 CLKP CLKN CLKSEL DEGRADE FAIL ALS VCC3 GND3 IMMON IBMON VCC2 IMODN GND2 IMODP GND2 GND2 IBIAS CCBIAS Loop Bandwidth Select Alarm Threshold Set Pin Extinction Ratio Set Pin Average Optical Power Set Pin Monitor Photodiode Input Mirrored Current from Monitor Photodiode—Current Source Supply Ground Supply Voltage Extinction Ratio Loop Capacitor Average Power Loop Capacitor Supply Voltage Data Negative Differential Terminal Data Positive Differential Terminal Supply Ground Data Clock Positive Differential Terminal, Used if CLKSEL = VCC Data Clock Negative Differential Terminal, Used if CLKSEL = VCC Clock Select (Active = VCC), Used if Data Is Clocked into Chip DEGRADE Alarm Output FAIL Alarm Output Automatic Laser Shutdown Supply Voltage Supply Ground Modulation Current Mirror Output—Current Source Bias Current Mirror Output—Current Source Supply Voltage Modulation Current Negative Output, Connect via Matching Resistor to VCC Supply Ground Modulation Current Positive Output, Connect to Laser Diode Supply Ground Supply Ground Laser Diode Bias Current Output Extra Laser Diode Bias When AC-Coupled—Current Sink –4– REV. 0 ADN2848 Note that IERSET and IPSET will change from device to device; however, the control loops will determine the actual values. It is not required to know the exact values for LI or MPD optical coupling. GENERAL Laser diodes have current-in to light-out transfer functions as shown in Figure 2. Two key characteristics of this transfer function are the threshold current, ITH, and slope in the linear region beyond the threshold current, referred to as slope efficiency, LI. Loop Bandwidth Selection For continuous operation, the user should hardwire the LBWSET pin high and use 1 µF capacitors to set the actual loop bandwidth. These capacitors are placed between the PAVCAP and ERCAP pins and ground. It is important that these capacitors are low leakage multilayer ceramics with an insulation resistance greater than 100 GΩ or a time constant of 1,000 sec, whichever is less. OPTICAL POWER ER = P1 P0 P1 PAV = P1 + P0 2 P PAV LI = P I I Operation Mode P0 ITH CURRENT Continuous High 50 Mbps to 1.25 Gbps Optimized Low for 1.25 Gbps Figure 2. Laser Transfer Function Control A monitor photodiode, MPD, is required to control the LD. The MPD current is fed into the ADN2848 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser’s changing threshold current and light-to-current slope efficiency. Recommended ERCAP 1 µF 1 µF 47 nF 47 nF Alarms The ADN2848 is designed to allow interface compliance to ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two active high alarms, DEGRADE and FAIL. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will be raised at 90% of this level. Example: The ADN2848 uses closed-loop extinction ratio control to allow optimum setting of extinction ratio for every device. Thus SONET/SDH interface standards can be met over device variation, temperature, and laser aging. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation. This reduces research and development time and second sourcing issues caused by characterizing LDs. Average power and extinction ratio are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer RPSET is used to change the average power. The potentiometer RERSET is used to adjust the extinction ratio. Both PSET and ERSET are kept 1.2 V above GND. IFAIL = 50 mA so IDEGRADE = 45 mA I 50 mA I ASET = FAIL = = 500 A 100 100 1.2V 1.2 *RASET = = = 2.4 k I ASET 500 A For an initial setup, RPSET and RERSET potentiometers may be calculated using the following formulas. RERSET Recommended PAVCAP Setting LBSET low and using 47 nF capacitors results in a shorter loop time constant (a 10× reduction over using 1 µF capacitors and keeping LBWSET high). The ADN2848 uses automatic power control, APC, to maintain a constant average power over time and temperature. RPSET = LBWSET *The smallest valid value for R ASET is 1.2 kΩ, since this corresponds to the I BIAS maximum of 100 A. 1.2 V ( Ω) I AV The laser degrade alarm, DEGRADE, is provided to give a warning of imminent laser failure if the laser diode degrades further or environmental conditions continue to stress the LD, such as increasing temperature. 1.2V ( Ω) I MPD _ CW ER − 1 × × PAV PCW ER + 1 The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH compliant. This occurs when one of the following conditions arise: where: IAV is the average MPD current. PCW is the dc optical power specified on the laser data sheet. IMPD_CW is the MPD current at that specified PCW. PAV is the average power required. ER is the desired extinction ratio (ER = P1/P0). • The ASET threshold is reached. • The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system that ALS has been enabled. DEGRADE will be raised only when the bias current exceeds 90% of ASET current. REV. 0 –5– ADN2848 Monitor Currents CCBIAS IBMON, IMMON, and IMPDMON are current controlled current sources from VCC. They mirror the bias, modulation, and MPD current for increased monitoring functionality. An external resistor to GND gives a voltage proportional to the current monitored. When the laser is used in ac-coupled mode, the CCBIAS and the IBIAS pins should be tied together (see Figure 7). In dccoupled mode, CCBIAS should be tied to VCC. Automatic Laser Shutdown The ADN2848 ALS allows compliance to ITU-T-G958 (11/94), section 9.7. When ALS is logic high, both bias and modulation currents are turned off. Correct operation of ALS can be confirmed by the FAIL alarm being raised when ALS is asserted. Note that this is the only time that DEGRADE will be low while FAIL is high. If the monitoring function IMPDMON is not required, the IMPD pin must be grounded and the monitor photodiode output must be connected directly to the PSET pin. Data and Clock Inputs Data and clock inputs are ac-coupled (10 nF capacitors recommended) and terminated via a 100 Ω internal resistor between DATAP and DATAN and also between the CLKP and CLKN pins. There is a high impedance circuit to set the commonmode voltage, which is designed to allow for maximum input voltage headroom over temperature. It is necessary that ac coupling be used to eliminate the need for matching between common-mode voltages. Alarm Interfaces The FAIL and DEGRADE outputs have an internal 30 kΩ pullup resistor that is used to pull the digital high value to VCC. However, the alarm output may be overdriven with an external resistor allowing alarm interfacing to non-VCC levels. Non-VCC alarm output levels must be below the VCC used for the ADN2848. Power Consumption The ADN2848 die temperature must be kept below 125oC. The LFCSP package has an exposed paddle. The exposed paddle should be connected in such a manner that it is at the same potential as the ADN2848 ground pins. The θJA for the package is shown under the Absolute Maximum Ratings. Power consumption can be calculated using ADN2848 DATAP (TO FLIP-FLOPS) DATAN 50 50 VREG R ICC = ICCMIN + 0.3 IMOD R = 2.5k, DATA R = 3k, CLK P = VCC ICC + (IBIAS VBIAS_PIN) + IMOD (VMODP_PIN + VMODN_PIN)/2 400A TYP TDIE = TAMBIENT + θJA P Thus, the maximum combination of IBIAS + IMOD must be calculated. Where: Figure 3. AC Coupling of Data Inputs ICCMIN = 50 mA, the typical value of ICC provided on Page 2 with IBIAS = IMOD = 0 For input signals that exceed 500 mV p-p single-ended, it is necessary to insert an attenuation circuit as shown in Figure 4. R1 DATAP/CLKP TDIE = die temperature TAMBIENT = ambient temperature ADN2848 VBIAS_PIN = voltage at IBIAS pin VMODP_PIN = average voltage at IMODP pin RIN R3 R2 VMODN_PIN = average voltage at IMODN pin DATAN/CLKN Laser Disode Interfacing NOTE THAT RIN = 100 = THE DIFFERENTIAL INPUT IMPEDANCE OF THE ADN2848 Many laser diodes designed for 1.25 Gbps operation are packaged with an internal resistor to bring the effective impedance up to 25 Ω in order to minimize transmission line effects. In high current applications, the voltage drop across this resistor, combined with the laser diode forward voltage, makes direct connection between the laser and the driver impractical in a 3 V system. AC coupling the driver to the laser diode removes this headroom constraint. Figure 4. Attenuation Circuit –6– REV. 0 ADN2848 VCC Caution must be used when choosing component values for ac coupling to ensure that the time constant (L/R and RC, see Figure 7) are sufficiently long for the data rate and expected number of CIDs (consecutive identical digits). Failure to do this could lead to pattern dependent jitter and vertical eye closure. For designs with low series resistance, or where external components become impractical, the ADN2848 supports direct connection to the laser diode (see Figure 6). In this case, care must be taken to ensure that the voltage drop across the laser diode does not violate the minimum compliance voltage on the IMODP pin. VCC VCC IMPD ADN2848 IMODP ADN2850 IBIAS TX SDI RX SDO CLK CLK DAC1 PSET DAC2 ERSET The PSET and ERSET potentiometers may be replaced with a dual-digital potentiometer, the ADN2850 (see Figure 5). The ADN2850 provides an accurate digital control for the average optical power and extinction ratio and ensures excellent stability over temperature. IDTONE DATAP Optical Supervisor DATAN CS CS DATAP DATAN IDTONE Figure 5. Application Using the ADN2850 Dual 10-Bit Digital Potentiometer with Extremely Low Temperature Coefficient as an Optical Supervisor FAIL DEGRADE ALS 1k 1.5k 1.5k CLKSEL FAIL ALS VCC3 GND3 VCC2 VCC DEGRADE 25 IMMON 17 IBMON 24 IMODN VCC 16 CLKN CLKP CLKP * MPD LD 10nF CLKN 10nF GND2 GND1 IMODP DATAP 10nF * GND2 * DATAP ADN2848 * DATAN DATAN 10nF GND2 VCC1 1F IBIAS 10H PAVCAP CCBIAS VCC4 9 GND4 IMPDMON IMPD PSET ERSET ASET ERCAP LBWSET VCC 32 1 VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2848 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS. 8 ** ** 1.5k LD = LASER DIODE MPD = MONITOR PHOTODIODE 1F VCC 10nF 10nF 10nF 10nF 10F GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED. ** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED. Figure 6. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked REV. 0 –7– ADN2848 FAIL VCC DEGRADE ALS * 1k * * * * 1.5k 1.5k CLKSEL FAIL ALS VCC3 GND3 VCC2 VCC DEGRADE 25 IMMON * 17 IBMON 24 16 10nF CLKN IMODN CLKN CLKP CLKP 10nF MPD LD GND2 GND1 IMODP DATAP 10nF * GND2 * DATAP ADN2848 * * DATAN DATAN 10nF GND2 VCC1 IBIAS 10H CCBIAS VCC4 9 GND4 IMPDMON IMPD PSET ERSET ASET ERCAP LBWSET 32 1F PAVCAP 1 VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE ADN2848 AND THE LASER DIODE USED. CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF CAPACITORS IN PARALLEL WITH 10nF CAPACITORS. 8 ** ** 1.5k LD = LASER DIODE MPD = MONITOR PHOTODIODE 1F VCC 10nF 10nF 10nF 10nF 10F GND NOTES * DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED. ** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED. Figure 7. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked Figure 8. A 1.244 Mbps Optical Eye. Temperature at 25C. Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS 31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser. Figure 9. A 1.244 Mbps Optical Eye. Temperature at 85C. Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS 31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a DFB Laser. –8– REV. 0 ADN2848 OUTLINE DIMENSIONS 32-Lead Frame Chip Scale Package [LFCSP] (CP-32) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.60 MAX 25 24 PIN 1 INDICATOR 4.75 BSC SQ TOP VIEW 17 16 9 3.50 REF 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 1.00 0.90 0.80 SEATING PLANE 0.30 0.23 0.18 0.25 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 REV. 0 2.25 1.70 SQ 0.75 BOTTOM VIEW 0.50 0.40 0.30 12 MAX 32 1 0.50 BSC –9– 8 –10– –11– –12– PRINTED IN U.S.A. C02746–0–1/03(0)