a 10.709 Gbps Laser Diode Driver Chipset ADN2843 FEATURES Data Rates from 9.952 Gbps to 10.709 Gbps Typical Rise/Fall Time 25 ps/23 ps Bias Current Range 3 mA to 80 mA Modulation Current Range 5 mA to 80 mA Monitor Photodiode Current 50 A to 1200 A Closed-Loop Control of Both Average Optical Power and Extinction Ratio Laser Fail and Laser Degrade Alarms Automatic Laser Shutdown, ALS Dual MPD Functionality for Wavelength Control CML Data Inputs 50 Internal Data Terminations 3.3 V Single-Supply Operation Driver Supplied in Dice Format GENERAL DESCRIPTION The ADN2943 chipset consists of two components, the ADN2845 and the ADN2844. The ADN2845 is a 10.709 Gbps laser diode driver. The ADN2845 eliminates the need to ac couple since it can deliver 80 mA of modulation while dc coupled to the laser diode. It is intended to be copackaged with the laser to minimize bond lengths, which improves performance of the optical transmitter. For transmission line applications, contact HSN Application Group at [email protected]. The ADN2844 offers a unique control loop algorithm and provides dual loop control of both average power and extinction ratio. Programmable alarms are provided for laser fail (end of life) and laser degrade (impending fail). Both the ADN2844 and the ADN2845 are available as bare die. The ADN2844 is also available in 5 mm ¥ 5 mm 32-lead LFCSP. APPLICATIONS SONET OC-192, SDH STM-64 Supports 10.667 Gbps and 10.709 Gbps FEC Rates 10 Gb Ethernet IEEE802.3ae FAIL DEGRADE IBMON IMPDMON2 VCC IMMON VCC IMPDMON FUNCTIONAL BLOCK DIAGRAM VCC MPD VCC VCC LD ADN2843 ADN2844 ADN2845 IMPD IMODP IMODN IMPD2 GND MODE DATAP CONTROL GND IMOD_CTRL ALS DATAN D_IMOD PSET * IBIAS IBIAS_CTRL GND ERSET * GND ERCAP PAVCAP ASET ALS GND IDTONE GND GND *ADN2850 OR ADN2860 OPTICAL SUPERVISOR REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. V to 3.6 V, All specifications T at 25C.) ADN2843–SPECIFICATIONS (Vvalues= 3.0as specified CC Parameter LASER BIAS (BIAS) Output Current IBIAS Compliance Voltage IBIAS during ALS ALS Shutdown Response Time MODULATION CURRENT (IMODP, IMODN) Output Current IMOD Compliance Voltage IMOD during ALS Rise Time Fall Time Random Jitter Total Jitter MIN Min Typ 3 1.2 to TMAX, unless otherwise noted. Typical Max Unit Conditions 80 VCC – 1.0 10 10 mA V A s See Note 1 80 VCC 10 mA V A ps ps fs rms ps p-p See Note 2 5 1.2 25 23 170 7.41 POWER SET INPUT (PSET) External Capacitance Voltage 1.15 80 1.35 pF V EXTINCTION RATIO SET INPUT (ERSET) Allowable Resistance Range Voltage 1.5 1.15 25 1.35 k V 1.2 1.15 13.2 1.35 5 k V % 0.22 s ALARM SET (ASET) Allowable Resistance Range Voltage Hysteresis CONTROL LOOP Time Constant DATA INPUTS (DATAP, DATAN) V p-p (Single-Ended Peak-to-Peak) Input Impedance (Single-Ended) 300 LOGIC INPUTS (ALS, MODE) VIH 2.4 800 mV 0.8 V 0.4 V 10 50 VCC – 2 1000 4000 kHz A V 50 1200 1.65 A V 2 VCC – 1.5 A/A A/A % V 50 2.4 V VOL IDTONE fIN Input Current Range Voltage on IDTONE MONITOR PD (MPD, MPD2) Current Input Voltage IBMON, IMMON, IMPDMON, IMPDMON2 IBMON, IMMON Division Ratio IMPDMON, IMPDMON2 IMPDMON to IMPDMON2 Matching Compliance Voltage SUPPLY VCC ICC (ADN2844) ICC (ADN2845) See Note 5 V VIL ALARM OUTPUTS (Internal 30 k to V CC) VOH See Note 3 See Note 4 100 1 0 3.0 3.3 75 3.6 36 V mA mA Measured at 1200 A See Note 6 See Note 6 NOTES 1 In ALS mode current is sourced to the laser from the I BIAS pin, which reverse biases the laser. 2 The ADN2845 high speed specifications are measured into a 5 load. 3 RMS jitter measured with a 0000 0000 1111 1111 repeating pattern at 10.7 Gbps rate. 4 Peak-to-peak total jitter measured with a 2 13 – 1 PRBS with 80 CIDs pattern at 10.7 Gbps rate. 5 Max capacitance refers to capacitance of photodiode and other parasitic capacitance. 6 IBIAS = 0, IMOD = 0 (when ALS is asserted). See Power Dissipation section on page 7 for calculation of complete power dissipation. Specifications subject to change without notice. –2– REV. 0 ADN2843 ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE (TA = 25°C, unless otherwise noted.) VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V Digital Inputs (ALS, MODE) . . . . . . . . –0.5 V to VCC + 0.3 V IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 1.2 V MOD_CONTROL to GND . . . . . . . . . . . . . . –0.5 V to 4.2 V IBIAS_CONTROL to GND . . . . . . . . . . . . . . –0.5 V to 4.2 V D_MOD to GND . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.2 V DATAP to GND . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.2 V DATAN to GND . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.2 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . . 150°C Temperature Range Model ADN2843CHIPSET Package Option –40°C to +85°C ADN2844 Control Loop: 32-Lead LFCSP ADN2845 Data Switch: Dice ADN2843CHIPSET-B –40°C to +85°C ADN2844 Control Loop: Dice ADN2845 Data Switch: Dice EVAL-ADN2843 Evaluation Board *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. GND GND DEGRADE FAIL ALS IMMON IBMON IDTONE ADN2844 METALLIZATION PHOTOGRAPH GND GND VCC GND IBIAS_CTRL GND GND MODE IMOD_CTRL PAVCAP D_IMOD ERCAP GND VCC GND IMPD2 IMPDMON2 IMPDMON IMPD GND PSET ERSET ASET GND 3000m CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADN2843 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– 2390m ADN2843 ADN2845 METALLIZATION PHOTOGRAPH VCC VCC VCC GND VCC (IMODN TERM) DATAN GND NC 1340m (20m) IMODP NC IBIAS GND NC DATAP ALS IMOD_CTRL IBIAS_CTRL GND 1140m (20m) GND IBIAS_CTRL VCC GND 29 28 27 26 25 GND IMOD_CTRL 30 VCC D_IMOD 31 VCC GND 32 VCC GND PIN CONFIGURATIONS 1 23 IBMON PSET 3 22 IMMON 21 ALS 20 FAIL 19 DEGRADE IMPDMON2 7 18 GND IMPD2 8 17 GND ADN2844 GND 4 BOND PAD SIZE: >115m BOND PAD PITCH: >104m DIE SIZE: 3000m 2390m IMPD 5 9 10 11 12 13 14 15 16 GND VCC ERCAP PAVCAP MODE GND GND GND IMPDMON 6 VCC (IMODN TERM) DATAN GND NC GND ADN2845 NC PAD PITCH: 200m MAXIMUM DIE SIZE: 1.16mm 1.36mm DIE THICKNESS: 0.25mm SINGLE PAD SIZE: 92m 92m DOUBLE PAD SIZE: 151m 92m DATAP –4– IMODP IBIAS NC GND ERSET 2 IBIAS_CTRL IDTONE IMOD_CTRL 24 ALS ASET 1 REV. 0 ADN2843 ADN2844 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14, 15, 17 18, 31, 32 16 19 20 21 22 23 24 25 26 27 28 29 30 ASET ERSET PSET GND IMPD IMPDMON IMPDMON2 IMPD2 GND VCC ERCAP PAVCAP MODE GND GND GND DEGRADE FAIL ALS IMMON IBMON IDTONE GND VCC IBIAS_CTRL GND IMOD_CTRL D_IMOD Alarm Current Threshold Set (Should be Terminated with a 1.2 k Resistor when Not Used) Extinction Ratio Current Set Average Optical Power Set Negative Supply Monitor Photodiode Current Input (Tie to GND when Not in Use) Mirrored Current from IMPD (Tie to VCC when Not in Use) Mirrored Current from IMPD2 (For Optional Use with Two MPDs, Tie to VCC when Not in Use) Optional Second MPD Current Input (Tie to GND when Not in Use) Negative Supply Positive Supply Extinction Ratio Loop Capacitor Average Power Loop Capacitor Control Loop Operating Mode Logic Input (Should Not Be Left Floating) Negative Supply Negative Supply Negative Supply DEGRADE Alarm Output, Open Collector, Active High FAIL Alarm Output, Open Collector, Active High Automatic Laser Shutdown Logic Input (Should Not Be Left Floating) Modulation Current Mirror Output, Current Source from VCC Bias Current Mirror Output, Current Source from VCC ID Tone Input Current (Tie to VCC when Not in Use) Negative Supply Positive Supply Control Output Current Sink Negative Supply Control Output Current Sink Control Output Current Sink ADN2845 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 2 3, 13 4 5 6 7 8 9 10 11 12 14 15 16–18 DATAN GND NC GND DATAP ALS IMOD_CTRL IBIAS_CTRL GND NC IBIAS IMODP VCC GND VCC AC-Coupled CML Data, Negative Differential Terminal Negative Supply No Connect, Leave Floating Negative Supply AC-Coupled CML Data, Positive Differential Terminal Automatic Laser Shutdown Logic Input Modulation Current Control Input (Control Circuit Sinks IMOD/10 from Pin to GND) BIAS Current Control Input (Control Circuit Sinks IBIAS/10 from Pin to GND) Negative Supply No Connect, Leave Floating BIAS Current Modulation Current VCC Connection for IMODN Termination Resistor Negative Supply Positive Supply REV. 0 –5– ADN2843 force the PSET and ERSET pins to 1.23 V above GND. For initial setup, RPSET and RERSET may be calculated using the following formulas: GENERAL Laser diodes have current-in to light-out transfer functions as shown in Figure 1. Two key characteristics of this transfer function are the threshold current, ITH, and slope in the linear region beyond the threshold current, referred to as the slope efficiency, LI. The PSET resistor is given by the following formulas: 1.23 V RPSET = (W ) I AV where IAV is average MPD current. ER = P1 P0 PAV = P1 + P0 2 OPTICAL POWER P1 The value of the ERSET resistor is a function of the operation mode of the ADN2843 as follows: P PAV LI = For Mode A: P I R ERSET = R PSET ¥ I ER + 1 ER – 1 For Mode B: P0 ITH R ERSET = CURRENT Figure 1. Laser Transfer Function Note that IERSET and IPSET will change from laser diode to laser diode, therefore RERSET and RPSET need to be adjusted for each laser diode. When tuning the laser diode, RPSET should be adjusted first with RERSET at 25 k. Once the average power is set, RERSET is adjusted to set the desired extinction ratio, and RPSET is again adjusted to re-establish the desired average power. Once the values RPSET and RERSET have been adjusted to set the desired average power and extinction ratio, the control loops maintain these values of average power and extinction ratio over environmental conditions and time. CONTROL A monitor photodiode, MPD, is required to control the LD. The MPD current is fed into the ADN2843 to control the power and extinction ratio, continuously adjusting the bias current and modulation current in response to the laser’s changing threshold current and light-to-current slope efficiency. The ADN2843 uses automatic power control, APC, to maintain a constant average power over time and temperature. The ADN2843 uses closed-loop extinction ratio control to allow optimum setting of the extinction ratio for every device. Thus, SONET/SDH interface standards can be met over device variation, temperature, and laser aging. Closed-loop modulation control eliminates the need to either overmodulate the LD or include external components for temperature compensation, thus reducing research and development time and second sourcing issues. PAVCAP AND ERCAP The control loop constants are set by the PAVCAP and ERCAP capacitors. The required value for the PAVCAP and ERCAP capacitors is 22 nF. The PAVCAP and ERCAP capacitors are connected between the respective pins and GND. The capacitors should be low leakage multilayer ceramic capacitors with an insulation resistance >100 G or an RC >1000 s, whichever is lowest. The ADN2843 dual-loop control has two modes of operation. Each mode is given by the configuration of the MODE and D_IMOD pins as shown below. Operation Mode MODE Pin Setting D_IMOD Pin Connected to A B HIGH LOW IBIAS IBIAS_CTRL R PSET ER + 1 ¥ 2 ER – 1 ALARMS The ADN2843 is designed to allow interface compliance to ITU-T-G958 (11/94), Section 10.3.1.1.2 (Transmitter Fail), and Section 10.3.1.1.3 (transmitter degrade). The ADN2843 has two alarms, DEGRADE and FAIL. These alarms are raised when IBIAS exceeds the respective DEGRADE and FAIL thresholds. These alarms are active high. A resistor between ground and the ASET pin is used to set the current at which these alarms are raised. The current through the ASET resistor is a ratio of 1:100 to the FAIL alarm threshold. The DEGRADE alarm will be raised at 90% of the FAIL threshold. Configuring the ADN2843 in Mode A or Mode B (see Figures 3 and 4) enables users to achieve accurate control of the extinction ratio. Mode B is suitable for applications where an IBIAS pin is not available to the TOSA, or where there is no space on the TOSA for an IBIAS inductor. Experimental data and simulation for typical lasers has shown ER to be 0.3 dB to 0.5 dB better in Mode A, at a 5 dB extinction ratio. Care should be taken to ensure that the extra capacitance on the IBIAS pin due to the D_IMOD connection does not degrade the eye quality. When physical constraints do not allow a low capacitance interconnect between D_IMOD and IBIAS, the ADN2843 should be configured in Mode B (see Figure 4). Example: I FAIL = 50 mA so I DEGRADE = 45 mA I FAIL 50 mA = = 500 A 100 100 1.23 V 1.23 V = = = 2.46 kW 500 A I ASET I ASET = R ASET Average power and extinction ratio for both modes are set using the PSET and ERSET pins, respectively. Potentiometers are connected between these pins and ground. The potentiometer RPSET is used to set the average power. The potentiometer RERSET is used to set the extinction ratio. The internal control loops The laser degrade alarm, DEGRADE, is provided to give a warning of imminent laser failure if the laser diode degrades further or if environmental conditions continue to stress the LD, such as increasing temperature. –6– REV. 0 ADN2843 The laser fail alarm, FAIL, is activated when the transmitter can no longer be guaranteed to be SONET/SDH compliant. This occurs when one of the following conditions arise: tor photodiode cathode should be connected directly to the PSET node, and IMPDMON and IMPDMON2 should be tied to VCC. MPD currents as high as 3 mA can be used in this configuration. ∑ The ASET threshold is reached. Another way to increase the MPD current range without sacrificing the monitoring function is to use IMPD and IMPD2 in parallel. This effectively doubles the current range but raises the lower MPD current specification from 50 A to 100 A. If this configuration is used, the IMPDMON and IMPDMON2 pins should be tied together and terminated with a single resistor. The mirror ratio of 1 is maintained in this configuration. ∑ The ALS pin is set high. This shuts off the modulation and bias currents to the LD, resulting in the MPD current dropping to zero. This gives closed-loop feedback to the system that ALS has been enabled. DEGRADE is raised only when the bias current exceeds 90% of the alarm threshold. DUAL MPD DWDM FUNCTION ALARM INTERFACE The MPD function mirrors the current in MPD to the PSET pin and to the IMPDMON pin with a ratio of 1. A second monitor photodiode can be connected to the IMPD2 pin. Its current is mirrored to IMPDMON2 and also to the PSET pin, where it is summed with the current mirrored from IMPD. The two MPD monitor currents can be used as inputs to a DWDM wavelength control function when used in combination with various optical filtering techniques. If the IMPD monitor function is not required, the monitor photodiode can be directly connected to the PSET pin, and the IMPD pin must be tied to GND. If the IMPD2 pin is not being used, it should be tied to GND. The alarm voltages are open collector outputs. An internal pull-up resistor of 30k that is used to pull the logic high value to VCC. However, this can be overdriven with an external resistor, allowing alarm interfacing to non-VCC levels. The FAIL output may not be connected directly to the ALS pin to shut down the bias and modulation currents. It can however be latched using a flip-flop, and the output of the flip-flop can then be used to activate ALS. Non-VCC alarm output levels must be below the VCC used for the ADN2843. DATA INPUTS Figure 2 shows a simplified schematic of the ADN2845 data inputs. The data inputs are terminated via the equivalent of a 100 internal resistor between DATAN and DATAP. This provides 50 termination for single-ended signals. The actual signal on the switching devices is attenuated by a factor of 2 internally. There is a high impedance circuit to set the commonmode voltage, which is designed to change over temperature. It is recommended that ac coupling be used to eliminate the need for matching between the common-mode voltages. DATAN IDTONE The IDTONE pin is supplied for fiber identification/supervisory channels or for control purposes. This pin modulates the optical one level by adding a current to IMOD over a possible range of 2% of minimum IMOD to 10% of maximum IMOD. The IDTONE current is set by an external current sink connected to the IDTONE pin. There is a gain of 2 between the IDTONE pin and the IMOD current. To ratio the IDTONE current to IMOD, the input current can be derived from the IMMON output current. If the IDTONE function is not being used, this pin must be tied to VCC to properly disable it. ADN2845 25 Note that using IDTONE during transmission may cause optical eye degradation. 25 2k INTERNAL REFERENCE AUTOMATIC LASER SHUTDOWN (ALS) 25 DATAP The ADN2843 ALS allows compliance to ITU-T-G958 (11/94), Section 9.7. When ALS is asserted, both bias and modulation currents are turned off. In ALS mode, current is sourced to the laser from the IBIAS pin, which reverse biases the laser and ensures that it is turned off. Correct operation of ALS can be confirmed by the FAIL alarm being raised when ALS is asserted. Note this is the only time that DEGRADE will be low while FAIL is high. 25 Figure 2. Simplified Schematic of Data Inputs MONITOR CURRENTS IBMON, IMMON mirror the bias, modulation current at a ratio of 1:100 for increased monitoring functionality. IMPDMON and IMPDMON2 mirror the current in IMPD and IMPD2, respectively, with a ratio of 1. All monitors source current from VCC. Note that for correct ALS operation, the ALS pin on the ADN2845 and ADN2844 should be connected and terminated with a 10 kW resistor. The ADN2843 ALS should be driven with correct logic levels (see Specifications section). ALS should never be left floating. If the MPD monitoring function is not required, then the IMPD pin should be tied to ground and the monitor photodiode cathode should be connected directly to the PSET pin. When the MPD monitor functions are not used, IMPDMON and IMPDMON2 should be tied to VCC. POWER DISSIPATION The power dissipation of the ADN2845 can be calculated using the following expressions: I CC = 75 mA + 1.75 ¥ I MOD (mA) + 0.3 ¥ I BIAS (mA) MPD CURRENT P = VCC ¥ I CC ( A) + VIMOD ¥ I MOD ( A) / 2 + VIBIAS ¥ I BIAS ( A) The maximum average MPD current is specified in the specifications section. This maximum current specified is limited by the MPD monitoring circuitry. If the monitoring function is not required, then IMPD and IMPD2 should be grounded, the moniREV. 0 where VIMOD is the average voltage on the IMOD pin, and VIBIAS is the average voltage on the IBIAS pin. –7– ADN2843 VCC VCC VCC VCC 100F TANTALUM 10nF 10nF VCC 18 15 GND VCC VCC 1 DATAN IMODNTERM 14 NC GND 10nF 5 DATAP VCC VCC 10nF NC ADN2845 IBIAS_CTRL GND IMOD_CTRL 10nF MPD IMODP IBIAS NC 10 9 GND ALS 6 VCC 10nF VCC IDTONE 24 ERSET IBMON PSET IMMON ** ADN2844 * GND ALS IMPD FAIL IMPDMON IMPDMON2 1k 1k 10k GND 9 GND GND GND 17 MODE VCC GND 8 IMPD2 ** DEGRADE PAVCAP ** VCC ERCAP 1k GND * GND VCC GND IBIAS_CTRL 1 ASET IMOD_CTRL D_IMOD GND 25 GND 32 16 10nF 22nF 22nF VCC VCC NOTES *FOR DIGITAL PROGRAMMING, THE ADN2850 OR ADN2860 OPTICAL SUPERVISOR CAN BE USED. **OPTIONAL MONITORING OF CURRENTS. Figure 3. ADN2843 Application Circuit (Mode A) • Best high frequency board layout techniques including power and ground planes should be used. • To minimize inductance, keep the connections between the ADN2845 and the laser diode as short as possible. Inductances <0.3 nH are recommended for best performance. Critical bonds are IMODP and VCC (Pin 14). Ribbon bonding can be used to reduce bond inductance. Minimize bond lengths for ADN2845 pads to achieve low inductance. • Place bypass capacitor on laser anode as close to laser as possible. • Bypass capacitors should be placed as close as possible to VCC pads. • 50 controlled impedance interconnects should be used on the DATA inputs. • Parasitic capacitance on IBIAS_CTRL and IMOD_CTRL interconnects should be less than 100 pF. If decoupling caps are used on IBIAS_CTRL and IMOD_CTRL, they should be tied to VCC rather than GND. • An inductor should be used in the bias current path. A Microwave Components coil 30-1847-GCCAS-01 (48 mil 24 mil) should be used. • The recommended substrate connection is to GND. However, the performance is not affected by connecting the substrate to VCC. –8– REV. 0 ADN2843 VCC VCC VCC VCC 100F TANTALUM 10nF 10nF VCC 18 15 GND VCC VCC VCC 10nF GND IBIAS_CTRL 5 DATAP IMOD_CTRL GND 10nF 10nF NC ADN2845 NC VCC IMODNTERM 14 1 DATAN MPD IMODP IBIAS GND 10 ALS 6 9 GND VCC 10nF VCC IDTONE 24 ERSET IBMON PSET * IMMON ** ADN2844 * GND ALS IMPD FAIL IMPDMON 1k GND VCC IBIAS_CTRL GND GND ASET IMOD_CTRL 1 D_IMOD 25 LBWSET 32 DEGRADE ** IMPDMON2 GND 9 GND GND GND GND 17 MODE PAVCAP VCC IMPD2 GND 8 ERCAP VCC 16 10nF 22nF 22nF VCC VCC NOTES *FOR DIGITAL PROGRAMMING, THE ADN2850 OR ADN2860 OPTICAL SUPERVISOR CAN BE USED. **OPTIONAL MONITORING OF CURRENTS. Figure 4. ADN2843 Application Circuit (Mode B) REV. 0 –9– ** 10k 1k 1k ADN2843 PARALLEL PLATE DECOUPLING CAPACITOR PARALLEL PLATE DECOUPLING CAPACITORS GROUND PLANE 18 VCC 1 MPD DATAN AGND 15 VCC VCC AGND VCC IMODNTERM BACK FACET LIGHT ADN2845 IMODP CERAMIC WITH GOLD SURFACE THAT CONTACTS THE LASER’S ANODE LASER LIGHT LASER IBIAS AGND 5 14 10 DATAP ALS IMOD_CTRL IBIAS_CTRL AGND 50 TRANSMISSION LINE 6 9 GROUND PLANE IBIAS OUTPUT INDUCTOR NOTES • FOR OPTIMUM PERFORMANCE, RIBBON BONDS ARE RECOMMENDED ON PADS 1, 5, 12, AND 14. WIRES ARE 3 MIL OR 5 MIL RIBBONS <400m • LONG. ALL OTHER PINS CAN BE ROUND WIRE <1mm. • LASER’S ANODE IS CONNECTED TO VCC THROUGH GOLD LAYER ON TOP OF CERAMIC STANDOFF. STANDOFF MINIMIZES LENGTH OF PAD • 12 AND PAD 14 RIBBONS. • PARALLEL PLATE DECOUPLING CAPACITORS SHOULD BE >100pF AND BE OF MICROWAVE AVX TYPE, PART NO. GB0159391KA6N (390pF). • THE RECOMMENDED SUBSTRATE CONNECTION IS TO GND. HOWEVER, PERFORMANCE IS NOT AFFECTED BY CONNECTING THE • SUBSTRATE TO VCC. • AN INDUCTOR SHOULD BE USED IN THE BIAS CURRENT PATH. A MICROWAVE COMPONENTS COIL 30-1847-GCCAS-01 (48 MIL 24 MIL) SHOULD BE USED. • THE EXTERNAL POWER SUPPLY IS CONNECTED AT THE PARALLEL PLATE DECOUPLING CAPACITOR. Figure 5. Recommended Layout Figure 6. 10 Gbps Optical Diagram Provided Courtesy of NEL. PAV = 0 dBm, ER = 5 dB, PRBS 31 Pattern. –10– REV. 0 ADN2843 DIE PAD COORDINATES (With Origin in the Center of the Die) ADN2845 ADN2844 Pad Number Pad Name X (m) Y (m) Pad Number Pad Name X (m) Y (m) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ASET ERSET PSET GND IMPD IMPDMON IMPDMON2 IMPD2 GND VCC ERCAP PAVCAP MODE GND GND GND GND GND DEGRADE FAIL ALS IMMON IBMON IDTONE GND VCC IBIAS_CNTRL GND IMOD_CTRL D_IMOD GND GND 1014.00 769.00 486.00 186.00 –132.00 –479.00 –811.00 –1056.00 –1339.00 –1339.00 –1339.00 –1339.00 –1339.00 –1339.00 –1339.00 –1339.00 –1051.00 –761.00 –476.00 –207.00 102.00 387.00 653.00 904.00 1359.00 1359.00 1359.00 1359.00 1359.00 1359.00 1359.00 1359.00 –1019.00 –1019.00 –1019.00 –1019.00 –1019.00 –1019.00 –1019.00 –1019.00 –877.00 –672.00 –429.00 –204.00 91.00 335.00 580.00 824.00 1019.00 1019.00 1019.00 1019.00 1019.00 1019.00 1019.00 1019.00 995.00 781.00 523.00 317.00 –29.00 –294.00 –562.00 –807.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 DATAN GND* NC GND* DATAP ALS IMOD_CTRL IBIAS_CTRL GND* NC* IBIAS IMODP* NC* VCC (IMODN)* GND* VCC* VCC* VCC* –500.00 –500.00 –500.00 –500.00 –500.00 –300.00 –100.00 100.00 300.00 500.00 500.00 500.00 500.00 500.00 300.00 100.00 –100.00 –300.00 400.00 222.00 0.00 –222.00 –400.00 –600.00 –600.00 –600.00 –600.00 –400.00 –200.00 –30.00 178.00 378.00 600.00 600.00 600.00 600.00 REV. 0 *Denotes –11– double bond pad. ADN2843 OUTLINE DIMENSIONS 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm 5 mm (CP-32) 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 12 MAX 32 1 0.50 BSC 4.75 BSC SQ 3.25 3.10 SQ 2.95 BOTTOM VIEW 0.50 0.40 0.30 1.00 0.90 0.80 PIN 1 INDICATOR 0.60 MAX 25 24 TOP VIEW C02764–0–4/03(0) Dimensions shown in millimeters 17 16 9 8 3.50 REF 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Exposed paddle should be soldered to the most negative supply of the ADN284 (ADN2844 also available as bare die) –12– REV. 0