深圳市美芯微电子有限公司 麦肯单片机授权一级代理商 电话：０７５５－３６８５７６０９／２７９４５５５１／２９４９１８８２ 地址：深圳市宝安区宝源路名优产品采购中心Ｂ１区７２１室 1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 2.0 K words of ROM, and 80 bytes of static RAM. 2. Features The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus On chip ROM size : 2 K words Internal RAM size : 80 bytes (72 general purpose, 8 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3 V ~ 5.5 V Addressing modes include direct, indirect and relative addressing modes Internal RC 4MHz frequency Power-on Reset (POR) MDT10P157 4 types of power edge-detector reset: 1.8v , 2.1v , always enable 1.8v and Disable Sleep mode for power saving 2 oscillator start-up time can be selected by programming option： 150 μs,20ms 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 20 I/O pins with their own independent direction control 20 I/O pins own independent weak pull-high and can be enabled by software. WDT can be enabled by software if WDT Disable is selected in user option. 3. Applications The application areas of this MDT10P157 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral … etc. This specification are subject to be changed without notice. Any latest information Please visit please preview http;//www.mdtic.com.tw http;//www.mx mcu.com.cn P.1 2010/06 Ver. 1.0 MDT10P157 4. Pin Assignment MDT10P157P11 MDT10P157S11 MDT10P157K11 RTCC 1 Vdd N/C Vss N/C PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 MDT10P157SS11 28 /MCLR 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS 1 N/C OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 RTCC VDD VDD PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 VSS 28 /MCLR 2 3 4 5 6 7 8 9 10 11 12 13 14 27 26 25 24 23 22 21 20 19 18 17 16 15 N/C OSC2 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 5. Order Information MARK MDT10P157P11 MDT10P157S11 MDT10P157SS11 MDT10P157K11 28 Timer (8 bit) 1 72 28 1 28-SOP 300 mil 72 72 28 28 1 1 28-SSOP 28-SKINNY 209 mil 300 mil ROM (Words) 2K RAM (Bytes) 72 2K 2K 2K I/O Package mil 28-DIP 600 mil 6. Pin Function Description Pin Name I/O Function Description PA0~PA3 I/O Port A, TTL input level PB0~PB7 I/O Port B, TTL input level PC0~PC7 I/O Port C, TTL input level RTCC I Real Time Clock/Counter, Schmitt Trigger input levels /MCLR I Master Clear, Schmitt Trigger input levels OSC2 O Clock out Vdd Power supply Vss Ground This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.2 2010/06 VER 1.0 MDT10P157 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 RTCC 02 PC 03 STATUS 04 MSR 05 Port A 06 Port B 07 Port C 08~0F Internal RAM, General Purpose Register 10~1F Internal Memory Select Register 30~3F Internal Memory Select Register 50~5F Internal Memory Select Register 70~7F Internal Memory Select Register Note : 00~0F, 20~2F, 40~4F, 60~6F are accessed to the same memory location. (1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK A10 A9 A8 A7~A0 Write PC, JUMP, CALL --- from b6-5 of STATUS LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.3 2010/06 VER 1.0 MDT10P157 (4) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 TF Time overflow Flag bit page Page select bit : 6—5 00 : 000H --- 1FFH 01 : 200H --- 3FFH 10 : 400H --- 5FFH 11 : 600H --- 7FFH 7 General purpose bit —— (5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F b7 b6 b5 b4 b3 b2 b1 b0 Read only, always read as “1” Indirect Addressing Mode (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) PORT C : R7 PC7~PC0, I/O Register This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.4 2010/06 VER 1.0 MDT10P157 (9) TMR (Time Mode Register) Bit Symbol 2—0 PS2—0 3 PSC 4 TCE 5 TCS 6 PHEN 7 WDTEN Function Prescaler Value RTCC rate WDT rate 1:2 0 0 0 1:1 1:4 0 0 1 1:2 1:8 0 1 0 1:4 1 : 16 0 1 1 1:8 1 0 0 1 : 16 1 : 32 1 0 1 1 : 64 1 : 32 1 1 0 1 : 128 1 : 64 1 1 1 1 : 256 1 : 128 Prescaler assignment bit : 0 — RTCC 1 — Watchdog Timer RTCC signal Edge : 0 — Increment on low-to-high transition on RTCC pin 1 — Increment on high-to-low transition on RTCC pin RTCC signal set : 0 — Internal instruction cycle clock 1 — Transition on RTCC pin Global Pull High Enable set : 0 — Enable weak internal Pull High 1 — Disable weak internal Pull High This bit will be ignored if the “I/O pull-hi” is disable in user option. Watchdog timer Enable set : 0 — Enable WDT 1 — Disable WDT (10) CPIO A, CPIO B, CPIO C (Control Port I/O Mode Register) The CPIO register is “write-only” ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode. (11) Set Pull hi mode The Pull hi register is “write-only” ＝“0”, Disable I/O pin Pull hi ＝“1”, Enable I/O pin Pull hi Do the CPIO instructions twice within three instructions on the same I/O port, then the second CPIO instruction will set the corresponding pull-hi of I/O pins to enable when global pull high Enable. Correct instruction sequence to enable pull-high Ex1: LDWI 0FFH CPIO 06H ←First：set PortB I/O LDWI 0FH ←Second This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.5 2010/06 VER 1.0 MDT10P157 CPIO 06H Ex2： LDWI 0FFH CPIO 06H CPIO 06H ←Third：enable Pull hi of PB3-0 ←First：set PortB I/O ←Second：Enable Pull hi of PB7-0 Incorrect instruction sequence to enable pull-high Ex1: (over three instructions) LDWI 0FFH CPIO 06H ←First：set PortB I/O LDWI 0FFH ←Second NOP ←Third CPIO 06H ←Fourth：set PortB I/O Ex2： LDWI CPIO CPIO (Different port) 0FFH 06H ←First：set PortB I/O 05H ←set PortA I/O (12) EPROM Option by writer programming : OST 150 us 20ms WDT Disable Enable Description Oscillator Start-up Time 150 us Oscillator Start-up Time 20 ms Description Watchdog timer disable all the time (can be enabled by software,if software WDT enable) Watchdog timer enable all the time (always enable) PED Disable Low level Mid level L(all on) Description PED disable 1.8V (disable during sleep) 2.1V (disable during sleep) always Enable 1.8V Security Disable Enable Security Disable Security Enable Description This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.6 2010/06 VER 1.0 MDT10P157 Software WDT Enable Disable Freq x 2 Enable Disable I/O pull-hi Enable Disable CLKOUT Enable Disable Reset on Err Enable Disable Description WDT can be enabled by software WDT can’t be enabled by software Description System clock is doubled (8MHz) System clock is 4MHz Description Allow software to enable independent I/O pin pull-high Disable all pull-high resistors Description Allow OSC2 to output CLKOUT signal OSC2 will be floating Description The MCU will be reset if two illegal instructions are executed continuously. Disable the illegal instruction reset function (13) Program Memory Address 000- 7FF 7FF Description Program memory The starting address of the power on, external reset or WDT This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.7 2010/06 VER 1.0 MDT10P157 8. Reset Condition for all Registers Register Address Power-On Reset /MCLR or WDT Reset CPIO A －－ 1111 1111 1111 1111 CPIO B －－ 1111 1111 1111 1111 CPIO C －－ 1111 1111 1111 1111 TMR －－ 1111 1111 1111 1111 IAR 00h － － RTCC 01h xxxx xxxx uuuu uuuu PC 02h 1111 1111 1111 1111 STATUS 03h 0001 1xxx 000# #uuu MSR 04h 100x xxxx 100u uuuu PORT A 05h - - - - xxxx - - - - uuuu PORT B 06h xxxx xxxx uuuu uuuu PORT C 07h xxxx xxxx uuuu uuuu Note : u = unchanged, x = unknown, - = unimplemented, read as “0” # = value depends on the condition of the following table Condition Status: bit 4 Status: bit 3 /MCLR reset (not during SLEEP) u u /MCLR reset during SLEEP 1 0 WDT reset (not during SLEEP) 0 1 WDT reset during SLEEP 0 0 This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.8 2010/06 VER 1.0 MDT10P157 9. Instruction Set Mnemonic Operands 010000 00000000 NOP No operation None 010000 00000001 CLRWT Clear Watchdog timer 0→WT TF, PF 010000 00000010 SLEEP Sleep mode 0→WT,stop OSC TF, PF 010000 00000011 TMODE Load W to TMODE register W→TMODE None 010000 00000100 RET Return Stack→PC None Control I/O port register W→CPIO Store W to register W→R Function Instruction Code R Operating 010000 00000rrr CPIO 010001 1rrrrrrr STWR 011000 trrrrrrr LDR R， t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R，t Swap halves register None 011001 trrrrrrr INCR R，t [R(0~3) ↔ R(4~7)]→t R + 1→t 011010 trrrrrrr INCRSZ R， R + 1→t None 011011 trrrrrrr ADDWR R，t Increment register，skip if zero Add W and register W + R→t 011100 trrrrrrr SUBWR R，t Subtract W from register 011101 trrrrrrr DECR R，t R ﹣W→t (R+/W+1→t) R ﹣1→t C，HC， Z C，HC， Z 011110 trrrrrrr DECRSZ R，t R Increment register Decrement register r Status None None Z Z R ﹣1→t None 010010 trrrrrrr Decrement register， skip if zero ANDWR R，t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI I AND W and immediate I ∩ W→W Z 010011 trrrrrrr IORWR R，t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI I Inclu. OR W and immediate I ∪ W→W Z 010100 trrrrrrr XORWR R，t Exclu. OR W and register 110110 iiiiiiii R ♁ W→t Z XORWI I Exclu. OR W and immediate I ♁ W→W Z 011111 trrrrrrr COMR R，t Complement register /R→t Z 010110 trrrrrrr RRR R，t Rotate right register C 010101 trrrrrrr RLR R，t Rotate left register 010000 1xxxxxxx CLRW Clear working register R(n)→R(n-1)， C→R(7) R(0)→C R(n)→(n+1)， C→R(0) R(7)→C 0→W 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R， b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R， b Bit set 1→R(b) None R C Z This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.9 2010/06 VER 1.0 MDT10P157 Instruction Code Mnemonic Function Operands 0001bb brrrrrrr BTSC R， b Bit Test，skip if clear Skip if R(b)=0 None 0011bb brrrrrrr Skip if R(b)=1 None n→PC， PC+1→Stack n→PC None n→PC, PC+1→Stack Stack→PC, i→W n→PC None Operating BTSS R， b Bit Test，skip if set 100nnn nnnnnnnn LCALL n Long CALL subroutine 101nnn nnnnnnnn LJUMP n Long JUMP to address 110000 nnnnnnnn CALL Call subroutine 110001 iiiiiiii n RTWI i 11001n nnnnnnnn JUMP n Return, place immediate to W JUMP to address Status None None None Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b t 0 1 R C HC Z / x i n : : : : : : : : : : : : Bit position Target Working register General register General register address Carry flag Half carry Zero flag Complement Don’t care Immediate data ( 8 bits ) Immediate address 10. Electrical Characteristics (A) Operating Voltage & Frequency Vdd ﹕2.3 V ~ 5.5 V Frequency﹕4M Hz (B) Input Voltage @ Vdd＝5.0 V, Temperature＝25 ℃ Vil Vih Port Min. Max. PA, PB, PC Vss 1.0 V RTCC, /MCLR Vss 1.0 V PA, PB, PC 2.0 V Vdd RTCC, /MCLR 3.3 V Vdd This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.10 2010/06 VER 1.0 MDT10P157 ＊Threshold Voltage : Port A, Port B, Port C Vth＝1.5 V RTCC, /MCLR Vil＝1.2 V, Vih＝3.1V (Schmitt Trigger) (C) Output Voltage @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : PA, PB, PC Port Ioh＝－20.0 mA Voh＝3.40 V Iol＝ Vol＝0.50 V 20.0 mA Ioh＝－5.0 mA Voh＝4.50 V Iol＝ mA Vol＝0.20 V 5.0 (D) Leakage Current @ Vdd＝5.0 V, Temperature＝25 ℃, the typical value as followings : Iil － 0.1μA (Max.) Iih ＋ 0.1 μA (Max.) (E) Sleep Current @WDT－Disable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd＜1.0 μA Vdd＝3.0 V Idd＜1.0 μA Vdd＝4.0 V Idd＜1.0 μA Vdd＝5.0 V Idd＜1.0 μA Vdd＝6.0 V Idd＜1.0 μA @WDT－Enable, Temperature＝25 ℃, the typical value as followings : Vdd＝2.3 V Idd＜1.0 μA Vdd＝3.0 V Idd＝1.2 μA Vdd＝4.0 V Idd＝3.0 μA Vdd＝5.0 V Idd＝5.0 μA Vdd＝6.0 V Idd＝10 μA This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.11 2010/06 VER 1.0 MDT10P157 F) Operating Current i.Internal RC 4MHz frequency Operating Temperature：-40°C<TA<80°C Freq Tolerance ±1 Typ 4.00 MHz ±2.5 4.00 MHz ±1.5 4.00 MHz conditions At VDD 4=V and Temperature=25°C 2.5V < VDD < 5.5V -40°C < TA < 80°C ii.OSC Type＝IRC4M；WDT－Enable；PED=Disable；Temperature＝25℃ Vdd Idd 5.5V 700 uA 5.0V 630 uA 4.0V 460 uA 3.0V 320 uA 2.5V 260 uA 2.3V 235 uA (G) Power Edge-detector Reset Voltage (Not in Sleep Mode), Vpr(Low level)≦1.6~1.8 V Vdd＝5.0 V (PED :Enable) Vpr ﹕Vdd (Power Supply) Vpr(Mid level)≦1.9~2.1 V PS. If PED_Enable then Internal Power_on_reset will be off This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.12 2010/06 VER 1.0 MDT10P157 (H) The basic WDT time-out cycle time Temperature＝25 ℃, the typical value as followings : Vdd =5.0 V, Temperature=25℃,the typical value as followings: Voltage (V) Basic WDT time-out cycle time (ms) 2.3 28.5 3.0 25.0 4.0 21.9 5.0 20.3 6.0 19.1 This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.13 2010/06 VER 1.0 MDT10P157 11. Port A ,Port B and Port C Equivalent Circuit Control Pull-high Pull high Resistor Working Register QB D Data I/P I/O Control Latch I/O Control Q CK Port I/O Pin D Data O/P Latch Write CK Q Data Bus D QB Read Data I/P Latch Input Resistor TTL Input Level CK This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.14 2010/06 VER 1.0 MDT10P157 12. MCLRB and RTCC Input Equivalent Circuit R≒1K MCLRB Schmitt Trigger R≒1K RTCC Schmitt Trigger This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.15 2010/06 VER 1.0 MDT10P157 13. Block Diagram Two Levels Stack RAM 72 x 8 EPROM 2048 x 14 Port A 11 bits Pull-high 11 bits Program Counter Port PA0~PA3 4 bits 14 bits Instruction Register Special Registers D0~D7 OSC2 MCLR Port B Port PB0~PB7 8 bits Pull-high Oscillator Circuit Instruction Decoder Control Circuit Data 8-bit Power on Reset PED Working Register ALU Status Register Port C Pull-high 8-bit Timer/Counter Prescaler WDT/OST Timer RTCC This specification are subject to be changed without notice. Any latest information please visit http;//www.mdtic.com.tw please preview http;//www.mx mcu.com.cn P.16 2010/06 VER 1.0 Port PC0~PC7 8 bits