PT4318 Low Power 315/433MHz OOK/ASK Super-heterodyne Receiver with SAW-Based Oscillator DESCRIPTION The PT4318 is a low power single chip OOK/ASK super-heterodyne receiver for the 315 MHz and 434 MHz frequency bands. It offers a high level integration and requires few external components. The PT4318 is composed of a low-noise amplifier (LNA), down-conversion mixer, SAW-based oscillator, auto-tuned on-chip gm-C intermediate frequency (IF) band-pass filter, IF limiting amplifier with received-signal-strength indicator (RSSI), automatic gain control (AGC) circuitry, and analog baseband data recovery circuitry (data filter, peak detector, and data slicer). The PT4318 is available in the 16-pin SSOP package and operate in a specific temperature range from –40 to +85°C. FEATURES Wide supply voltage range: 2.4 V to 5.5 V Supports 315 MHz / 434 MHz ISM bands Low current consumption: 5 mA typ. at 434 MHz SAW-based oscillator with low frequency drift Automatic gain control (AGC) function Auto-tuned on-chip channel select filter Supports data rates up to 10 Kb/s Requires few external components 16-pin SSOP package APPLICATIONS Remote Keyless Entry (RKE) systems Remote control systems Garage door openers Alarm systems Security systems Wireless sensors BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, No. 233-1, Baociao Rd., Sindian Dist., New Taipei City 23145,Taiwan PT4318 433.92 MHZ APPLICATION EXAMPLE U1 VDD5 1 CE OSCOUT 16 2 FDIV OSCIN 15 3 RFIN VSS 14 4 VSSLNA DATA 13 DSN 12 435.72MHz 2.2pF Etched Inductor on PCB 27nH 100nF PTC PT4318-X 5 NC 6 VREG PDOUT 11 7 DFFB OPP 10 VDD5 9 8 DSP 22nF 150pF VDD5 10W 470pF 100nF APPLICATION CIRCUIT U1 C8 R1 1 CE OSCOUT 16 2 FDIV OSCIN 15 3 RFIN VSS 14 4 VSSLNA DATA 13 5 NC DSN 12 6 VREG PDOUT 11 7 DFFB OPP 10 VDD5 9 X1 C1 L2 L1 C2 8 PTC PT4318-X DSP C7 C6 C5 VDD5 R2 C3 C4 Floating V 1.0 PIN # PIN NAME (pulled HIGH internally) Set“LOW” 2 FDIV For 433.92 MHz For 315 MHz 2 May 2016 PT4318 BILL OF MATERIALS Part Value Unit Description 315 MHz 433.92 MHz L1 47 n 27 n H Antenna input matching, coil inductor L2 82 n 56 n H Antenna ESD protection, coil inductor (optional) C1 1.8 p 2.2 p F Antenna input matching C2/C4 100 n 100 n F Power supply de-coupling capacitor C31 470 p 470 p F Data filter capacitor. C51 150 p 150 p F Data filter capacitor. C61 22 n 22 n F Data slicer threshold charge capacitor. C7/C82 — — F SAW oscillator frequency trimming capacitors. R1 10 K 10 K Ω MCU interface resistor (option). R2 10 10 X13 316.8 435.72 MHz SAW oscillator. U1 PT4318 IC PT4318 IC U1 Receiver chip. Power supply de-coupling resistor (optional) Notes: 1. The data filter and slicer are optimized for 2 Kb/s data rate in this application circuit. 2. The C7 and C8 are trimming capacitors for fine tuning the oscillation frequency of SAW oscillator. 3. X1 is the SAW resonator, and the frequency drift tolerance of ±75 KHz is acceptable. V 1.0 3 May 2016 PT4318 ORDER INFORMATION Valid Part Number PT4318-X Package Type 16 Pins, SSOP, 150 mil Top Code PT4318-X PIN CONFIGURATION CE 1 16 OSCOUT FDIV 2 15 OSCIN RFIN 3 14 VSS VSSLNA 4 13 DATA NC 5 12 DSN VREG 6 11 PDOUT DFFB 7 10 OPP DSP 8 9 VDD5 PT4302-X PT4318-X PIN DESCRIPTION V 1.0 Pin No. Pin Name I/O Description 1 2 3 4 5 6 CE FDIV RFIN VSSLNA NC VREG I I I G — I/O Chip enable RF frequency band select RF input Ground for low noise amplifier No connection Voltage regulator output 7 8 9 10 11 12 DFFB DSP VDD5 OPP PDOUT DSN I I/O P I O I/O Data filter feedback point Positive input of data slicer (data filter output) 5 V power supply voltage Non-inverting op-amp input Peak detector output Negative input of data slicer 13 14 15 16 DATA VSS OSCIN OSCOUT O G I O Data output Ground SAW oscillator input SAW oscillator output 4 May 2016 PT4318 FUNCTION DESCRIPTION POWER SUPPLY The PT4318 includes an internal voltage regulator to supply power to all receiver blocks. Only the VDD5 pin (pin 9) must be connected to the external supply voltage along with series resistor R2 and shunt capacitor C4 for filtering. Bypass capacitor C2 should be placed as close as possible to the voltage regulator output pin (pin 6) to reduce noise. The PT4318 chip supports operation over a wide supply voltage range from 2.4 V to 5.5 V. RF FRONT-END The RF front-end of the receiver part employs a super-heterodyne architecture that achieves good performance characteristics, including low noise figure, high voltage conversion gain, and excellent reverse isolation. The RF frontend down-converts the input radio-frequency (RF) signal into an intermediate frequency (IF) signal at 1.8 MHz. According to the block diagram, the RF front-end consists of an LNA, down-conversion mixer, and a surface acoustic wave (SAW) oscillator with a buffer amplifier to drive the mixer’s LO input. The output of the RF front-end is fed into the IF chain for channel-select filtering and demodulation. The RF down-converter does not include inherent suppression of the image frequency. Depending upon the particular application and the system's environmental conditions, a RF front-end filter may be added. If image rejection or good blocking immunity is a relevant system parameter, a band-pass filter must be placed in front of the LNA. This filter may be a SAW or LC-based filter (e.g. helix type). The RF input pin (pin 3) may be matched to 50 Ω with a shunt inductor L1 from the RF input pin to ground and a series capacitor C1 from the RF input to the antenna. An example of the input matching network is shown in Figure 1 and the input impedance of the PT4318 for 315 and 434 MHz frequency bands is listed in the right-hand side table. The component values given in the BOM for the application circuit shown on page 3 are nominal values only. Actual inductor and capacitor values may be different, depending upon the PCB material, PCB thickness, ground configuration, and length of PCB traces. C1 3 RF Frequency fRF RFIN Input Impedance (Pin 3) 315 MHz 3.2641 – j258.51 433.92 MHz 2.537 – j182.51 Table 1: Input Impedance for 315 / 434 Mhz bands RFIN L1 Figure 1: Input Matching Network Example ANTENNA PIN ESD PROTECTION The PT4318 IC provides the ESD protection level (Human Body Mode) better than 4 KV at the ANT pin. However, higher ESD protection level may still be required at the system level for some applications. Achieving an enhanced ESD protection level may need to rely on the appropriate selection of external components. Changing L1 from SMD type to coil type could enhance ESD protection level, and adding a shunt coil inductor L2 (or an etched PCB inductor) in front of C1 may help to further improve ESD protection. C1 3 Etched Inductor on PCB L2 RF Frequency fRF Suggestion value of L2 315 MHz 82 nH 433.92 MHz 56 nH Table 2: Suggested L2 Value ANT L1 Figure 2: Enhance ESD Protection V 1.0 5 May 2016 PT4318 AUTOMATIC GAIN CONTROL (AGC) The AGC circuitry monitors the RSSI voltage level. When the RSSI voltage exceeds a threshold reference value corresponding to an RF input level of approximately –72 dBm, the AGC switches on the LNA gain and then reduces the LNA gain by around 30 dB, thereby reducing the RSSI output by approximately 340 mV. The threshold reference voltage which is compared with the RSSI voltage to determine the gain state of the LNA is also reduced. The LNA resumes high-gain mode when the RSSI voltage drops below this lower threshold voltage corresponding to approximately –64 dBm RF input. The AGC incorporates an additional protection mechanism (delay timer of 2 16 × TREF seconds) to prevent immediate resetting of the LNA back to the high-gain state during reception of a “space” for OOK/ASK modulation. Figure 3 shows the change of RSSI voltage versus RF input power. When the RSSI level increases and then exceeds 1.8 V (RF input power rising), the AGC switches the LNA from high-gain mode to low-gain mode. As RSSI level decreases back to 1.35 V (RF input power falling), the AGC switches the LNA from low-gain mode back to high-gain mode. Figure 3: RSSI Response Parameter AGC Hysteresis Delay Time Condition RF input power changes from High to Low fRF = 315 MHz/433.92MHz 105 ms Table 3: AGC hysteresis delay times V 1.0 6 May 2016 PT4318 SAW OSCILLATOR The SAW oscillator is configured as a Pierce oscillator, but consists of a cascade of three amplifiers instead of a single amplifier. Although the circuit configuration is quite similar to the conventional Pierce oscillator, this configuration is capable of generating a much higher value of negative resistance. The SAW resonator is connected between pin 15 (OSCIN) and pin 16 (OSCOUT). The capacitors (C8 and C9) connected from pin 15 (OSCIN) and pin 16 (OSCOUT) to ground are used for adjusting the oscillation frequency. In general, these capacitors are unnecessary if frequency drift may be ignored. The SAW oscillator circuitry is shown in Figure 4, and an equivalent circuit of a SAW resonator is shown in Figure 5. The component values of the equivalent circuit are also listed below for reference. Figure 5: SAW Resonator Equivalent Circuit Figure 4: SAW oscillator circuitry Part Number SRA316D800A01-SD11 MFSRA435.72A01-SD11 Center Frequency (MHz) RS (Ω) LS (μH) 316.8 19 119.06 435.72 18 85.38 Table 4: component values of the equivalent circuit CS (pF) 0.00213 0.00156 CL (pF) 2.4 1.7 For down-converting the RF signal to the IF frequency, a suitable SAW oscillation frequency must be chosen. For the PT4318 chip, since the center frequency of the IF CSF is located at 1.8 MHz, the following equation may be used to calculate an appropriate SAW oscillator frequency: SAW Oscillator Freq. = TX Freq. ± 1.8 MHz V 1.0 7 May 2016 PT4318 IF CHANNEL SELECT FILTER (CSF) The PT4318 integrates a channel-select filter (CSF) with a bandwidth of approximately 450 KHz. The CSF is implemented as a 6th-order Chebyshev gm-C filter. An on-chip automatic frequency tuning circuit is also included and its absolute reference clock is derived from the SAW oscillator. The automatic frequency tuning circuit centers the passband of the CSF at the IF frequency (fIF) of 1.8MHz. LIMITER/RSSI The limiter is an AC coupled, successive approximation logarithmic amplifier with a cumulative gain of approximately 70 dB that has a band-pass characteristic centered near 1.8 MHz. The –3dB bandwidth of the limiter is around 2 MHz. The limiter circuit also produces an RSSI voltage that is directly proportional to the input signal level with a slope of approximately 10 mV/dB. This signal is used by the succeeding baseband circuitry to demodulate ASK-modulated receive signals. DATA FILTER The data filter is also implemented as a 2 nd-order low-pass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors (C3 and C5). Adjusting the value of the external capacitors changes the corner frequency and allows for optimization with different data rates. The corner frequency should be set to approximately 1.5 times the highest expected data rate from the transmitter. An ideal Sallen-Key filter is shown below. Figure 6: Ideal Sallen-Key Filter Utilizing the on-board voltage follower and the two 100 KΩ on-chip resistors, a 2nd-order Sallen-Key low pass data filter may be constructed by adding two external capacitors (C3 and C5) between pins 7 (DFFB) and 8 (DSP) and to pin 10 (OPP) as depicted in the Application Circuit. The following table shows the recommended values of the capacitors for different data rates. Data Rate C3 (pF) < 2Kb/s 1000 2Kb/s ~ 10Kb/s 470 10Kb/s ~ 20Kb/s 150 20Kb/s ~ 40Kb/s 56 > 40Kb/s (see Note) 15 Table 5: Values of the capacitors for different data rates C5 (pF) 270 150 56 15 4.7 Note: The maximum data rate supported by the PT4318 is 50 Kb/s. V 1.0 8 May 2016 PT4318 PEAK DETECTOR The peak detector generates a DC voltage which is proportional to the peak value of the received data signal. An external R-C network is required. The peak detector input is connected to the data filter output, which is connected to pin 8 (DSP), and its output signal may be used as a reference for the data slicer. The R-C time constant is calculated with the driving current of the data filter, 250 A. The following table shows the recommended values of the resistor R5 and capacitors C7 and C12 for different data rates. Data Rate R5 (Ω) C7 & C12 (F) 2 Kb/s 250 K 15 n 10 Kb/s 250 K 3n 20 Kb/s 250 K 1.5 n 40 Kb/s 250 K 680 p Table 6: Resistor R5 and capacitors C7 and C12 for different data rates Note: The maximum data rate supported by the PT4318 is 50 Kb/s. The circuit which utilizes the peak detector for faster start-up is depicted in the following figure. Figure 7: Utilizes the peak detector V 1.0 9 May 2016 PT4318 DATA SLICER The data slicer consists chiefly of a fast comparator, which allows for a maximum received data rate up to 50 Kb/s. The maximum achievable data rate also depends upon the IF filter bandwidth. Both data slicer inputs are accessible offchip to allow for easy adjustment of the slicing threshold. The output delivers a digital data signal (CMOS level) for subsequent circuits. The self-adjusting threshold on pin 12 (DSN) is generated by an R-C network or peak detector depending upon the baseband coding scheme. The suggested data slicer configuration uses an internal resistor Rin = 25 KΩ resistor connected between DSN and DSP with a capacitor from DSN to ground as shown in Figure 8. The cut-off frequency of the R-C integrator must be set lower than the lowest frequency appearing in the data signal to minimize distortion in the output signal. Figure 8: Suggested data slicer configuration V 1.0 10 May 2016 PT4318 DEMODULATION Using different circuit combinations, the PT4318 is capable of achieving three demodulation modes: “peak mode,” “squelch mode,” and “average mode.” PEAK MODE The peak detector circuit can contributes an instantaneous voltage jump on node DSN through capacitive voltage divider formed by C7 and C12. After the jump, the voltage on node DSN will decay to a steady–state value determined by the resistive divider formed by Rin and R5. By selecting the suitable value of R5, C7 and C12, the threshold voltage for comparison may be rapidly set through the help of the peak detector circuit (see the ”PEAK DETECTOR” section). SQUELCH MODE In the absence of an RF signal, the data filter outputs a DC voltage with a time-varying noise with a peak-to–peak voltage value of around 20 mV. The noise causes the non-inverting input voltage of the data slicer to swing back and forth across the DSN threshold voltage, resulting in random fluctuation of the comparator’s output between the supply voltage and ground. The squelch mode operation adds a threshold deviation (DC offset) on the DSN threshold that stops the effect. However, the receiving sensitivity will be sacrificed. The recommended value for the resistor R6 is 1.2 MΩwith an associated sensitivity loss of around 4 dB. The DC offset may be adjusted by changing the resistance of R6 and the VREG voltage. A larger DC offset will introduce more sensitivity loss. AVERAGE MODE When the “average mode” has been set according to the figure shown in the DATA SLICER section above, the DATA output will exhibit a toggling behavior similar to random noise. In this mode, better sensitivity may be achieved, but noise immunity is worse than in “peak mode.” V 1.0 11 May 2016 PT4318 SENSITIVITY AND SELECTIVITY In digital radio systems, sensitivity is often defined as the lowest signal level at the receiver input that will achieve a specified bit error rate (BER) at the output. The sensitivity of the PT4318 receiver is typically –108 dBm (ASK modulated with 2 Kb/s, 50% duty cycle square wave) to achieve a 0.1% BER when its input is matched for a 50 Ω signal source. The selectivity is governed by the response of the receiver front-end circuitry, the IF channel select filter (CSF), and the data filter. Note that the IF filter provides not only channel selectivity, but also the interference rejection. Within the pass band of the receiver, no rejection for interfering signals is provided POWER-DOWN CONTROL The chip enable (CE) pin controls the power on/off behavior of the PT4318. Connecting CE to HIGH sets the PT4318 to the normal operation mode; connecting CE to LOW sets the PT4318 to standby mode. The current consumption of the PT4318 is lower than 1 μA in standby mode. Once enabled, the PT4318 requires <5 ms to recover received data. A timing plot showing the response of the data output once the PT4318 is enabled is shown in Figure 9. Figure 9: Data output V 1.0 12 May 2016 PT4318 ANTENNA DESIGN For a λ/4 dipole antenna and operating frequency, f (in MHz), the required antenna length, L (in cm), may be calculated by using the formula 7132 L f For example, if the frequency is 315MHz, then the length of a λ/4 antenna is 22.6 cm. If the calculated antenna length is too long for the application, then it may be reduced to λ/8, λ/16, etc. without degrading the input return loss. However, the RF input matching circuit may need to be re-optimized. Note that in general, the shorter the antenna, the worse the receiver sensitivity and the shorter the detection distance. Usually, when designing a λ/4 dipole antenna, it is better to use a single conductive wire (diameter about 0.8mm to 1.6mm) rather than a multiple core wire. If the antenna is printed on the PCB, ensure there is neither any component nor ground plane underneath the antenna on the backside of PCB. For an FR4 PCB (εr=4.7) and a strip-width of 30mil, the length of the antenna, L (in cm), is calculated by c L where “c” is the speed of light (3 x1010 cm/s) 4 f r V 1.0 13 May 2016 PT4318 PCB LAYOUT CONSIDERATION Proper PCB layout is extremely critical in achieving good RF performance. At the very least, using a two-layer PCB is strongly recommended, so that one layer may incorporate a continuous ground plane. A large number of via holes should connect the ground plane areas between the top and bottom layers. Note that if the PCB design incorporates a printed loop antenna, there should be no ground plane beneath the antenna. Careful consideration must also be paid to the supply power and ground at the board level. The larger ground area plane should be placed as close as possible to the VSS and VSSLNA pins. To reduce supply bus noise coupling, the power supply trace should be incorporate series-R, shunt-C filtering as shown below. Power Supply VDD5 9 R 10 W C 100 n C’ 47 p Figure 10: Power supply noise reduction configuration If the power source is capable of supplying a stable voltage, C’ may be ignored. In some applications, the DC source may be supplied from a simple AC-DC transformer. In such cases, the DC voltage level could be unstable and may adversely affect ASK/OOK receiver sensitivity. A solution may be to increase C to an appropriately large value while continuing to make the power source as stable as possible. Finally, in an RF system, it is extremely important to keep the LNA or RF signal traces away from large voltage swing signals and digital data signal traces to avoid unnecessary interference. A representative layout of a PT4318 demoboard is shown on page 17. V 1.0 14 May 2016 PT4318 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Range Analog I/O Voltage Digital I/O Voltage Operating Temperature Range Storage Temperature Range Soldering Temperature Soldering Time Symbol Min. Max. Unit VDD5 – – Topr Tstg TSLD tSTG –0.3 –0.3 –0.3 –40 –40 6 3 6 +85 +125 V V V °C °C °C S 260 10 RECOMMENDED OPERATING CONDITIONS (VSS=0 V) Parameter Symbol Supply Voltage Range Operating Temperature VDD5 TA Min. Value Typ. Max. 2.4 –40 5.0 27 5.5 85 V °C Unit Unit PACKAGE THERMAL CHARACTERISTIC Parameter From Chip Conjunction Dissipation to External Environment From Chip Conjunction Dissipation to Package Surface V 1.0 Symbol Condition Rja Min. Typ. Max. – 37.15 – – 1 1.8 TA=27°C Rjc 15 °C/W May 2016 PT4318 ELECTRICAL CHARACTERISTICS Nominal conditions: VDD5=5.0 V, VSS=0 V, CE=HIGH, TA=+27 °C. Parameter General Characteristics Operating Frequency Range Supply Voltage Current Consumption Standby Current Maximum Receiver Input Level Sensitivity1 Symbol fRF VDD5 IDD5 ISTBY PRF,MAX SIN Conditions Min. Typ. Max. Unit FDIV = LOW FDIV = FLOATING Connect the supply voltage to VDD5 pin only CE = HIGH CE = LOW 300 400 315 433.92 330 460 MHz 2.4 5.0 5.5 V – – –20 5 – –10 – 1.0 – mA μA dBm 433.92MHz, ASKNote2, DRate=2Kb/s, Peak power level 433.92MHz, OOK, DRate=2Kb/s, Peak power level 315 MHz, ASKNote2, DRate=2Kb/s, Peak power level 315MHz, OOK, DRate=2Kb/s, Peak power level – -108 -105 – -102 -99 – -109 -106 – -103 -100 2 – – 50 –57 5 Kb/s dBm ms dBm dBm DRATE LLO TSTUP Measured at antenna input – – – GVRF NFRF Matched to 50 Ω Matched to 50 Ω 50 6 55 7 60 8 dB dB IF Center Frequency fIF fRF = 315 MHz fRF = 433.92 MHz Bandwidth RSSI Dynamic Range RSSI Slope SAW Oscillator Start-Up Time BW LIM DRRSSI SLRSSI – – – 60 9 1.8 1.8 450 70 10.5 – – – 80 12 MHz MHz kHz dB mV/dB TOSC,ST – – 500 μs Data Rate LO Leakage System Start-Up Time RF Front-End Conversion Voltage Gain Noise Figure IF Section Notes: 1. Packet Error Rate (PER) < 1e-2 with one byte packet of A5hex and data rate = 2Kb/s. 2. To use AM 99% with square wave modulation instead if there is no ASK feature in the signal generator. V 1.0 16 May 2016 PT4318 Figure 11: Supply Current vs. Supply Voltage Figure 12: Voltage Regulator Characteristic Figure 13: Selectivity Response for fRF = 434 MHz Figure 14: Current Consumption vs. Temperature Figure 15: Smith Chart Plot of RFIN Figure 16: Sensitivity vs. Temperature V 1.0 17 May 2016 PT4318 TEST BOARD LAYOUT <Top Side> <Bottom Side> V 1.0 18 May 2016 PT4318 PACKAGE INFORMATION L L 16 Pins, SSOP ,150mil Symbol Min. Nom. Max. A - - 1.750 A1 0.102 - 0.254 A2 1.245 - - b 0.203 - 0.305 c 0.102 - 0.254 D 4.90 BSC e 0.635 BSC E 6.00 BSC E1 3.91 BSC L1 0.406 - 1.270 θ 0º - 8º Notes: 1. Refer to JEDEC MO-137 AB 2. Unit: mm V 1.0 19 May 2016 PT4318 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian Dist., New Taipei City 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V 1.0 20 May 2016