SYNCMOS SM89T16R1L16

SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Product List
Feature
SM89T16R1L16, 16MHz 64KB internal flash MCU
SM89T16R1C25, 25MHz 64KB internal flash MCU
z
z
General Description
The SM89T16R1 is a high speed (4 clocks /
machine cycle) single-chip 8-bits microcontroller
manufactured in an advanced CMOS process with
on chip flash memory. It supports a derivative of
the 80C51 microcontroller family. The
SM89T16R1 has the same instructions set as the
80C51.
The SM89T16R1 contains a 64KB on chip program
flash, a volatile 1280 x 8 bits data RAM, four 8-bits
I/O ports, one 4-bits I/O port, two 16-bits
timer/event counters, and an additional 16-bits
timer coupled to capture and compare latches, a
two-priority-level, nested interrupt structure, two
pulse-width- modulation outputs, two UART and
two DPTR, an on-chip oscillator and timing circuit.
For system that requires extra capability the
SM89T16R1 can be expanded using standard TTL
compatible memory and logic.
In addition, The SM89T16R1 has two software
selectable modes of power saving – IDLE mode
and POWER-DOWN mode. The IDLE mode
freezes the CPU while allowing the RAM, timer,
serial ports, and interrupt system to continue
functioning. The POWER-DOWN mode saves the
RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
The Power Management Mode (PMM) is useful for
portable or battery-powered applications. This
feature allows software to select a lower speed
clock as the main time base.
z
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z
z
z
z
z
z
z
z
z
z
z
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Working Voltage: 3.3V or 5.0V.
80C51 Central Processor Unit (CPU),
High-Speed Architecture (4 clocks / machine
cycle), the maximum clock rate is 25 MHz.
64K x 8 on chip flash memory can be
programmed at VPP = 12V
1280 x 8 RAM (On-Chip 256 bytes and
Expand 1024 bytes), expandable externally to
64KB
Two standard 16-bits timers/counters
An additional 16-bits timer/counter coupled to
a capture and compare register.
Two 8-bits / 5-bits resolution
Pulse-Width-Modulation (PWM) outputs.
Four channels 6 bits Analog to Digital
Converter (ADC).
Four 8-bits I/O ports.(For PDIP package)
Four 8-bits I/O ports plus one 4-bits I/O port.
(For PLCC or PQFP package)
Two Full-duplex Enhance UART
Two DPTR (either data pointer can be
incremented and decrement).
13 interrupt sources (default 6 + int2, int3, int4,
int5, UART1, ADC, RTC) with 2 priority
levels.
RTC (Real Time Clock) function.
Extended temperature range (-40℃ to +85℃)
Software enable/disable ALE output pulse
Wake-up from POWER-DOWN mode by
external interrupt, RTCI or H/W Reset.
Ordering Information
SM89T16R1ihhkL
yymmv
Taiwan
6F, No.10-2 Li- Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {16,25}
k: package type postfix {as below table}
yy: year mm: month
v: version identifier { , A, B, ...}
TEL: 886-3-567-1820
886-3-567-1880
FAX: 886-3-567-1891
886-3-567-1894
L: PB Free identifier
{No text is Non-PB Free,”P” is PB Free}
Specifications subject to change without notice contact your sales representatives for the most recent information.
1
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Package Spec.
Package
44L PQFP
44L PLCC
40L PDIP
Pin / PAD
Figure 1
Figure 2
Figure 3
Frequency
16 MHz at 3.3V and 25MHz at 5V
16 MHz at 3.3V and 25MHz at 5V
16 MHz at 3.3V and 25MHz at 5V
Pin Configuration
AD0/P0.0 37
19 P2.1/A9
VDD 38
18 P2.0/A8
P4.2 39
17 P4.0
T2/P1.0 40
16 VSS
T2EX/P1.1 41
15 XTAL1
RXD1/P1.2 42
14 XTAL2
TXD1/P1.3 43
13 P3.7/#RD
8
9
10
11
T1/P3.5
P4.2
VDD
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P1.0/T2
43
42
41
40
PWM1/#INT3/P1.5
7
39 P0.4/AD4
INT4/P1.6
8
38 P0.5/AD5
#INT5/P1.7
9
37 P0.6/AD6
RES
10
36 P0.7/AD7
RXD/P3.0
11
35 #EA
P4.3
12
34 P4.1
TXD/P3.1
13
33 ALE/X32OUT
#INT0/P3.2
14
32 #PSEN/X32IN
#INT1/P3.3
15
31 P2.7/A15/ADC3
T0/P3.4
16
30 P2.6/A14/ADC2
T1/P3.5
17
29 P2.5/A13/ADC1
18
#WE/P3.6
7
T0/P3.4
6
#INT1/P3.3
5
RES
#INT5/P1.7
PWM1/#INT3/P1.5
4
P4.3
3
RXD/P3.0
2
INT4/P1.6
1
#INT0/P3.2
12 P3.6/#WE
TXD/P3.1
PWM0/INT2/P1.4 44
44
19
20
21
22
23
24
25
26
27
28
A11/P2.3
20 P2.2/A10
1
ADC0/A12/P2.4
AD1/P0.1 36
2
A9/P2.1
21 P2.3/A11
3
A10/P2.2
AD2/P0.2 35
4
A8/P2.0
22 P2.4/A12/ADC0
5
P4.0
AD3/P0.3 34
6
VSS
23
P1.2/RXD1
24
P1.1/T2EX
25
XTAL2
26
XTAL1
ALE/X32OUT
27
P1.3/TXD1
P4.1
28
#RD/P3.7
#EA
29
P2.5/A13/ADC1
P0.7/AD7
30
P2.6/A14/ADC2
P0.6/AD6
31
#PSEN/X32IN
P0.5/AD5
32
P2.7/A15/ADC3
P0.4/AD4
33
P1.4/INT2/PWM0
Figure 2 44L PLCC Package
Figure 1 44L PQFP Package
P2.0/A8
21
20
VSS
P2.1/A9
22
19
XTAL1
P2.2/A10
23
18
XTAL2
P2.3/A11
24
17
#RD/P3.7
P2.5/A13/ADC1
25
16
P2.4/A12/ADC0
26
15
T1/P3.5
#WE/P3.6
P2.6/A14/ADC2
T0/P3.4
27
14
#INT1/P3.3
P2.7/A15/ADC3
28
13
#INT0/P3.2
#PSEN/X32IN
29
12
TXD/P3.1
ALE/X32OUT
30
11
RXD/P3.0
#EA
31
P0.7/AD7
32
9
10
RES
33
8
#INT5/P1.7
P0.6/AD6
34
7
INT4/P1.6
P0.5/AD5
35
6
PWM1/#INT3/P1.5
P0.4/AD4
36
5
PWM0/INT2/P1.4
P0.3/AD3
37
4
TXD1/P1.3
P0.2/AD2
38
3
RXD1/P1.2
P0.1/AD1
39
2
VDD
40
1
T2/P1.0
T2EX/P1.1
P0.0/AD0
Figure 3 40L PDIP Package
Specifications subject to change without notice contact your sales representatives for the most recent information.
2
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Block Diagram
(1) (1)
Xtal1
Xtal2
Int-RAM
256x8
UART
EA
FLASH
64Kx8
UART1
Ext-RAM
1024x8
C51
CORE
CPU
PWM
(1)
(1)
Timer2
INT5
INT4
INT3
INT2
(1) (1)
T2
(3)
T2EX
PWM0
PWM1
TxD1
RxD1
TxD
RxD
(3)
(1) (1) (1) (1)
Expand
Interrupt/
Wake Up
iBUS
ALE
PSEN
Timer0
Timer1
(3)
RD
(3)
WR
INT /
PDWU
Port0
(3)
(3)
(3)
Port1
Port2
Port3
Port4
(2) (2) (2) (2)
(4) (4)
ADC3
ADC2
ADC1
ADC0
P4
P3
P2
(1): Alternate function of P1
(2): Alternate function of P2
(3): Alternate function of P3
(4): Alternate function of ALE, PSEN
P1
P0
X32OUT
X32IN
INT1
INT0
T1
T0
RES
Notes:
(3)
ADC
Parallel I/O ports & Ext. Bus
RTC
Specifications subject to change without notice contact your sales representatives for the most recent information.
3
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Pin Description
MNEMONIC
DIP 40 pin
PQFP 44 Pin
PLCC 44 pin
VDD
40
38
44
P0.0 – P0.7
39,38,37,36
35,34,33,32
37,36,35,34
33,32,31,30
43,42,41,40
39,38,37,36
P1.0 – P1.7
1,2,3,4,
5,6,7,8
40,41,42,43,
44,1,2,3
2,3,4,5,
6,7,8,9
RST
9
4
10
P2.0 – P2.7
21,22,23,24,
25,26,27,28
18,19,20,21
22,23,24,25
24,25,26,27,
28,29,30,31
MNEMONIC
DIP 40 pin
PQFP 44 Pin
PLCC 44 pin
Names and Functions
Power supply:
+3.3V and +5V power supply pin during normal operations and power
saving modes.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them become floating and can be used as high- impedance
inputs. Port 0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory. In this application,
it uses strong internal pull-ups when emitting 1s.
Port Pin
Alternative function
P0.0
AD0
P0.1
AD1
P0.2
AD2
P0.3
AD3
P0.4
AD4
P0.5
AD5
P0.6
AD6
P0.7
AD7
Port 1:
An 8-bits bidirectional I/O port with internal pull-ups on all pins. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups
and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL).
Alternate function of SM89T16R1 include:
Port Pin
Alternative function
P1.0
T2: TIMER2 clock output
P1.1
T2EX: TIMER2 reload/capture DIR.
P1.2
RxD1: UART1 input
P1.3
TxD1: UART1 output
P1.4
PWM0: PWM channel 0 output
INT2: rising edge trigger
P1.5
PWM1: PWM channel 1 output
#INT3: falling edge trigger
P1.6
INT4: rising edge trigger
P1.7
#INT5: falling edge trigger
Reset:
A high on this pin for two machine cycles while the oscillator is running
resets the device. An internal resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
Port 2:
Port 2 is an 8-bits bidirectional I/O port with internal pull-ups. Port 2 pins
that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being
pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to
external data memory that uses 16-bits addresses (MOVX @DPTR). In
this application, it uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that uses 8-bits addresses (MOV @Ri),
port 2 emits the contents of the P2 special function register.
Port Pin
Alternative function
P2.0
A8
P2.1
A9
P2.2
A10
P2.3
A11
P2.4
A12/ADC0
P2.5
A13/ADC1
P2.6
A14/ADC2
P2.7
A15/ADC3
Names and Functions
Specifications subject to change without notice contact your sales representatives for the most recent information.
4
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
P3.0 – P3.7
10,11,12,13
14,15,16,17
5,7,8,9,
10,11,12,13
11, 13,14,15,
16,17,18,19
ALE/X32OUT
30
27
33
#PSEN/X32IN
29
26
32
#EA
31
29
35
XTAL1
19
15
21
XTAL2
18
14
20
Port 3:
Port 3 is an 8-bits bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being
pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also serves the special features.
Port Pin
Alternative function
P3.0
RxD UART input
P3.1
TxD UART output
P3.2
#EX0 external interrupt 0
P3.3
#EX1 external interrupt 1
P3.4
T0: Timer 0 external input
P3.5
T1: Timer 1 external input
P3.6
#WR External data memory write strobe
P3.7
#RD External data memory read strobe
Address Latch Enable:
Output pulse for latching the low byte of the address during an access to
external memory. In normal operation, ALE is emitted twice every
machine cycle, and can be used for external timing or clocking. Note that
one ALE pulse is skipped during each access to external data memory.
Setting SFR SCONF.0 can disable ALE. With this bit set, ALE will be
active only during a MOVX instruction.
X32OUT: The 32.768KHz crystal output for RTC function.
Program Store Enable:
The read strobe to external program memory. When executing code from
the external program memory, #PSEN is activated twice each machine
cycle, except that two #PSEN activations are skipped during each access
to external data memory. #PSEN is not activated during fetches from
internal program memory.
X32IN: The 32.768KHz crystal input for RTC function.
External Access Enable:
#EA must be externally held low to enable the device to fetch code from
external program memory locations. If #EA is held high, the device
executes from internal program memory.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
SFR Mapping
The special function register of SM89T16R1 fall into the following categories
z C51 CORE register: ACC, B, DPL, DPH, PSW, SP
z I/O ports: P0,P1, P2, P3, P4
z Timer/Counter register: T2CON, T2MOD, TCON, TMOD, TH0, TH1, TH2, TL0, TL1, TL2, RCA2PL,
RCAP2H
z The Second DPTR register: DPS, DPH1, DPL1
z UART I/O register: SBUF, SCON
z UART1 I/O register: SBUF1, SCON1
z ADC register: ADCSC, ADCD, P2CON
z Power and system control register: PCON, SCONF
z Interrupt system register: IP, IE, IP1, IE1, IFR
z Expand External Interrupt register: EIE, EIP, EXIF
z RTC register: RTCC, RTCS
z PWM output register: PWMC0, PWMC1, PWMD0, PWMD1, P1CON
z PMM (Power Management) register: PMR
Specifications subject to change without notice contact your sales representatives for the most recent information.
5
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Table 1 SFR Map
$F8
$F0
SCON1
0000 0000
B
0000 0000
$E8
$E0
$D8
$D0
$C8
$F7
SADEN
0000 0000
ACC
0000 0000
P4
xxxx 1111
PSW
0000 0000
T2CON
0000 0000
$FF
SBUF1
xxxx xxxx
$EF
SADEN1
0000 0000
$E7
SADDR
0000 0000
PMR
01xx 0000
T2MOD
0000 0000
$DF
SADDR1
0000 0000
RCAP2L
0000 0000
PWMC0
0000 0000
RCAP2H
0000 0000
PWMC1
0000 0000
TL2
0000 0000
$D7
TH2
0000 0000
$CF
$C7
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
IP
x000 0000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
IP1
0000 0000
IE1
0000 0000
RTCS
0000 0000
SBUF
xxxx xxxx
EXIF
0000 1xxx
TMOD
0000 0000
SP
0000 0111
EIP
xxxx 0000
IFR
0000 0000
RTCC
0000 0000
LEDP0
0000 0000
TL0
0000 0000
DPL
0000 0000
SCONF
0000 0000
PWMD0
0000 0000
EIE
0000 0000
CKCON
0000 0001
P1CON
0000 0000
LEDP1
0000 0000
TL1
0000 0000
DPH
0000 0000
$BF
$B7
PWMD1
0000 0000
$AF
DPL1
0000 0000
P2CON
0000 0000
LEDP2
0000 0000
TH0
0000 0000
DPH1
0000 0000
$A7
DPS
0000 0000
$9F
LEDP3
0000 0000
TH1
0000 0000
LEDP4
0000 0000
ADCSC
0000 0000
$97
ADCD
0000 0000
PCON
00xx 0000
$8F
$87
Table 2 All SFR list (ADC, RTC, PWM, LED Driving Capability Control)
Symbol
ADCSC
ADCD
Description
Direct
Bit 7
ADC status & control
ADC data register
8EH
8FH
COM
AD.5
RTC Status
RTC Control
A1H
A2H
RTCen
Int_sel.1
PWMC0
PWMC1
PWMD0
PWMD1
PWM 0 Control
PWM 1 Control
PWM 0 Data
PWM 1 Data
D3H
D4H
B3H
B4H
LEDP 0
LEDP 1
LEDP 2
LEDP 3
LEDP 4
LED output in P0
LED output in P1
LED output in P2
LED output in P3
LED output in P4
92H
93H
94H
95H
96H
RTCS
RTCC
PWMD.7
PWMD.7
Bit 6
Bit 5
Bit 4
A/D Converter
CON
ADCSS1 ADCSS0
AD.4
AD.3
AD.2
Real Timer Clock (RTC)
Stable
Sec.5
Sec.4
Int_sel.0
Min.5
Min.4
PWM output
PWMD.6
PWMD.6
PWMD.5
PWMD.5
PWMD.4
PWMD.4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
CH1
AD.1
CH0
AD.0
Sec.3
Min.3
Sec.2
Min.2
Sec.1
Min.1
Sec.0
Min.0
00H
00H
PBS
PBS
PFS1
PFS1
PFS0
PFS0
PWMD.2
PWMD.2
PWMD.1
PWMD.1
PWMD.0
PWMD.0
00H
00H
00H
00H
PWMD.3
PWMD.3
00H
00H
LED Driving Capability Control
00H
00H
00H
00H
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
6
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Table 3 : All SFR list (8051, I/O, Timer, UART/UART1, System, Interrupt)
Symbol
Description
Direct
ACC*
B
SP
PSW*
DPTR
DPH
DPL
Accumulator
B register
Stack Pointer
Process Status
Data Pointer (2 Bytes)
Data Pointer High
Data Pointer Low
E0
F0
81H
D0H
P0*
P1*
P2*
P3*
P4*
P1CON
P2CON
Port 0
Port 1
Port 2
Port 3
Port 4
P1 Control
P2 Control
80H
90H
A0H
B0H
D8H
9BH
9CH
ADCE3
TCON*
THL0
TH0
TL0
THL1
TH1
TL1
T2CON*
T2MOD
Timer Control register
Timer 0 (2 Bytes)
Timer 0 High
Timer 0 Low
Timer 1 (2 Bytes)
Timer 1 High
Timer 1 Low
Timer 2 Control
Timer 2 Mode Control
Reload/Capture (2 bytes)
RCAP2 High
RCAP2 Low
Time 2 (2 bytes)
Timer 2 High
Time 2 Low
88H
TF1
RCAP2HL
RCAP2H
RCAP2L
THL2
TH2
TL2
SCON*
SBUF
SCON1
SBUF1
SADDR
SADDR1
SADEN
SADEN1
UART Control
UART Buffer
UART 1 Control
UART 1 Buffer
Slave Address
Slave Address 1
Slave Address Mask
Enable
Slave Address 1 Mask
Enable
Bit 7
CY
Bit 6
Bit 5
8051 Core
AC
F0
Bit 4
RS1
Bit 3
RS0
Bit 2
Bit 1
OV
Bit 0
RESET
P
00H
00H
07H
00H
83H
82H
00H
00H
P0.7
P1.7
P2.7
P3.7
I/O PORT
P0.5
P1.5
P2.5
P3.5
P0.6
P1.6
P2.6
P3.6
P0.4
P1.4
P2.4
P3.4
PWM1E
PWM0E
ADCE2
ADCE1
ADCE0
TIMER / Counter
TF1
TF0
TR0
P0.3
P1.3
P2.3
P3.3
P4.3
P0.2
P1.2
P2.2
P3.2
P4.2
P0.1
P1.1
P2.1
P3.1
P4.1
-
P0.0
P1.0
P2.0
P3.0
P4.0
-
FFH
FFH
FFH
FFH
XFH
00H
00H
IE1
IT1
IE0
IT0
00H
8CH
8AH
00H
00H
8DH
8BH
C8H
C9H
00H
00H
00H
00H
TF2
HC5
EXF2
HC4
RCLK
HC3
TCLK
HC2
EXEN2
T2CR
TR2
CT2
T2OE
CPRL2
DCEN
CBH
CAH
00H
00H
CDH
CCH
00H
00H
98H
99H
F8H
F9H
D9H
DAH
UART & UART1
SM2
REN
SM0/FE
SM1
SM0_1/FE_1
SM1_1
SM2_1
REN_1
TB8
RB8
TI
RI
TB8_1
RB8_1
TI_1
RI_1
E9H
00H
XXH
00H
XXH
00H
00H
00H
EAH
00H
Data Point 1
DPTR1
DPH1
DPL1
DPS
PCON
SCONF
PMR
IE*
IE1
IFR
EIE
IP*
IP1
EIP
CKCON
Data Pointer 1 (2 Bytes)
Data Pointer 1 High
Data Pointer 1 Low
Data Point Select
A5H
A4H
A6H
Power and System
SMOD0
Power Control register
System Control
Power Management
Register
87H
BFH
SMOD
SMOD1
D1H
CD1
CD0
Interrupt Enable
Interrupt Enable 1
Interrupt Flag 1
External Interrupt Enable
Interrupt Priority
Interrupt Priority 1
External Interrupt Priority
A8H
A9H
AAH
ABH
B8H
B9H
BAH
EA
ES1
Interrupt system
ET2
ES0
PS1
PT2
PS0
Clock Control
A3H
PD
OME
PDWUE
DPS.0
00H
00H
00H
IDLE
ALEI
00H
00H
XTOFF
Clock Control
T2M
T1M
40H
ET1
EADC
ADCIF
EX5
PT1
PADC
PX5
EX1
ERTC
RTCIF
EX4
PX1
PRTC
PX4
T0M
MD2
ET0
EX0
EX3
PT0
EX2
PX0
PX3
PX2
00H
00H
00H
00H
00H
00H
X0H
MD1
MD0
01H
Specifications subject to change without notice contact your sales representatives for the most recent information.
7
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Operating Conditions
Symbol
TA
VCC33
VCC5
Fosc 16
Fosc 25
Description
Operating temperature
Supply voltage
Supply voltage
Oscillator Frequency
Oscillator Frequency
Min.
-40
3.0
4.5
Typ.
25
3.3
5.0
Max.
85
3.6
5.5
16
25
Unit.
℃
V
V
MHz
MHz
Remarks
Ambient temperature under bias
For 3.3V application
For 5.0V application
DC Characteristic
VCC = 5V (±10%), VSS=0V TA= -40℃ to 85℃
SYMBOL
TEST
CONDITIONS
PARAMETER
VCC
Supply Voltage
ICC
Supply current operating
IID
Supply current IDLE Mode
IPD
Supply current Power-Down MODE RTC
Disable
Supply current Power-Down MODE RTC
Enable
VIL1
VIL2
VIH1
VIH2
IIL
ITL
ILI
Input LOW voltage, P0, P1, P2, P3, P4, /EA
Input LOW voltage, RES, XTAL1
Input HIGH voltage, P0, P1, P2, P3, P4, /EA
Input HIGH voltage, RES, XTAL1
Input current LOW level Port 1,2,3,4
Transition current High to Low Port 1,2,3,4
Input leakage current
VOL1
VOL2
VOH1
VOH1
RRST
CIO
Output LOW voltage, Port 0,ALE, /PSEN
Output LOW voltage, Port 1, 2, 3, 4
Output High voltage Port0 ALE, /PSEN
Output High voltage Port 1,2,3,4
Internal RESET pull-down resistor
Pin capacitance
LIMITS
MIN
MAX
4.5
5.5
See notes 1
fCLK = 12MHz VCC = 5.0V
See note 2
fCLK = 12MHz VCC = 5.0V
UNIT
V
30
mA
15
mA
See note 3；VCC = 5.5V
30
µA
See note 3；VCC = 5.5V
100
uA
0.8
0.8
Vcc+0.5
Vcc+0.5
-75
-650
±10
V
V
V
V
µA
µA
µA
0.45
0.45
V
V
V
V
kΩ
pF
INPUT
-0.5
0
2.0
70%VCC
VIN = 0.45V
VIN = 2.0 V
0.45V < VIN < VCC-0.3V
OUTPUT
IOL = 3.2mA，VCC=5.0V
IOL = 1.6mA，VCC =5.0V
IOH = -800uA，VCC =5.0V
IOH = -60µA，VCC =5.0V
2.4
2.4
50
300
10
Test freq=1MHz, TA=25℃
VCC = 3.3V (±10%), VSS=0V , TA=-40℃ to 85℃
SYMBOL
VCC
ICC
IID
IPD
TEST
CONDITIONS
PARAMETER
Supply Voltage
MIN
3.0
LIMITS
MAX
3.6
See notes 1
Supply current operating
fCLK = 12MHz VCC = 3.6V
See note 2
Supply current IDLE Mode
fCLK = 12MHz VCC = 3.6V
See note 3；VCC = 3.6V
Supply current Power-Down MODE RTC Disable
See note 3；VCC = 3.6V
Supply current Power-Down MODE RTC Enable
INPUT
VIL1
Input LOW voltage, P0, P1, P2, P3, P4, /EA
VCC = 3.6V
0
VIL2
Input LOW voltage, RST,XTAL1
VCC = 3.6V
0
VIH1
Input HIGH voltage, P0, P1, P2, P3, P4, /EA
VCC = 3.6V
0
VIH2
Input HIGH voltage, RST
VCC = 3.6V
VIH3
Input HIGH voltage, XTAL1
VCC = 3.6V
0.6 VCC
-0.4
0.6 VCC
UNIT
V
20
mA
10
mA
20
30
µA
µA
0.2 VCC
-0.2
0.2 VCC
-0.2
0.2 VCC
-0.2
V
V
V
VCC + 0.2
V
VCC + 0.2
V
Specifications subject to change without notice contact your sales representatives for the most recent information.
8
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
-0.4
IIN1
Input current LOW level Port 1,2,3,4
ITL
Transition current High to Low Port 1,2,3,4
ILI
Input leakage current P0, /EA
VOL1
VOL2
VOH1
VOH2
ISK1
ISK2
ISR1
ISR2
RRST
CIO
Output Low voltage, Port 0,ALE, /PSEN
Output Low voltage Port 1,2,3,4
Output High voltage Port0, ALE, /PSEN
Output High voltage Port 1,2,3,4
Sink Current Port 1, 2, 3, 4
Sink Current Port 0,ALE, /PSEN
Source Current Port 1, 2, 3, 4
Source Current Port 0,ALE, /PSEN
Internal RESET pull-down resistor
Pin capacitance
VCC = 3.0V ~3.6V,
VIN = 0.45V.
See note 4
VCC = 3.6V, VIN = 1.2 V
VCC = 3.0V ~3.6V,
0.45V<VIN<VCC
OUTPUT
IOL = 7mA，VCC =3.3V
IOL = 7mA，VCC =3.3V
IOH =-300uA，VCC =3.3V
IOH =-20µA，VCC =3.3V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 2.4 V
VCC = 3.3V, VIN = 2.4 V
-10
50
µA
-75
400
µA
-10
10
µA
0.4
0.4
V
V
V
V
mA
mA
uA
mA
kΩ
pF
2.4
2.4
50
Test freq=1MHz, TA=25℃
6
8
-80
-8
300
10
NOTES FOR DC ELECTRICAL CHARACTERISTICS
1.
The operating supply current is measured with all output disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;/EA=RST=Port0=VCC.
2.
The IDLE MODE supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V;
VIH=VCC-0.5V; XTAL2 not connect;/EA= Port0=VCC.
3.
The POWER-DOWN MODE supply current is measured with all output pins disconnected; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not
connect; /EA= Port0=VCC.
4.
Port 1, 2, 3, and 4 sources a transition current when they are being externally driven from HIGH to LOW. The transition current reaches
its maximum value when VIN is approximately 2V.
5.
Capacities loading on port 0 and 2 may cause spurious noise to be superimposed on VOL of ALE and port 1, 3, and 4. The noise is due to
external bus capacitance discharging into port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacities loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt trigger STROBE input.
Specifications subject to change without notice contact your sales representatives for the most recent information.
9
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
AC Characteristic
VCC=3.3V±10%, VSS=0V, tclk min = 1/ fmax(maximum operating frequency)
TA=-40℃ to +85℃
CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
tCYC
PARAMETER
MIN
External Clock drive into XTAL1
Xtal1 Period
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time = tCLCL / 4
4
4
4
4
4
4
62.5 (1)
31
31
5.2
MAX
15
15
-
UNIT
ns
ns
ns
ns
ns
ns
NOTES:
1.
Operating at 25MHz.
Symbol
FIGURE
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV1
tAVIV2
tPLAZ
7
7
7
7
8
7
7
7
7
7
7
7
7
7
PARAMETER
MIN
Program Memory
System clock frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
Address hold after ALE low for MOVX Write
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Port 0 Address to valid instruction in
Port 2 Address to valid instruction in
/PSEN low to address float
3.0
1.5 tCLCL -5
0.5 tCLCL -5
0.5 tCLCL -5
0.5 tCLCL -5
0.5 tCLCL -5
2.0 tCLCL -5
0
MAX
16
2.5tCLCL-20
2.0tCLCL-20
tCLCL -5
3.0tCLCL-20
3.5tCLCL-20
0
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOVX Characteristics Using Stretch Memory Cycles
Symbol
FIGURE
PARAMETER
MIN
tLHLL2
8
ALE pulse width
tLLAX2
tRLRH
9
8
Address hold after ALE low for MOVX Write
/RD pulse width
tWLWH
9
/WR pulse width
tRLDV
8
/RD LOW to valid data in
tRHDX
tRHDZ
8
8
Data hold after /RD
Data float after /RD
tLLDV
8
ALE LOW to valid data in
tAVIV1
8
Port 0 Address to valid instruction in
tAVIV2
7,8
Port 2 Address to valid instruction in
tLLWL
8,9
ALE LOW to /RD or /WR LOW
tAVWL1
8,9
Port0 Address valid to /WR or /RD LOW
tAVDV2
9
Port2 Address valid to /WR or /RD LOW
1.5 tCLCL –5
2.0 tCLCL -5
0.5 tCLCL -5
2.0 tCLCL –5
tMCS -10
2.0 tCLCL –5
tMCS -10
0
0.5 tCLCL–5
1.5 tCLCL–5
tCLCL–5
2.0 tCLCL–5
1.5tCLCL–5
MAX
UNIT
Stretch
ns
tMCS =0
tMCS >0
ns
ns
ns
2.0 tCLCL –20
tMCS -20
tCLCL –5
2.0 tCLCL –5
2.5 tCLCL –5
tMCS+2.0tCLCL –40
3.0 tCLCL-20
2.0 tCLCL –5
3.5 tCLCL-20
2.5 tCLCL –5
0.5 tCLCL+5
1.5 tCLCL+5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
Specifications subject to change without notice contact your sales representatives for the most recent information.
10
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
tQVWX
9
Data valid to /WR transition
tWHQX
9
Data hold after /WR
tRLAZ
tWHLH
8
8,9
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
2.5 tCLCL–5
-5
1.0 tCLCL -5
1.0 tCLCL -5
2.0 tCLCL -5
0
1.0 tCLCL -5
ns
ns
0.5 tCLCL–5
10
1.0 tCLCL +5
ns
ns
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
tMCS =0
tMCS >0
Notes:
tMCS is time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection.
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Parameter
Serial Port Clock Cycle Time
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
Output Data Setup to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
Output Data Hold to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
Input Data Hold to Clock Rising
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
Clock Rising Edge to Input Data Valid
SM2=0,12 clocks per cycle
SM2=1,4 clocks per cycles
MOVX Cycles
2 machine cycles
3 machine cycles
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
Figure
10
Symbol
tXLXL
tMCS
0
4 tCLCL
8 tCLCL
12 tCLCL
16 tCLCL
20 tCLCL
24 tCLCL
28 tCLCL
Min
Typ
12 tCLCL
4 tCLCL
Max
Unit
ns
ns
10
tQVXH
12 tCLCL
4 tCLCL
ns
ns
10
tXHQX
12 tCLCL
4 tCLCL
ns
ns
10
tXHDX
12 tCLCL
4 tCLCL
ns
ns
10
tXHDV
12 tCLCL
4 tCLCL
ns
ns
tCHCX
tCLCH
VIH1
tCHCL
0.8V
tCLCX
tCLCL
Figure 4 External Clock Drive waveform
2.0V
Test Points
0.8V
Floating
2.0V
0.8V
2.0V
2.0V
0.8V
0.8V
Notes:
Notes:
The float state is define as the point which PORT 0 pins sinks
3.2mA or source 400µA at the voltage test level.
AC inputs during testing are driven at 2.4V for logic “HIGH” and
0.45V for logic “LOW”. Timing measurements are at 2.0V for
logic “HIGH” and 0.8V for logic “LOW”
Figure 5 AC Testing Input/Output
Figure 6 AC Testing, Floating Waveform
Specifications subject to change without notice contact your sales representatives for the most recent information.
11
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
t LHLL
ALE
t LLPL
t PLPH
t AVLL
t PLIV
/PSEN
t PLAZ
t LLAX
t PXIZ
t LLIV
PORT0
t PXIX
A0-A7
INSTR IN
A0-A7
t AVIV2
t AVIV1
PORT2
A8-A15
A8-A15
A8-A15
Figure 7 External Program Memory Read Cycle
t LLHL2
t
LLDV
ALE
t WHLH
/PSEN
t LLWL
t
t LLAX1
RLRH
t RLDV
/RD
t
t
AVLL
t
PORT0 Instruction IN
t RHDZ
RLAZ
t RHDX
AVWL1
A0-A7
DATA IN
A0-A7
t AVIV1
t
PORT2
AVIV2
A8-A15
A8-A15
A8-A15
Figure 8 External Data Memory Read cycle
t LLHL2
ALE
t WHLH
/PSEN
t LLAX2
t LLWL
t WLWH
/WR
t AVLL
t QVWX
t AVWL1
PORT0 Instruction IN
t LWHQX
A0-A7
DATA OUT
A0-A7
t AVDV2
PORT2
A8-A15
A8-A15
A8-A15
Figure 9 External Data Memory Write cycle
UART (Synchronous Mode)
High Speed Operation SM2=1 => TXD Clock =XTAL/4
ALE
/PSEN
WRITE_TO_SBUF
t
TXD_DATA_OUT
QVXH
D0
D1
t
D2
D3
t
XHQX
D4
D5
D6
D7
D8
XHDX
TXD_CLOCK
t
XLXL
TI
WRITE_TO_SCON_TO_CLEAN_RI
RXD_DATA_IN
D0
D1
t
D2
D3
D4
D5
D6
D7
D8
XHDV
TXD_CLOCK
RI
Figure 10 UART Mode 1Timing
Specifications subject to change without notice contact your sales representatives for the most recent information.
12
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
UART (Synchronous Mode)
SM2=0 => TXD Clock =XTAL/12
ALE
/PSEN
WRITE_TO_SBUF
TXD_DATA_OUT
D0
D1
D6
D7
TXD_CLOCK
TI
WRITE_TO_SCON_TO_CLEAN_RI
RXD_DATA_IN
D0
D1
D6
D7
TXD_CLOCK
RI
Figure 11 UART Mode 0 Timing
Function Description
The SM89T16R1 is a High-Speed (4 clocks/machine cycle) stand-alone high-performance microcontroller designed
for use in 3V/5V application, such as LCD monitor, instrumentation, or high-end consumer applications.
In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these
applications.
The SM89T16R1 is a control-oriented CPU with on-chip program and data memory. It can be extended with external
data memory up to 64K bytes. For system requiring extra capability, the SM89T16R1 can be enhanced by using
external memory and peripherals.
The SM89T16R1 has two software selectable modes of saving power consumption-IDLE and POWER-DOWN. The
IDLE mode freezes the CPU while allowing the RAM, timer, serial ports and interrupt system to continue functioning.
The POWER-DOWN mode save the RAM contents but freezes the oscillator causing all other chip functions to be
inoperative. The POWER-DOWN mode can be terminated by H/W reset, or by any one of the six external interrupt or
RTC function.
CPU
The CPU of SM89T16R1 is High-Speed 80C51. The structure of this CPU is shown as FIGURE 12. It contains
Instruction Register (IR), Instruction Decoder, Program Counter (PC), Accumulator (ACC), B Register, and control
logic. This CPU provides an 8-bits bi-direction bus to communicate with other blocks in the chip. The address and
data are transferred through on the same 8-bits bus.
Specifications subject to change without notice contact your sales representatives for the most recent information.
13
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
PROG.
ADDR.
IRQ
ACC
RES
CONTROL
LOGIC
Timing & Reset
PROGRAM
ADDR.REGISTER
TMP2
TMP1
CLK
BUFFER
CTRL.
BUS
INSTRUCTION
DECODER
PROGRAM
INCREMENT
ALU
SP
PROGRAM
COUNTER
B
Register
INSTRUCTION
REGISTER
PSW
DPTR
DATA
IN/OUT
PCON
POWER CTRL Signal
Figure 12 The CPU Structure
CPU Timing
The machine cycle consists of a sequence of 4 states, numbered S1 through S4. Only one-oscillator periods for each
state time. Thus a machine cycle takes 4 oscillator periods. FIGURE 13 Shows relationships between oscillator, phase,
and S1-S4.
Sequence
S1
S2
S3
S4
S1
S2
S3
S4
S1
S2
S3
S4
S1
S2
S3
S4
S1
S2
S3
S4
OSC
(Xtal2)
Machine
Cycle
M1
M2
M3
M4
M5
Figure 13 Sequences and Phases
FIGURE 14 shows the fetch / execute sequences in states and phases for various kinds of instructions. Normally the
program fetches are generated during each machine cycle, even if the instruction being executed doesn’t require it. If
the instruction being executed doesn’t need more code bytes, the CPU simply ignores the extra fetch, and the
PROGRAM COUNTER is incremented accordingly.
Due to the reduced time for each instruction execution, both of the clocks edges are used for internal timing. Hence it
is important that the duty cycle of the clock be as close to 50% as possible to avoid timing conflicts. The SM89T16R1
dose one op-code fetch per machine cycle. Therefore, in most of the instructions, the number of machine cycles
needed to execute the instruction is equal to the number of bytes in the instruction. Of the 256 available op-codes, 128
of them are signal cycle instruction. See Figure14 shows the different cycle (A-D) instruction timing.
Specifications subject to change without notice contact your sales representatives for the most recent information.
14
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
A.) Signal Cycle Instruction Timing
Single_Cycle
S1
S2
S3
S4
CLK
ALE
/PSEN
AD7-0
A7-A0
Data
PORT_2
A15-A8
B.) Two Cycles Instruction Timing
Instruction_Fetch
S1
S2
Operand_Fetch
S3
S4
S1
S2
S3
S4
CLK
ALE
/PSEN
AD7-0
A7-A0
OP-CODE
PORT_2
A7-A0
OPERAND
A15-A8
A15-A8
C.) Three Cycles Instruction Timing
Instruction_Fetch
S1
S2
S3
Operand_Fetch
S4
S1
S2
S3
Operand_Fetch
S4
S1
S2
S3
S4
CLK
ALE
/PSEN
AD7-0
A7-A0
PORT_2
OP-CODE
A7-A0
A15-A8
OPERAND
A7-A0
A15-A8
OPERAND
A15-A8
D.) Four Cycles Instruction Timing
Instruction_Fetch
S1
S2
S3
S4
Operand_Fetch
S1
S2
S3
S4
Operand_Fetch
S1
S2
S3
S4
Operand_Fetch
S1
S2
S3
S4
CLK
ALE
/PSEN
AD7-0
PORT_2
A7-A0 OP-CODE
A15-A8
A7-A0 OPERAND
A7-A0 OPERAND
A15-A8
A7-A0 OPERAND
A15-A8
A15-A8
Figure 14 Timing of various instructions
In standard 8032, the MOVX instructions take two machine cycles to execute. However in the SM89T16R1, the user
has a facility to stretch the duration of this instruction from 2 machines cycle to 9 machines. The /RD and /WR strobe
lines are also proportionately elongated. This gives the user flexibility in accessing both fast and slow peripherals
without the use of external circuitry and with minimum software overhead. See FIGURE 15
Specifications subject to change without notice contact your sales representatives for the most recent information.
15
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
A) Data Memory Write with Stretch Value = 0(MOVX Instruction execute 2 machine cycles)
MOVX_Instruction_cycle
Last_Instruction
S1
S2
Next_Instruction
First_Machine_cycle
S3
S4
S1
S2
Second_Machine_cycle
S3
S4
S1
S2
S3
S4
S1
S2
S3
S4
CLK
ALE
/PSEN
WR_width
/WR
MOVX_Data_out
MOVX_Inst.
AD7-0
A7-A0
D7-D0
Next_inst._Read
A7-A0
D7-D0
A7-A0
D7-D0
MOVX_Inst._Address
A7-A0
D7-D0
MOVX_Data_Address
Next_Inst._Address
PORT_2
A15-A8
A15-A8
A15-A8
A15-A8
B) Data Memory Write with Stretch Value = 1(MOVX Instruction execute 3 machine cycles)(Default)
MOVX_Instruction_Cycle
Second_Machine_cycle
Last_Instruction
S1
S2
Next_Instruction
First_Machine_cycle
S3
S4
S1
S2
S3
S4
S1
S2
Third_Machine_Cycle
S3
S4
S1
S2
S3
S4
S1
S2
S3
S4
CLK
ALE
/PSEN
WR_width
/WR
Next_inst._Read
MOVX_Inst.
AD7-0
A7-A0
D7-D0
MOVX_Data_out
A7-A0
D7-D0
A7-A0
D7-D0
MOVX_Inst._Address
A7-A0
D7-D0
MOVX_Data_Address
Next_Inst._Address
PORT_2
A15-A8
A15-A8
A15-A8
A15-A8
C) Data Memory Write with Stretch Value = 2(MOVX Instruction execute 4 machine cycles)
MOVX_Instruction_Cycle
2'nd_Machine_cycle
Next_Instruction
1'st_Machine_cycle
4'th_Machine_Cycle
Last_Instruction
S2
S4
S1
S3
3'rd_Machine_Cycle
S2
S1
S4
S3
S2
S1
S4
S3
S2
S1
S4
S3
S2
S1
S4
S3
S2
S1
S4
S3
CLK
ALE
/PSEN
WR_width
/WR
Next_inst._Read
MOVX_Inst.
AD7-0
A7-A0
D7-D0
A7-A0
MOVX_Data_out
D7-D0
D7-D0
A7-A0
MOVX_Inst._Address
A7-A0
D7-D0
MOVX_Data_Address
Next_Inst._Address
PORT_2
A15-A8
A15-A8
A15-A8
A15-A8
Figure 15: MOVX Instruction Timing (Stretch=0~Stretch=2)
Specifications subject to change without notice contact your sales representatives for the most recent information.
16
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Instruction Set
The SM89T16R1 is High-Speed 80C51; it’s contained 4 clocks per machine. The SM89T16R1 dose one op-code
fetch per machine cycle .It consists of 111 instructions used 40 single-cycle, 38 used two-cycles,
19 used three-cycles, and 10 used four-cycles.
A summary of the instruction set is given in Table 4.
Addressing Mode
Notes on instruction set and address modes:
Rn
Direct
@Ri
#data
#data16
addr11
Rel
Bit
Register R7-R0 of the currently selected register bank.
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a SFR[i.e., I/O port,
control register, status register, etc.(128-255) ]
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank
8-bits constant included in the instruction
16-bits constant included in the instruction
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the same 2 Kbytes page
of program memory as the first byte of the following instruction.
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes
relative to first byte of the following instruction.
Direct addressed bit in internal data RAM or SFR
Table 4: summary of the instruction
Mnemonic
Arithmetic Instructions
ADD
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
ADDC
A,@Ri
ADDC
A,#data
SUBB
A,Rn
SUBB
A,direct
SUBB
A,@Ri
SUBB
A,#data
INC
A
INC
Rn
INC
direct
INC
@Ri
DEC
A
DEC
Rn
DEC
direct
DEC
@Ri
INC
DPTR
DEC
DPTR
MUL
AB
DIV
AB
DA
A
Logical Instructions
ANL
A,Rn
ANL
A,direct
ANL
A,@Ri
ANL
A,#data
ANL
direct,A
ANL
direct,#data
ORL
A,Rn
ORL
A,direct
ORL
A,@Ri
ORL
A,#data
ORL
direct,A
ORL
direct,#data
OPERATION
BYTE
CYCLE
A = A + Rn
A = A + direct
A = A + <@Ri>
A = A + #data
A = A + Rn + C
A = A + direct + C
A = A + @Ri + C
A = A + #data + C
A = A － Rn － C
A = A － direct － C
A = A － <@Ri> － C
A = A－#data － C
A=A+1
Rn = Rn + 1
direct = direct + 1
<@Ri> = <@Ri> + 1
A=A － 1
Rn = Rn － 1
direct = direct － 1
<@Ri> = <@Ri> － 1
DPTR = DPTR + 1
DPTR = DPTR － 1
B:A = A × B
A = INT (A/B),B = MOD (A/B)
Decimal adjust ACC
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
3
1
A .AND. Rn
A .AND. direct
A .AND. <@Ri>
A .AND. #data
direct .AND. A
direct .AND. #data
A .OR. Rn
A .OR. direct
A .OR. <@Ri>
A .OR. #data
direct .OR. A
direct .OR. #data
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
1
2
1
2
2
3
Specifications subject to change without notice contact your sales representatives for the most recent information.
17
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
XRL
A,Rn
XRL
A,direct
XRL
A,@Ri
XRL
A,#data
XRL
direct,A
XRL
direct,#data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
Data Transfers Instructions
MOV
A,Rn
MOV
A,direct
MOV
A,@Ri
MOV
A,#data
MOV
Rn,A
MOV
Rn,direct
MOV
Rn,#data
MOV
direct,A
MOV
direct,Rn
MOV
direct,direct
MOV
direct,@Ri
MOV
direct,#data
MOV
@Ri,A
MOV
@Ri,direct
MOV
@Ri,#data
MOV
DPTR,#data16
MOVC
A,@A+DPTR
MOVC
A,@A+PC
MOVX
A,@Ri
MOVX
A,@DPTR
MOVX
@Ri,A
MOVX
@DPTR,A
PUSH
direct
POP
direct
XCH
A,Rn
XCH
A,direct
XCH
A,@Ri
XCHD
A,@Ri
Boolean Instructions
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C,bit
ANL
C,/bit
ORL
C,bit
ORL
C,/bit
MOV
C,bit
MOV
bit,C
JC
rel
JNC
rel
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
Jump Instructions
JZ
rel
JNZ
rel
JMP
@A+DPTR
A .XOR. Rn
A .XOR. direct
A .XOR. <@Ri>
A .XOR. #data
direct .XOR. A
direct .XOR. #data
A=0
A = /A
Rotate ACC Left 1 bit
Rotate Left through Carry
Rotate ACC Right 1 bit
Rotate Right through Carry
Swap Nibbles in A
1
2
1
2
2
3
1
1
1
1
1
1
1
1
2
1
2
2
3
1
1
1
1
1
1
1
A = Rn
A = direct
A = <@Ri>
A = #data
Rn = A
Rn = direct
Rn = #data
direct = A
direct = Rn
direct = direct
direct = <@Ri>
direct = #data
<@Ri> = A
<@Ri> = direct
<@Ri> = #data
DPTR = #data16
A = code memory[A+DPTR]
A = code memory[A+PC]
A = external memory[Ri] (8-bits address)
A = external memory[DPTR] (16-bits address)
external memory[Ri] = A (8-bits address)
external memory[DPTR] = A (16-bits address)
INC SP: MOV “@’SP’, < direct >
MOV < direct >, “@SP”: DEC SP
ACC and < Rn > exchange data
ACC and < direct > exchange data
ACC and < Ri > exchange data
ACC and @Ri exchange low nibbles
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
2
1
2
1
2
2
2
2
3
2
2
1
2
2
3
3
3
2~9
2~9
2~9
2~9
2~9
2~9
1
2
1
1
C=0
bit = 0
C=1
bit = 1
C = /C
bit = /bit
C = C .AND. bit
C = C .AND. /bit
C = C .OR. bit
C = C .OR. /bit
C = bit
bit = C
Jump if C= 1
Jump if C= 0
Jump if bit = 1
Jump if bit = 0
Jump if C = 1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
2
1
2
1
2
2
2
2
2
2
2
3
3
4
4
4
Jump if A = 0
Jump if A ≠ 0
Jump to A+ DPTR
2
2
1
3
3
2
Specifications subject to change without notice contact your sales representatives for the most recent information.
18
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
DJNZ
DJNZ
CJNE
CJNE
CJNE
CJNE
ACALL
AJMP
LCALL
LJMP
SJMP
RET
RETI
NOP
Ri,rel
Direct,rel
A,direct,rel
A,#data,rel
@Ri,#data,rel
Ri,#data,rel
Address11
Address11
Address16
Address16
rel
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
Jump if A ≠ < direct >
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Call Subroutine only at 2k bytes Address
Jump only At 2k bytes addressing
Call Subroutine in max 64K bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Return from subroutine
Return from interrupt
No Operation
2
3
3
3
3
3
2
2
3
3
2
1
1
1
3
4
4
4
4
4
3
3
4
4
3
3
3
1
Memory organization
Program memory
The program memory of SM89T16R1 consists of 64K bytes FLASH memory on chip. If during RESET, the /EA pin
was held HIGH, the SM89T16R1 does not execute out of the internal program memory. If the /EA pin was held LOW
during RESET the SM89T16R1 fetch all instructions from the external program memory.
Internal Data memory
The Data memory of SM89T16R1 consists of 1280 bytes internal data memory (256 bytes standard RAM and 1024
bytes AUX-RAM). The AUX-RAM is enable by SCONF.1 ($BF.1), and read/write by MOVX (Stretch=0, 2 machine
fixed)
Analog to Digital Converter (ADC)
The ADC Block Diagram Shown as below:
Those are only 4 pins mirror to Port 2[7:4] at Vin<3:0>. The Digital output DATA [7:0] were put into ADCD ($8FH).
And the ADC interrupt vector is 4BH.
The ADC SFR is shown as below:
ADSCR ($8EH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
COM
CON
ADCSS1
ADCSS0
CH1
CH0
COM: Read only. When conversion complete, it will be set.
CON: when set, the ADC will conversion continuous, else it will conversion only once.
ADCSS [1:0]: ADC clock select. (ADC_CLK range 500 KHz~2.5 MHz).If over frequency of ADC_CLK, the
conversion data may be unstable.
ADCSS1
0
0
1
1
ADCSS0
0
1
0
1
ADC_CLK
FOSC/4
FOSC/8
FOSC/16
FOSC/32
CH1
0
0
1
1
CH0
0
1
0
1
Input select
CH0
CH1
CH2
CH3
CH [1:0]: ADC channel select.
ADCD ($8FH)
Bit7
AD.5
Bit6
AD.4
Bit5
AD.3
Bit4
AD.2
Bit3
AD.1
Bit2
AD.0
Bit1
Bit0
Specifications subject to change without notice contact your sales representatives for the most recent information.
19
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
V D D (= V re f)
A D C SS1 A D C SS0 A D C _CLK
0
0
F o s c /4
0
1
F o s c /8
1
0
F o s c /1 6
1
1
F o s c /3 2
A D C_CLK
6
6 -b it S A R A D C
D A T A < 5 :0 >
{ A D C D [7 :2 ]}
A D C S S [1 :0 ]= { A D S C R [5 :4 ]}
V A I N < 3 : 0 > { P 2 .4 ~ P 2 .7 }
C H < 2 :0 > { A D S C R [3 :2 ]}
4
3
C o m p le te
{ A D S C R .7 }
C o n t i n u o u s { A D S C R .6 }
V SS
Figure 16 ADC Block Diagram
Dual UART
Serial Port in the SM89T16R1 is a full duplex port. The SM89T16R1 provides the user with additional features such
as the Frame Error Detection and the Automatic Address Recognition. The serial ports are capable of synchronous as
well as asynchronous communication. In Synchronous mode the SM89T16R1 generates the clock and operates in a
half duplex mode. In the asynchronous mode, full duplex operation is available. This means that it can simultaneously
transmit and receive data. The transmit register and the receive buffer are both addressed as SBUF Special Function
Register. However any write to SBUF will be to the transmit register, while a read from the receive buffer register.
The serial port can operate in four different modes as described below.
Mode 0
This mode provides synchronous communication with external devices. In this mode serial data is transmitted and
received on the RxD line. TxD is used to transmit the shift clock. The TxD clock is provided by the SM89T16R1
whether the device is transmitting or receiving. This mode is therefore a half duplex mode of serial communication. In
this mode, 8 bits are transmitted or received per frame. The LSB is transmitted / received first. The baud rate is fixed
at 1/12 or 1/4 of the oscillator frequency. This baud rate is determined at the SM2 bit (SCON.5). When this bit is set to
0, then the serial port runs at 1/12 of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional
facility of programmable baud rate in mode 0 is the only difference between the standard 8051 and the SM89T16R1.
The function block diagram is shown below. Data enters and leaves the Serial port on the RxD line. The TxD line is
used to output the shift clock. The shift clock is used to shift data into and out of the SM89T16R1 and the device at
the other end of the line. Any instruction that causes a write to SBUF will start the transmission. The shift clock will
be activated and data will shifted out on the RxD pin till all 8 bits are transmitted. If SM2 = 1, then the data on RxD
will appear 1 clock period before the falling edge of shift clock on TxD. The clock on TxD then remains low for 2
clock periods, and then goes high again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling
edge of shift clock on TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again. This
ensures that at the receiving end the data on RxD line can either be clocked on the rising edge of the shift clock on
TxD or latched when the TxD clock is low.
The TI flag is set high following the end of transmission of the last bit. The serial port will receive data when REN is
1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch data on the rising edge of the
shift clock. The external device should therefore present data on the falling edge on the shift clock. This process
continues till all the 8 bits have been received. The RI flag is set following the last rising edge of the shift clock on
TxD. This will stop reception, till the RI is cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
20
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Serial Port Mode 0:
Clock Source
Mode
Input
1/4
osc/1
1/64
osc/16
1/1024 osc/256
Internal
Data Bus
PARIN
RxD
P3.0 Alternate
Input function
SOUT
LOAD
Write to
SBUF
CLOCK
Transmit Shift Register
TX START
1/12
TX SHIFT
1/4
SM2
TI
TX CLOCK
0
1
Serial Port Interrupt
Serial Control
RI
TxD
P3.1 Alternate
Input function
SHIFT CLOCK
RX CLOCK
LOAD SBUF
/RI
RX START
RX SHIFT
REN
CLOCK
PAROUT
RxD
P3.0 Alternate
Input function
READ SBUF
SBUF
SBUF
SIN
Internal
Data Bus
Receive Shift Register
Mode 1
In mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of 10 bits
transmitted on TxD and received on RxD. The 10 bits consist of a start bit (0), 8 data bits (LSB first), and a stop bit
(1). On receive; the stop bit goes into RB8 in the SFR SCON. The baud rate in this mode is variable. The serial baud
can be programmed to be 1/16 or 1/32 of the Timer 1 overflow. Since the Timer 1 can be set to different reload values,
a wide variation in baud rates is possible.
Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin following the first rollover of
divide by 16 counter. The next bit is placed on TxD pin following the next rollover of the divide by 16 counter. Thus
the transmission is synchronized to the divide by 16 counter and not directly to the write to SBUF signal. After all 8
bits of data are transmitted the stop bit is transmitted. The TI flag is set after the stop bit has been put out on TxD pin.
This will be at the 10th rollover of the divide by 16 counter after a write to SBUF.
Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data, with the detection
of the falling edge on the RxD pin; the 1-to-0 detector continuously monitors the RxD line, sampling it at the rate of
16 times the selected baud rate. When a falling edge is detected, the divide by 16 counter is immediately reset. This
helps to align the bit boundaries with the rollovers of the divide by 16 counter.
The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a best of three
bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By using a majority 2 or 3 voting
system, the bit value is selected. This is done to improve the noise rejection feature of the serial port. If the first bit
detected after the falling edge of RxD pin is not 0, then this indicates an invalid start bit, and the reception is
immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is detected, then
the rest of the bits are also detected and shifted into the SBUF.
After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded and RI is set.
However certain conditions must be met before the loading and setting of RI can be done.
RI must be 0 and Either SM2 = 0, or the received stop bit = 1.
If these conditions are met, then the stop bit goes to RB8; the 8 data bits go into SBUF and RI is set. Otherwise the
received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition
on the RxD pin.
Specifications subject to change without notice contact your sales representatives for the most recent information.
21
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Serial Port Mode 1:
Timer 1
Overflow
Timer 2 Overflow
(for Serial Port 0 only)
1/2
SMOD=
(SMOD 1) 0
STOP
Internal
Data Bus
Write to
SBUF
1
PARIN
START
RxD
P3.0 Alternate
Input function
SOUT
LOAD
CLOCK
TCLK
1
1/16
TX START
TX CLOCK
Transmit Shift Register
TX SHIFT
TI
Serial Port Interrupt
RCLK
0
1
1/16
Serial Control
TxD
P3.1 Alternate
Input function
SHIFT CLOCK
LOAD SBUF
SAMPLE
1- To-0
Detector
RxD
P3.0 Alternate
Input function
RI
RX CLOCK
RX SHIFT
READ SBUF
SBUF
RX START
CLOCK
PAROUT
Bit
Detector
SIN
SBUF
D8
Internal
Data Bus
RB8
Receive Shift Register
Mode 2
This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional description is shown in
the figure below. The frame consists of one start bit (0), 8 data bits (LSB first), a programmable 9th bit (TB8) and a
stop bit (0). The 9th bit received is put into RB8. The baud rate is programmable to 1/32 or 1/64 of the oscillator
frequency, which is determined by the SMOD bit in PCON SFR. Transmission begins with a write to SBUF. The
serial data is brought out on to TxD pin following the first rollover of the divide by 16 counter. Thus the transmission
is synchronized to the divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are
transmitted the stop bit is transmitted. The TI flag is set after the stop bit has been put out on TxD pin. This will be at
the 11th rollover of the divide by 16 counter after a write to SBUF. Reception is enabled only if REN is high. The
serial port actually starts the receiving of serial data, with the detection of a falling edge on the RxD pin. The 1-to-0
detector continuously monitors the RxD line, sampling it at the rate of 16 times the selected baud rate. When a falling
edge is detected, the divide by 16 counter is immediately reset. This helps to align the bit boundaries with the
rollovers of the divide by 16 counter. The 16 states of the counter effectively divide the bit time into 16 slices. The bit
detection is done on a best of three bases. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states.
By using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise rejection feature
of the serial port.
If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit, and the
reception is immediately aborted. The serial port again looks for a falling edge in the RxD line. If a valid start bit is
detected, then the rest of the bits are also detected and shifted into the SBUF. After shifting in 9 data bits, there is one
more shift to do, after which the SBUF and RB8 are loaded and RI is set. However certain conditions must be met
before the loading and setting of RI can be done.
RI must be 0 and Either SM2 = 0, or the received 9th bit = 1.
If these conditions are met, then the 9th bit goes to RB8, the 8 data bits go into SBUF and RI is set. Otherwise the
received frame may be lost. After the middle of the stop bit, the receiver goes back to looking for a 1-to-0 transition
on the RxD pin.
Specifications subject to change without notice contact your sales representatives for the most recent information.
22
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Serial Port Mode 2:
Clock Source
Mode
Input
1/4
osc/2
1/64
osc/32
1/1024 osc/512
TB8
STOP
Internal
Data Bus
PARIN
1
1/16
1/16
RxD
P3.0 Alternate
Input function
SOUT
START
Write to
SBUF
1/2
SMOD=
(SMOD 1) 0
D8
LOAD
TX START
TX CLOCK
CLOCK
Transmit Shift Register
TX SHIFT
TI
Serial Control
Serial Port Interrupt
RI
TxD
P3.1 Alternate
Input function
SHIFT CLOCK
LOAD SBUF
SAMPLE
RX CLOCK
1- To-0
Detector
RX SHIFT
READ SBUF
SBUF
RX START
CLOCK
PAROUT
Bit
Detector
RxD
P3.0 Alternate
Input function
SIN
Internal
Data Bus
SBUF
D8
RB8
Receive Shift Register
Mode 3
This mode is similar to Mode 2 in all respects; expect that the baud rate is programmable. The user must first initialize
the Serial related SFR SCON before any communication can take place. This involves selection of the Mode and
Baud rate. The Timer 1 should also be initialized if modes 1 and 3 are used. In all four modes, transmission is started
by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0
and REN = 0. This will generate a clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in
the other modes by the incoming start bit if REN = 1. The external device will start the communication by
transmitting the start bit.
Pulse Width Modulation (PWM)
The PWM output pins are P1.4 and P1.5.
The PWM clock is {Fosc/ (2xDivider)}, the PWM output frequency is {(PWM clock)/32} at 5 bits resolution and
{(PWM clock)/256} at 8 bits resolution.
The PWM SFR is shown as below:
PWMC ($D3H and $D4H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
PBS
Bit1
PFS1
Bit0
PFS0
PBS: when set, the PWM is 5 bits resolution.
PFS [1:0]: The PWM clock divider select.
PFS1
0
0
1
1
PFS0
0
1
0
1
PWM clock divider select
1
2
4
8
Specifications subject to change without notice contact your sales representatives for the most recent information.
23
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
PWMD ($B3H and $B4H)
Bit7
PWMD.7
Bit6
PWMD.6
Bit5
PWMD.5
Bit4
PWMD.4
Bit3
PWMD.3
Bit2
PWMD.2
Bit1
PWMD.1
Bit0
PWMD.0
Real Time Clock (RTC)
The on-chip RTC keeps time of second and minute functions. Its time base is a 32.768 KHz crystal between pins
X32OUT (alternate function of ALE) and X32IN (alternate function of PSEN). The RTC maintains time to a second.
It also allows a user to read or write values of seconds and minute.
The RTC function used SFR descriptor as below:
RTCS ($A1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RTCen
Stable
SEC.5
SEC.4
SEC.3
SEC.2
SEC.1
SEC.0
RTCen: When set to ‘1’, enable the enable RTC function. When this bit set, the ALE and PSEN pins output will
disable, and the ALE and PSEN pins will use for RTC function as X32OUT and X32IN.
Stable: Read only. The Stable bit will set to 1 when the RTC module stable. Please wait 2 seconds before used the
RTC function.
SEC [5:0]: show the current second counter at RTC function. The range is from 00H to 3BH.
RTCC ($A2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
INT_SEL1
INT_SEL0
MIN.5
MIN.4
MIN.3
MIN.2
MIN.1
INT_SEL [1:0]: the interrupt distribution selection bit, the interrupt vector is 43H.
00: the interrupt is set as 0.5 second
01: the interrupt is set as 1 second
10: the interrupt is set as 30 second
11: the interrupt is set as 60 second
MIN [5:0]: show the current minute counter at RTC function. The range is from 00H to 3BH.
Bit0
MIN.0
Starting and stopping the RTC:
RTCS ($A1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RTCen
Stable
SEC.5
SEC.4
SEC.3
SEC.2
SEC.1
SEC.0
The RTC Function is enable by set the RTCS.7 (RTCen=1), then the ALE and /PSEN pins will switch to X32OUT
and X32IN that for RTC function used, the ALE and PSEN signal output will disable; the crystal frequency is
32768Hz. See figure 17.
SW 1
R
1
2
J1
1
1
2
3 2 7 6 8 H z C lo c k in
RTCen
X 3 2 in (/P S E N )
Y1
32768Hz
J2
1
In C h ip
X 3 2 o u t(A L E )
Figure 17 The RTC Crystal connect diagram
The stable bit (RTCS.6) will set to 1 when the RTC module stable. The design is about 31.25msec; suggest waiting 2
Specifications subject to change without notice contact your sales representatives for the most recent information.
24
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
second to use the RTC function. This bit will clear when RTCen bit set again.
The SEC [5:0] will show the second counter (range from 00H to 3BH), and the MIN [5:0] will show the minute
counter (range from 00H to 3BH) of RTC function. This two register will clear when RTCen bit set.
Interrupt:
The RTC can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. The interrupt vector
is 43H, it’s can wake-up CPU from POWER-DOWN mode.
The Interrupt functions are test at each test item. Like the int0 to int5 are test in PDWU function, the RTC
interrupt are test at RTC function test, the ADC interrupt are test at ADC function test.
This test item is focus in the priority test and only checks the lower voltage by each crystal.
The interrupt SFRs show as below:
IE1 ($A9H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EADC
ERTC
ERTC: When set to ‘1’, enable the RTC interrupt. If you want to use the RTC interrupt function, must enable the EA
bit in IE.7 and enable the ERTC bit in IE1.2.
EADC: When set to ‘1’, enable the ADC interrupt. If you want to use the ADC interrupt function, must enable the EA
bit in IE.7 and enable the EADC bit in IE1.3
RTCC ($A2H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INT_SEL1
INT_SEL0
MIN.5
MIN.4
MIN.3
MIN.2
MIN.1
MIN.0
Then select the interrupt distribution in INT_SEL [1:0] in RTCC [7:6].
The RTC can select each of 4 interrupt sources: 0.5 second, 1 second, 0.5 minute, and 1 minute. The interrupt vector
is 43H, it can wake-up CPU from POWER-DOWN mode.
IFR ($AAH)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADCIF
RTCIF
ADCIF: When interrupt occupy the ADC interrupt flag (IFR.3) will set, and the CPU will execute the interrupt
subroutine at the interrupt vector 4BH. The ADC Interrupt Flag must clear by software.
RTCIF: When interrupt occupy the RTC interrupt flag (IFR.2) will set, and the CPU will execute the interrupt
subroutine at the interrupt vector 43H. The RTC Interrupt Flag must clear by software.
Bit6
Bit5
Bit4
IP1 ($B9H)
Bit7
Bit3
PADC
Bit2
PRTC
Bit1
Bit0
The interrupt priority can be set at IP1.2 or IP1.3.
PADC: When set to ‘1’, enable the ADC interrupt priority.
PRTC: When set to ‘1’, enable the RTC interrupt priority.
Specifications subject to change without notice contact your sales representatives for the most recent information.
25
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
U2
int 0.5sec
int 1sec
Divider 16384
Divider 2
int 0.5min
Divider 30
Divider 2
4
3
2
1
15
14
13
12
int 1min
32768Hz Clock in
<Value>
<Value>
<Value>
<Value>
int sel0
int sel1
RTCen
11
10
9
7
D0
D1
D2
D3
D4
D5
D6
D7
Y
Y
5
6
int out
A
B
C
G
74151
5 bits shif register
5 bits shif register
sec0
sec1
sec2
second register sec3
sec4
sec5
min0
min1
min2
minute register min3
min4
min5
<Value>
<Value>
Figure 18 The RTC Block Diagram
LED Driving Capability Control
This function is set the sink current more then 10mA for each pin, 26mA for whole Port 0, 15mA for whole Port 1 or
whole Port2 or whole Port3 or whole Port4, and total 71mA for whole chip.
The SFR shown as below:
Port Name
Port0
Port1
Port2
Port3
Port4
SFR Address
$92H
$93H
$94H
$95H
$96H
Iol(max) of pre port
26 mA
15 mA
15 mA
15 mA
15 mA
Power Saving Mode
The SM89T16R1 has several features that help the user to control the power consumption of the device. The
powers saving features are basically the Power Down mode, Economy mode and the Idle mode of
operation.
Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the idle bit is the
last instruction that will be executed before the device goes into Idle Mode. In the Idle Mode, the clock to the CPU is
halted, but not to the Interrupt, Timer and Serial port blocks. This forces the CPU state to be frozen; the Program
counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The
ALE and PSEN pins are held high during the idle state. The port pins hold the logical states they had at the time idle
was activated. The idle mode can be terminated in two ways. Since the interrupt controller is still active, the activation
of any enabled interrupt can wake up the processor. This will automatically clear the idle bit, terminate the idle mode,
and the Interrupt Service Routine (ISR) will be executed. After the ISR, execution of the program will continue from
the instruction that put the device into idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either applying a high on the
external RST pin or a Power on reset condition. The external reset pin has to be held high for at least two machine
cycles to be recognized as a valid reset. In the reset condition the program counter is reset to 0000H and all the SFRs
are set to the reset condition. Since the clock is already running there is no delay and execution start immediately.
When the SM89T16R1 is exiting from an idle mode with a reset, the instruction following the one that put the device
into idle mode is not executed. So there is no danger of unexpected writes.
Specifications subject to change without notice contact your sales representatives for the most recent information.
26
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
The Power Down Wake Up (PDWU) function
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the
last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the
clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is
reduced to the lowest possible value. In this state the ALE and PSEN pins are pulled low. The port pins output the
values held by their respective SFRs.
The SM89T16R1 will exit the Power Down mode with a reset or by a RTC (Real Time Clock) interrupt or by an
external interrupts pin enabled as level detects.
1. An external reset can be used to exit the Power Down state. The high on RST pin terminates the Power Down mode,
and restarts the clock. The program execution will restart from 0000H.
2. An external interrupt pin and RTC interrupt can be used to exit the Power Down state when the external interrupt or
RTC interrupt actives and provided the corresponding interrupt is enabled, while the global enable (EA) bit is set and
the external input has been set to a level detect mode or RTC interrupt set. If these conditions are met, then the low
level on the external pin or RTC interrupt re-starts the oscillator. Then device executes the interrupt service routine for
the corresponding external interrupt or RTC interrupt. After the interrupt service routine is completed, the program
execution returns to the instruction after the one that put the device into Power Down mode and continues from there.
The status of external pins during Idle and Power Down:
Mode
Program
Memory
Internal
External
Internal
External
Idle
Idle
Power Down
Power Down
ALE
/PSEN
PORT0
PORT1
PORT2
PORT3
PORT4
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
PCON ($87H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
SMOD
SMOD0
SMOD: This bit set to ‘1’ to make the UART baud-rate double.
SMOD0: This bit define the SCON.7 and SCON1.7 use as FE (FE1) or SM0 (SM0_1)
PD: When set to ‘1’, the MCU will into Power Down mode
IDLE: When set to ‘1’, the MCU will into IDLE mode
Bit1
PD
Bit0
IDLE
IE ($A8H)
Bit7
Bit6
Bit5
Bit4
EA
ES1
ET2
ES0
EA: When set to ‘1’, enable interrupt global.
ES1: When set to ‘1’, enable UART1 interrupt.
ET2: When set to ‘1’, enable Timer2 interrupt.
ES0: When set to ‘1’, enable UART interrupt.
ET1: When set to ‘1’, enable Timer1 interrupt.
EX1: When set to ‘1’, enable external interrupt 1.
ET0: When set to ‘1’, enable Timer0 interrupt.
EX0: When set to ‘1’, enable external interrupt 0.
Bit3
ET1
Bit2
EX1
Bit1
ET0
Bit0
EX0
Bit3
PT1
Bit2
PX1
Bit1
PT0
Bit0
PX0
IP ($B8H)
Bit7
Bit6
Bit5
PT2
Bit4
PS0
PT2: Timer2 interrupt priority.
PS0: UART interrupts priority.
Specifications subject to change without notice contact your sales representatives for the most recent information.
27
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
PT1: Timer1 interrupt priority.
PX1: external interrupt 1 priority.
PT0: Timer0 interrupt priority.
PX0: external interrupt 0 priority.
EIP ($BAH)
Bit7
Bit6
Bit5
Bit4
Bit3
PX5
Bit2
PX4
Bit1
PX3
Bit0
PX2
Bit3
EX5
Bit2
EX4
Bit1
EX3
Bit0
EX2
Bit3
IE1
Bit2
IT1
Bit1
IE0
Bit0
IT0
Bit5
Bit4
Bit3
Bit2
Bit1
T2M
T1M
T0M
MD2
MD1
T2M: Timer 2 clock select. When “1” used divide by 4 clock; when “0” used divide by 12 clock.
T1M: Timer 1 clock select. When “1” used divide by 4 clock; when “0” used divide by 12 clock.
T0M: Timer 0 clock select. When “1” used divide by 4 clock; when “0” used divide by 12 clock.
MD [2:0]: Stretch MOVX selects bits
Bit0
MD0
PX5: When set to ‘1’, external interrupt 5 priorities.
PX4: When set to ‘1’, external interrupt 4 priorities.
PX3: When set to ‘1’, external interrupt 3 priorities.
PX2: When set to ‘1’, external interrupt 2 priorities.
EIE ($ABH)
Bit7
Bit6
Bit5
Bit4
EX5: When set to ‘1’, enable external interrupt 5.
EX4: When set to ‘1’, enable external interrupt 4.
EX3: When set to ‘1’, enable external interrupt 3.
EX2: When set to ‘1’, enable external interrupt 2.
TCON ($88H)
Bit7
Bit6
Bit5
TF1
TR1
TF0
TF1: Timer 1 overflow flag.
TR1: Timer 1 run control bit.
TF0: Timer 0 overflow flag.
TR0: Timer 0 run control bit.
IE1: External Interrupt 1 edge flag.
IT1: Interrupt 1 type control bit.
IE0: External Interrupt 0 edge flag.
IT0: Interrupt 0 type control bit.
Bit4
TR0
CKCON ($8EH)
Bit7
MD2
0
0
0
0
1
1
1
1
Bit6
MD1
0
0
1
1
0
0
1
1
MD0
0
1
0
1
0
1
0
1
Stretch Value
0
1
2
3
4
5
6
7
MOVX duration
2 machine cycles
3 machine cycles (Default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
Specifications subject to change without notice contact your sales representatives for the most recent information.
28
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Dual DPTR Function
The DPS.0 define the instruction of INC DPTR AND DEC DPTR are working in DPTR0 or DPTR1.
DPS ($A6H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DPS
DPS = 1 the instruction of INC DPTR and DEC DPTR are working in DPTR1.
= 0 the instruction of INC DPTR and DEC DPTR are working in DPTR0.
DPH ($83H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DPL ($82H)
Bit7
DPH1 ($A5H)
Bit7
DPL1 ($A4H)
Bit7
Data SRAM
The SCONF.1 must set to ‘1’ to enable the Expand 1024 bytes RAM, and this Expand RAM area must read/write by
using the MOVX instruction.
SCONF ($BFH)
Bit7
Bit6
Bit5
Bit4
Bit3
SMOD_1
PDWUE
SMOD_1: This bit set to ‘1’ to make the serial port 1 baud-rate double.
PDWUE: When set to ‘1’, enable the PDWU function.
OME: When set to ‘1’, enable the 1024 bytes expanded RAM.
ALEI: When set to ‘1’, it will stop ALE clock output for EMI reduce.
Bit2
Bit1
OME
Bit0
ALEI
Power Management Mode (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run
software but to use substantially less power. Normally, during default operation, the SM89T16R1 uses 4 clocks per
machine cycle. Thus the instruction cycle (machine cycle clock) rate is clock/4. At 16 MHz crystal speed, the
instruction cycle speed is 4 MHz. In Power Management Mode (PMM) the instruction cycle (machine cycle clock)
rate is clock/1024. At same 16 MHz crystal speed, the instruction cycle speed is 15.6 KHz. The operation current is
down from 20mA to 5mA. See Table 5.
Crystal Speed
11.0592 MHz
16 MHz
25 MHz
Table 5
Full Operation (4 clocks/machine cycle)
Instruction rate/operation current
2.765 MHz/19.6 mA
4.0 MHz/20 mA
6.25 MHz/30 mA
PMM (1024 clocks/machine cycle)
Instruction rate/operation current
10.8 KHz/4.78 mA
15.6 kHZ/5 mA
24.4 kHz/5.6 mA
Specifications subject to change without notice contact your sales representatives for the most recent information.
29
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Economy Mode
The power consumption of microcontroller relates to operating frequency. The SM89T16R1 offers an Economy mode
to reduce the internal clock rate dynamically without external components. By default, one machine cycle needs 4
clocks. In Economy mode, software can select 4, 64, or 1024 clocks per machine cycle. It keeps the CPU operating a
acceptable speed but eliminates the power consumption. In the Idle mode, the clock of the core logic is stopped, but
all clocked peripherals such as timer are still running at a rate of clock/4. In the Economy mode, all clocks peripherals
run at the same reduced clocks rate as in core logic. So the Economy mode may provide lower power consumption
than Idle mode.
Software invokes the Economy mode by setting the appropriate bits in the SFRs. Setting the bits CD0 (PMR.6), CD1
(PMR.7) decides the instruction cycle rate as below:
PMR ($D1H)
Bit7
CD1
Bit6
CD0
Bit5
CD1
0
0
1
1
Bit4
CD0
0
1
0
1
Bit3
XTOFF
Bit2
Bit1
Bit0
Clocks/machine cycle
Reserved
4
64
1024
Change Clock
Test Internal RC oscillator and External crystal switching
EXIF ($91H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IE5
IE4
IE3
IE2
XT/~RG
IE5: When set to ‘1’, external interrupt 5 flag.
IE4: When set to ‘1’, external interrupt 4 flag.
IE3: When set to ‘1’, external interrupt 3 flag.
IE2: When set to ‘1’, external interrupt 2 flag.
XT/~RG: When set to ‘1’, the MCU used External Crystal.
When clear to ‘0’, the MCU used Internal RC Oscillator
This selection of instruction rate is going to take effect after a delay of one instruction cycle. Switching to divide by
64 or 1024 mode must first go from divide by 4 modes. This means software cannot switch directly between clock/64
and clock/1024 mode. The CPU has to return clock/4 mode first, then go to clock/64 or clock/1024 mode.
The SM89T16R1 allows the user to use internal RC oscillator instead of external crystal. Setting the XT/~RG bit
(EXIF.3) selects the crystal or RC oscillator as the clock source. When invoking RC oscillator in Economy mode,
software may set the XTOFF bit to turn off the crystal amplifier for saving power. The CPU would run at the clock
rate of approximately 2-4 MHz divided by 4, 64 or 1024. The RC oscillator is not precise so that cannot be invoked to
the operation that needs the accurate time-base such as serial communication. If crystal amplifier is disabled and RC
oscillator is present clock source, software must first clear the XTOFF bit to turn on crystal amplifier before switch to
crystal operation.
PMR ($D1H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
CD1
CD0
XTOFF
XTOFF: External Crystal off; if the XT/~RG bit set to 1, this bit (XTOFF) don’t care.
Bit1
Bit0
Specifications subject to change without notice contact your sales representatives for the most recent information.
30
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
Internal Clock Source
XT/~RG
XTOFF
0
0
Internal RC Oscillator
0
1
Internal RC Oscillator(Ext-Crystal OFF)
1
0
External Crystal
1
1
External Crystal
The Priority structure and vector locations of interrupts:
Source
External interrupt 0
Timer 0 overflow
External interrupt 1
Timer 1 overflow
UART interrupt
Timer 2 overflow
UART 1 interrupt
RTC interrupt
ADC interrupt
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
Flag
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
RI_1+TI_1
RTCIF
ADCIF
IE2
IE3
IE4
IE5
Priority level
1(highest)
2
3
4
5
6
7
8
9
10
11
12
13(lowest)
Vector Address
03H
0BH
13H
1BH
23H
2BH
33H
43H
4BH
5BH
63H
6BH
73H
T2MOD ($C9H)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HC5
HC4
HC3
HC2
T2CR
T2OE
DCEN
HC5: Hardware Clear /INT5 flag
HC4: Hardware Clear /INT4 flag
HC3: Hardware Clear /INT3 flag
HC2: Hardware Clear /INT2 flag
T2CR: Timer 2 Capture Reset. In the Timer2 Capture Mode this bit enables/disables hardware automatically reset
Timer2 while the value in TL2 and TH2 have been transferred into the capture register.
T2OE: Timer2 clock Output Enable bit. If set to 1, the Timer2 clock will output to P1.0.
DCEN: Down Count Enable. When set this bit then allows Timer2 to be configured as an up/down counter.
Application Reference
X'tal
C1
C2
R
3MHz
30 pF
30 pF
open
Valid for SM89T16R1
6MHz
9MHz
30 pF
30 pF
30 pF
30 pF
open
open
XI
12MHz
22 pF
22 pF
open
X'tal
SM89T16R1
R
X2
X'tal
16MHz
25MHz
C1
C2
C1
30 pF
15 pF
C2
30 pF
15 pF
R
open
open
Note:
Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
Specifications subject to change without notice contact your sales representatives for the most recent information.
31
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
PDIP 40L (600mil) Package Information：
Symbol
Note:
1. Refer to JEDEC STD.MS-011(AC).
2. Dimension D and E1 do not include
mold protrusion. Allowable protrusion is
0.25 mm per side. D and E1 are
maximum plastic body size dimension
include mold mismatch.
3. Dimension b3 does not include dambar
protrusion. Allowable dambar protrusion
shall not cause the lead width to exceed
the maximum b3 dimension by more than
0.2mm.
Dimension in mm
Dimension in MIL
Min
Nom
Max
Min
Nom
Max
A1
0.254
－
－
10
－
－
A2
3.683
3.810
3.937
145
150
155
b
0.356
0.500
0.660
14
20
26
b1
0.356
0.457
0.508
14
18
22
b2
1.016
1.270
1.524
40
50
60
b3
1.016
1.321
1.626
40
52
64
c
0.203
0.254
0.432
8
10
17
c1
0.203
0.254
0.356
8
10
14
D
52.07
52.2
52.32
2050
2055
2060
E
14.99
15.24
15.49
590
600
610
E1
13.69
13.87
13.94
539
546
549
－
2.540
－
－
100
－
eB
15.75
16.26
16.76
620
640
660
L
2.921
3.302
3.683
115
130
145
S
1.727
1.981
2.235
68
78
88
Q1
1.651
1.778
1.905
65
70
75
0°
－
10°
0°
－
10°
e
θ
Specifications subject to change without notice contact your sales representatives for the most recent information.
32
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
PLCC 44L Package Information：
UNIT
SYMBOL
A
A1
A2
B
B1
c
D
D1
D2
E
E1
E2
e
y
θ
INCH(REF)
MM(BASE)
0.180(MAX)
0.024 ±0.005
0.105 ±0.005
0.018 + 0.004
- 0.002
0.028 + 0.004
- 0.002
0.010(TYP)
4.572(MAX)
0.52 ±0.14
2.667 ±0.127
0.457 + 0.102
- 0.051
0.711 + 0.102
- 0.051
0.254(TYP)
0.690 ±0.010
17.526 ±0.254
0.653 ±0.003
16.586 ±0.076
0.610 ±0.020
15.494 ±0.508
0.690 ±0.010
17.526 ±0.254
0.653 ±0.003
16.586 ±0.076
0.610 ±0.010
15.494 ±0.254
0.050(TYP)
1.270(TYP)
0.003(MAX)
0.076(MAX)
0~5°
0~5°
Specifications subject to change without notice contact your sales representatives for the most recent information.
33
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
QFP 44L(10x10x2.0mm) Package Information：
Symbol
Note:
1. Refer to JEDC STD.MS-022(AB).
2. Dimension E1 do not include mold protrusion.
Allowable protrusion is 0.25mm per side.E1 are
maximum plastic body size dimension include
mold mismatch .
3. Dimension b does not include dambar
protrusion .Allowable dambar protrusion shall not
cause the lead width to exceed the maximum b3
dimension by more than 0.1 mm.
Dimension in mm
Dimension in MIL
Min
Nom
Max
Min
Nom
Max
A
－
－
2.45
－
－
964
A1
0.05
0.15
0.25
2.1
6.0
9.6
A2
1.90
2.00
2.10
74.8
78.7
82.7
b
0.29
0.32
0.45
11.4
12.6
17.7
b1
0.29
0.30
0.41
11.4
11.8
16.1
c
0.11
0.17
0.23
4.3
6.7
9.1
c1
0.11
0.15
0.19
4.3
5.9
7.5
E
13.00
13.20
13.40
512
520
528
E1
9.90
10.00
10.10
390
394
398
【e】
－
0.800
－
－
31.5
－
L
0.73
0.88
1.03
28.7
34.6
40.6
L1
1.50
1.60
1.70
59.1
63.0
66.9
y
－
－
0.076
－
－
3
θ
0°
－
7°
0°
－
7°
Specifications subject to change without notice contact your sales representatives for the most recent information.
34
Ver 2.1 SM89T16R1 08/2006
SyncMOS Technologies International, Inc.
SM89T16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & Two UART & RTC & ADC & PWM embedded
e MCU writer list
Company
Advantech
7F, No.98, Ming-Chung Rd.,
Shin-Tien City, Taipei, Taiwan,
ROC
Web site:
http://www.aec.com.tw
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
Lab Tool - 48XP (1 * 1)
Lab Tool - 848 (1*8)
Hi-Lo
4F, No. 20, 22, LN, 76,
Rui Guang Rd., Nei Hu, Taipei,
Taiwan, ROC.
Web site:
http://www.hilosystems.com.tw
Tel:02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 11 (1*1)
Gang - 08 (1*8)
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung,
Taipei Hsien, Taiwan, ROC
Web site:
http://www.leap.com.tw
Tel:02-29991860
Fax:02-29990015
E-mail:
[email protected]
Leap-48 (1*1)
SU - 2000 (1*8)
Xeltek Electronic Co., Ltd
338 Hongwu Road, Nanjing, China
210002
Web site:
http://www.xeltek-cn.com
Tel:+86-25-84408399, 84543153-206
E-mail:
[email protected],
[email protected]
Superpro/2000 (1*1)
Superpro/280U (1*1)
Superpro/L+(1*1)
Specifications subject to change without notice contact your sales representatives for the most recent information.
35
Ver 2.1 SM89T16R1 08/2006