Hot Swap Controller and Digital Power and Energy Monitoring with PMBus Interface ADM1276 Controls supply voltages from 2 V to 20 V 370 ns response time to short circuit Resistor-programmable 5 mV to 25 mV current limit ±1% accurate, 12-bit ADC for current, VIN/VOUT readback Charge pumped gate drive for multiple external N-channel FETs High gate drive voltage to ensure lowest RDSON Foldback for tighter FET SOA protection Automatic retry or latch-off on current fault Programmable current-limit timer for SOA Programmable, multifunction GPO Power-good status output Analog UV and OV protection ENABLE pin Peak detect registers for current and voltage PMBus fast mode compliant interface 20-lead LFCSP APPLICATIONS FUNCTIONAL BLOCK DIAGRAM SENSE+ VCC VCAP ENABLE UV SENSE– ADM1276-3 + – ×50 IOUT + – – + 1.0V ISET VCP GATE DRIVE/ LOGIC 1.0V OV CHARGE PUMP LDO + – REF SELECT 1.0V TIMEOUT CURRENT LIMIT TIMER ON TIMER SENSE+ VOUT IOUT VOUT CURRENT LIMIT CONTROL SS TIMER GATE FLB TIMEOUT 12-BIT ADC LOGIC AND PMBus GND PWRGD GPO2/ALERT2 LATCH SCL SDA ADR 09718-001 FEATURES Figure 1. Power monitoring and control/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers GENERAL DESCRIPTION The ADM1276 is a hot swap controller that allows a circuit board to be removed from or inserted into a live backplane. It also features current and voltage readback via an integrated 12-bit analog-todigital converter (ADC), accessed using a PMBus™ interface. The load current is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the SENSE+ and SENSE− pins. A default limit of 20 mV is set, but this limit can be adjusted, if required, using a resistor divider network from the internal reference voltage to the ISET pin. The ADM1276 limits the current through the sense resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage—and, therefore, the load current—is maintained below the preset maximum. The ADM1276 protects the external FET by limiting the time that the FET remains on while the current is at its maximum value. This current-limit time is set by the choice of capacitor connected to the TIMER pin. In addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the FET is increased. This helps to maintain constant power in the FET and allows the safe operating area (SOA) to be adhered to in an effective manner. In case of a short-circuit event, a fast internal overcurrent detector responds within 370 ns and signals the gate to shut down. A 1500 mA pull-down device ensures a fast FET response. The ADM1276 features overvoltage (OV) and undervoltage (UV) protection, programmed using external resistor dividers on the UV and OV pins. A PWRGD signal can be used to detect when the output supply is valid, using the FLB pin to monitor the output. A GPO pin can be configured as an output signal that can be asserted when a programmed current or voltage level is reached. The 12-bit ADC can measure the current in the sense resistor, as well as the supply voltage on the SENSE+ pin or the output voltage. A PMBus interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by a PMBus command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever required. As many as four unique PMBus addresses can be selected, depending on the way that the ADR pin is connected. The ADM1276 is available in a 20-lead LFCSP and has a LATCH pin that can be configured for automatic retry or latch-off when an overcurrent fault occurs. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADM1276 TABLE OF CONTENTS Features .............................................................................................. 1 Power Monitor Commands ...................................................... 28 Applications....................................................................................... 1 Warning Limit Setup Commands ............................................ 29 Functional Block Diagram .............................................................. 1 PMBus Direct Format Conversion .......................................... 30 General Description ......................................................................... 1 Voltage and Current Conversion Using LSB Values.............. 32 Revision History ............................................................................... 3 GPO2/ALERT2 Pin Behavior ....................................................... 33 Specifications..................................................................................... 4 Faults and Warnings .................................................................. 33 Serial Bus Timing Characteristics .............................................. 7 Generating an Alert ................................................................... 33 Absolute Maximum Ratings............................................................ 8 Handling/Clearing an Alert ...................................................... 33 Thermal Characteristics .............................................................. 8 SMBus Alert Response Address ............................................... 33 ESD Caution.................................................................................. 8 Example Use of SMBus Alert Response Address ................... 34 Pin Configuration and Function Descriptions............................. 9 PMBus Command Reference........................................................ 35 Typical Performance Characteristics ........................................... 11 OPERATION .............................................................................. 36 Typical Application Circuit ........................................................... 17 CLEAR_FAULTS........................................................................ 36 Theory of Operation ...................................................................... 18 CAPABILITY.............................................................................. 36 Powering the ADM1276............................................................ 18 VOUT_OV_WARN_LIMIT..................................................... 36 Current Sense Inputs.................................................................. 18 VOUT_UV_WARN_LIMIT..................................................... 36 Current-Limit Reference ........................................................... 19 IOUT_OC_WARN_LIMIT ...................................................... 36 Setting the Current Limit (ISET) ............................................. 19 IOUT_WARN2_LIMIT............................................................. 36 Soft Start ...................................................................................... 20 VIN_OV_WARN_LIMIT ......................................................... 37 Foldback....................................................................................... 20 VIN_UV_WARN_LIMIT ......................................................... 37 Timer............................................................................................ 21 PIN_OP_WARN_LIMIT .......................................................... 37 Hot Swap Retry Duty Cycle ...................................................... 21 STATUS_BYTE .......................................................................... 37 FET Gate Drive Clamps............................................................. 21 STATUS_WORD........................................................................ 38 Fast Response to Severe Overcurrent ...................................... 22 STATUS_VOUT ......................................................................... 38 Undervoltage and Overvoltage................................................. 22 STATUS_IOUT .......................................................................... 38 ENABLE Input ............................................................................ 22 STATUS_INPUT........................................................................ 39 Power Good................................................................................. 22 STATUS_MFR_SPECIFIC........................................................ 39 VOUT Measurement ................................................................. 23 READ_EIN.................................................................................. 40 FET Health .................................................................................. 23 READ_VIN ................................................................................. 40 Power Monitor ............................................................................ 23 READ_VOUT............................................................................. 40 PMBus Interface ............................................................................. 24 READ_IOUT .............................................................................. 40 Device Addressing...................................................................... 24 READ_PIN.................................................................................. 40 SMBus Protocol Usage............................................................... 24 PMBUS_REVISION .................................................................. 40 Packet Error Checking............................................................... 24 MFR_ID....................................................................................... 41 SMBus Message Formats ........................................................... 25 MFR_MODEL ............................................................................ 41 Group Commands...................................................................... 26 MFR_REVISION........................................................................ 41 Hot Swap Control Commands ................................................. 27 PEAK_IOUT............................................................................... 41 ADM1276 Information Commands ........................................ 27 PEAK_VIN.................................................................................. 41 Status Commands....................................................................... 27 PEAK_VOUT ............................................................................. 42 GPO and Alert Pin Setup Commands..................................... 28 PMON_CONTROL ................................................................... 42 Rev. 0 | Page 2 of 48 ADM1276 PMON_CONFIG........................................................................42 READ_PIN_EXT ........................................................................44 ALERT2_CONFIG .....................................................................43 READ_EIN_EXT........................................................................44 DEVICE_CONFIG .....................................................................44 Outline Dimensions........................................................................45 POWER_CYCLE.........................................................................44 Ordering Guide ...........................................................................45 PEAK_PIN ...................................................................................44 REVISION HISTORY 3/11—Revision 0: Initial Version Rev. 0 | Page 3 of 48 ADM1276 SPECIFICATIONS VCC = 2.95 V to 20 V, VCC ≥ VSENSE+, VSENSE+ = 2 V to 20 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +85°C, unless otherwise noted. Table 1. Parameter POWER SUPPLY Operating Voltage Range Undervoltage Lockout Undervoltage Hysteresis Quiescent Current UV PIN Input Current UV Threshold UV Threshold Hysteresis UV Glitch Filter UV Propagation Delay OV PIN Input Current OV Threshold OV Threshold Hysteresis OV Glitch Filter OV Propagation Delay SENSE+ AND SENSE− PINS Input Current Input Imbalance VCAP PIN Internally Regulated Voltage ISET PIN Reference Select Threshold Internal Reference Gain of Current Sense Amplifier Input Current GATE PIN Gate Drive Voltage Gate Pull-Up Current Gate Pull-Down Current Regulation Slow Fast Gate Holdoff Resistance HOT SWAP SENSE VOLTAGE Hot Swap Sense Voltage Current Limit Foldback Inactive Symbol Min VCC 2.95 2.4 Typ 90 ICC IUV UVTH UVHYST UVGF UVPD 0.97 40 2 IOV OVTH OVHYST OVGF OVPD 0.97 50 0.5 1.0 50 5 1.0 60 1.0 ISENSEx IΔSENSE Max Unit Test Conditions/Comments 20 2.7 120 5 V V mV mA 100 1.03 60 7 8 nA V mV μs μs UV ≤ 3.6 V UV falling 100 1.03 70 1.5 2 nA V mV μs μs OV ≤ 3.6 V OV rising 150 5 μA μA Per individual pin; SENSE+, SENSE− = 20 V IΔSENSE = (ISENSE+) − (ISENSE−) VCC rising GATE on and power monitor running 50 mV overdrive UV low to GATE pull-down active 50 mV overdrive OV high to GATE pull-down active VVCAP 2.66 2.7 2.74 V 0 μA ≤ IVCAP ≤ 100 μA; CVCAP = 1 μF VISETRSTH VCLREF AVCSAMP 1.35 1.5 1 50 1.65 V V V/V If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used Accuracies included in total sense voltage accuracies Accuracies included in total sense voltage accuracies 100 nA IISET 10 4.5 8 4.5 −20 12 14 13 10 6 −30 V V V V μA VISET ≤ VVCAP Maximum voltage on the gate is always clamped to ≤31 V ΔVGATE = VGATE − VSENSE+ 17 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA 20 V ≥ VCC ≥ 17 V; IGATE ≤ 5 μA VSENSE+ = VCC = 5 V; IGATE ≤ 5 μA VSENSE+ = VCC = 2.95 V; IGATE ≤ 1 μA VGATE = 0 V 45 5 750 60 10 1500 20 75 15 2000 μA mA mA Ω VGATE ≥ 2 V; VISET = 1.0 V; (SENSE+) − (SENSE−) = 30 mV VGATE ≥ 2 V VGATE ≥ 12 V; VCC ≥ 12 V VCC = 0 V 19.6 20 20.4 mV 24.6 19.6 9.6 4.6 25 20 10 5 25.4 20.4 10.4 5.4 mV mV mV mV VISET > 1.65 V; VFLB > 1.12 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V VISET = 1.25 V; VFLB > 1.395 V VISET = 1.0 V; VFLB > 1.12 V VISET = 0.5 V; VFLB > 0.57 V VISET = 0.25 V; VFLB > 0.295 V ΔVGATE IGATEUP IGATEDN IGATEDN_REG IGATEDN_SLOW IGATEDN_FAST VSENSECL Rev. 0 | Page 4 of 48 ADM1276 Parameter Foldback Active Symbol Min 3.5 9.6 Typ 4 10 Max 4.5 10.4 Unit mV mV Circuit Breaker Offset SEVERE OVERCURRENT Voltage Threshold VCBOS 0.6 0.88 1.12 mV VSENSEOC 40 9.5 90 50 13.0 200 mV mV ns 530 900 ns 180 645 370 1020 ns ns 2 mV overdrive maximum severe overcurrent threshold −8 1.8 μA mV μA VSS = 0 V When VSENSE reaches this level, ISS is enabled, ramping VSENSECL; VSS = 0 V VSS = 1 V Short Glitch Filter Duration Long Glitch Filter Duration (Default) Response Time With Short Glitch Filter With Long Glitch Filter SOFT START (SS PIN) SS Pull-Up Current Default VSENSECL Limit SS Pull-Down Current TIMER PIN Timer Pull-Up Current Power-On Reset(POR) Overcurrent (OC) Fault Timer Pull-Down Current Retry Hold Timer Retry/OC Fault Current Ratio Timer High Threshold Timer Low Threshold FOLDBACK (FLB PIN) FLB and PWRGD Threshold Input Current Hysteresis Current Internal Hysteresis Voltage Power-Good Glitch Filter Minimum Foldback Clamp VOUT PIN Input Current LATCH PIN Output Low Voltage ISS −12 0.5 100 ITIMERUP ITIMERUPPOR ITIMERUPFLT ITIMERDNRT ITIMERDNHOLD VISET = 1.0 V; VFLB > 1.1 V; VSS ≥ 2 V VISET = 0.25 V; VFLB > 1.1 V; VSS ≥ 2 V VISET > 1.65 V; VSENSE driven from 18 mV to 52 mV; selectable via PMBus VSENSE driven from 18 mV to 52 mV −2 −57 −3 −60 −4 −63 μA μA Initial power-on reset; VTIMER = 0.5 V Overcurrent fault; 0.2 V ≤ VTIMER ≤ 1 V 1.7 2 100 3.33 2.3 3.8 μA μA % After fault when GATE is off; VTIMER = 0.5 V Holds TIMER at 0 V when inactive; VTIMER = 0.5 V Defines the limits of the autoretry duty cycle VTIMERH VTIMERL 0.98 0.18 1.0 0.2 1.02 0.22 V V VFLBTH IFLB 1.08 1.1 1.12 100 100 2.3 3.1 1 V nA nA μA mV μs mV FLB rising; VISET = 1.0 V VFLB ≤ 1.0 V; VISET = 1.25 V VVCAP ≤ VFLB ≤ 20 V 20 μA VOUT = 20 V 0.4 1.5 100 1 V V nA μA ILATCH = 1 mA ILATCH = 5 mA VLATCH ≤ 2 V; LATCH output high-Z VLATCH = 20 V; LATCH output high-Z 100 1 nA μA V V PWRGDGF 1.7 1.9 0.3 VOL_LATCH Leakage Current ENABLE PIN Leakage Current Input High Voltage Input Low Voltage −10 1.25 Test Conditions/Comments VFLB = 0 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 1 V VISET > 1.0 V; VFLB = 0.5 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 1 V Circuit breaker trip voltage, VCB = VSENSECL − VCBOS VIH VIL 0.7 200 1.1 0.8 Voltage drop across the internal 1.3 kΩ resistor 50 mV overdrive Accuracies included in total sense voltage accuracies No internal pull-up present on this pin VGPO2 ≤ 2 V VGPO2 = 20 V Rev. 0 | Page 5 of 48 ADM1276 Parameter GPO2/ALERT2 PIN Output Low Voltage Symbol Min Typ Max Unit Test Conditions/Comments VOL_GPO2 0.4 1.5 100 1 V V nA μA IGPO2 = 1 mA IGPO2 = 5 mA VGPO2 ≤ 2 V; GPO output high-Z VGPO2 = 20 V; GPO output high-Z VOL_PWRGD 0.4 1.5 V V V IPWRGD = 1 mA IPWRGD = 5 mA ISINK = 100 μA; VOL_PWRGD = 0.4 V 100 1 nA μA VPWRGD ≤ 2 V; PWRGD output high-Z VPWRGD = 20 V; PWRGD output high-Z ±0.75 ±0.8 ±1.1 ±2.0 ±4.3 ±1.0 % % % % % % % % % % % % % % % % % % % % 25 mV input range; 128 sample averaging (unless otherwise noted) VSENSE = 20 mV; VSENSE+ = 12 V; TA = 0°C to 65°C VSENSE = 20 mV; VSENSE+ = 12 V; TA = 25°C VSENSE = 20 mV VSENSE = 20 mV; TA = 25°C VSENSE = 20 mV; TA = 0°C to 65°C VSENSE = 20 mV; 16 sample averaging VSENSE = 20 mV; 16 sample averaging; TA = 25°C VSENSE = 20 mV; 16 sample averaging; TA = 0°C to 65°C VSENSE = 20 mV; 1 sample averaging VSENSE = 20 mV; 1 sample averaging; TA = 25°C VSENSE = 20 mV; 1 sample averaging; TA = 0°C to 65°C VSENSE = 25 mV; VSENSE+ = 12 V VSENSE = 25 mV; VSENSE+ = 12 V; TA = 25°C VSENSE = 25 mV; VSENSE+ = 12 V; TA = 0°C to 65°C VSENSE = 20 mV; VSENSE+ = 12 V VSENSE = 15 mV; VSENSE+ = 12 V VSENSE = 10 mV; VSENSE+ = 12 V VSENSE = 5 mV; VSENSE+ = 12 V VSENSE = 2.5 mV; VSENSE+ = 12 V Low input range; input voltage ≥ 3 V ±1.0 % 237 280 μs 360 426 μs 3753 4233 μs 5545 6570 μs Leakage Current PWRGD PIN Output Low Voltage VCC That Guarantees Valid Output Leakage Current 1 CURRENT AND VOLTAGE MONITORING Current Sense Absolute Error ±0.2 ±0.08 ±0.7 ±1.0 ±0.08 ±0.2 ±1.0 ±0.08 ±0.2 ±2.8 ±0.09 ±0.2 ±0.7 ±0.04 ±0.15 SENSE+/VOUT Absolute Error ADC Conversion Time Power Multiplication Time ADR PIN Address Set to 00 Input Current for Address 00 Address Set to 01 Address Set to 10 14 0 −40 135 −1 μs 0.8 −22 150 High input range; input voltage ≥ 10 V Includes time for power multiplication 1 sample of VIN and IOUT; from command received to valid data in register 1 sample of VIN, VOUT, and IOUT; from command received to valid data in register 16 samples of VIN and IOUT averaged; from command received to valid data in register 16 samples of VIN, VOUT, and IOUT averaged; from command received to valid data in register 165 +1 V μA kΩ μA Connect to GND VADR = 0 V to 0.8 V Resistor to GND No connect state; maximum leakage current allowed Rev. 0 | Page 6 of 48 ADM1276 Parameter Address Set to 11 Input Current for Address 11 SERIAL BUS DIGITAL INPUTS (SDA, SCL) Input High Voltage Input Low Voltage Output Low Voltage Input Leakage Symbol Min 2 VIH VIL VOL ILEAK-PIN Nominal Bus Voltage Capacitance for SDA, SCL Pins Input Glitch Filter Typ Max 3 10 Unit V μA 1.1 −10 −5 2.7 VDD CPIN 0.8 0.4 +10 +5 5.5 V V V μA μA V pF 50 ns 5 tSP 0 Test Conditions/Comments Connect to VCAP VADR = 2.0 V to VCAP; must not exceed the maximum allowable current draw from VCAP IOL = 4 mA Device is not powered 3 V to 5 V ± 10% SERIAL BUS TIMING CHARACTERISTICS Table 2. Parameter fSCLK tBUF Description Clock frequency Bus free time tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tR tF Start hold time Start setup time Stop setup time SDA hold time SDA setup time SCL low time SCL high time SCL, SDA rise time SCL, SDA fall time Min Typ Max 400 1.3 4.7 0.6 0.6 0.6 300 100 1.3 0.6 20 20 900 300 300 Unit kHz μs μs μs μs μs ns ns μs μs ns ns Test Conditions/Comments Following the stop condition of a read transaction Following the stop condition of a write transaction Timing Diagram tLOW VIL tHD;DAT tHD;STA SDA tF tHIGH tSU;STA tSU;DAT tSU;STO VIH VIL P tBUF S S Figure 2. Serial Bus Timing Diagram Rev. 0 | Page 7 of 48 P 09718-002 SCL tR VIH ADM1276 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter VCC Pin UV Pin OV Pin SS Pin TIMER Pin VCAP Pin ISET Pin LATCH Pin SCL Pin SDA Pin ADR Pin ENABLE Pin GPO2/ALERT2 Pin PWRGD Pin FLB Pin VOUT Pin GATE Pin (Internal Supply Only)1 SENSE+ Pin SENSE− Pin VSENSE (VSENSE+ − VSENSE−) Continuous Current into Any Pin Storage Temperature Range Operating Temperature Range Lead Temperature, Soldering (10 sec) Junction Temperature 1 Rating −0.3 V to +25 V −0.3 V to +4 V −0.3 V to +4 V −0.3 V to VCAP + 0.3 V −0.3 V to VCAP + 0.3 V −0.3 V to +4 V −0.3 V to VCAP + 0.3 V −0.3 V to +25 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to VCAP + 0.3 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +25 V −0.3 V to +36 V −0.3 V to +25 V −0.3 V to +25 V ±0.3 V ±10 mA −65°C to +125°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 20-lead LFCSP (CP-20-9) ESD CAUTION The GATE pin has internal clamping circuits to prevent the GATE pin voltage from exceeding the maximum ratings of a MOSFET with VGSMAX = 20 V and internal process limits. Applying a voltage source to this pin externally may cause irreversible damage. Rev. 0 | Page 8 of 48 θJA 30.4 Unit °C/W ADM1276 20 19 18 17 16 UV VCC SENSE+ SENSE– GATE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 PIN 1 INDICATOR ADM1275-3 TOP VIEW (Not to Scale) 15 GND 14 VOUT 13 FLB 12 PWRGD 11 SCL NOTES 1. SOLDER THE EXPOSED PADDLE TO THE BOARD TO IMPROVE THERMAL DISSIPATION. THE EXPOSED PADDLE CAN BE CONNECTED TO GROUND. 09718-003 LATCH 6 ADR 7 ENABLE 8 GPO2/ALERT2 9 SDA 10 OV VCAP ISET SS TIMER Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 19 Mnemonic VCC 20 UV 1 OV 2 VCAP 3 ISET 4 SS 5 TIMER 6 LATCH 7 ADR 8 ENABLE 9 GPO2/ALERT2 10 11 12 SDA SCL PWRGD 13 FLB 14 15 VOUT GND Description Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required. Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is under the UV limit. Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect whether the supply is above the OV limit. Internal Regulated Supply. Place a capacitor with a value of 1 μF or greater on this pin to maintain good accuracy. This pin can be used as a reference to program the ISET pin voltage. Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a resistor divider from VCAP. An external reference can also be used. Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls the current sense voltage limit, which controls the inrush current profile. Timer Pin. An external capacitor, CTIMER, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled low when the voltage on the TIMER pin exceeds the upper threshold. Latch Pin. This pin signals that the device is latching off after an overcurrent fault. The device can be configured for automatic retry after latch-off by connecting this pin directly to the UV or the ENABLE pin. PMBus Address Pin. This pin can be tied to GND, tied to VCAP, remain floating, or tied low through a resistor to set four different PMBus addresses (see the Device Addressing section). Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1276 hot swap controller to begin a power-up sequence. If this pin is held low, the ADM1276 is prevented from powering up. There is no internal pull-up on this pin. General-Purpose Digital Output/Alert. This is a dual function pin. There is no internal pull-up on this pin. The ALERT2 function of this pin can be configured to generate an alert signal when one or more fault or warning conditions are detected. At power-up, ALERT2 indicates the FET health mode by default. Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up. Serial Clock Pin. Open-drain input. Requires an external resistive pull-up. Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage present on the FLB pin. Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is not increased beyond the SOA limits. Output Voltage. This pin is used to read back the output voltage using the internal ADC. Ground Pin. Rev. 0 | Page 9 of 48 ADM1276 Pin No. 16 Mnemonic GATE 17 SENSE− 18 SENSE+ N/A 1 EP 1 Description Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is below UVLO. Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1276 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin. Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1276 controls the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin is also used to measure the supply input voltage using the ADC. Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground. N/A means not applicable. Rev. 0 | Page 10 of 48 ADM1276 TYPICAL PERFORMANCE CHARACTERISTICS 5 14 12 4 IGATEDN_SLOW (mA) +85°C +25°C ICC (mA) VCC = 12V 3 –40°C 2 10 8 6 4 1 4 6 8 10 12 14 16 18 20 VCC (V) 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 4. Supply Current (ICC) vs. Supply Voltage (VCC) 09718-007 2 09718-004 0 2 Figure 7. Gate Pull-Down Current (IGATEDN_SLOW) vs. Temperature 5 15 14 13 VCC = 20V 12 VCC = 12V 11 VCC = 2.95V IGATEDN_SLOW (mA) ICC (mA) 4 3 2 10 9 8 7 6 5 4 1 3 2 0 20 40 60 0 09718-005 –20 80 TEMPERATURE (°C) 0 5 10 15 20 25 VGATE (V) 09718-008 1 0 –40 Figure 8. Gate Pull-Down Current (IGATEDN_SLOW) vs. Gate Voltage (VGATE) Figure 5. Supply Current (ICC) vs. Temperature 0 14 –5 +25°C 10 –40°C –10 IGATEUP (µA) 8 +85°C 6 4 –20 –25 –30 2 –35 2 4 6 8 10 12 VCC (V) 14 16 18 20 09718-006 0 –15 Figure 6. Gate Pull-Down Current (IGATEDN_SLOW) vs. Supply Voltage (VCC) Rev. 0 | Page 11 of 48 –40 2 4 6 8 10 12 14 16 18 20 VCC (V) Figure 9. Gate Pull-Up Current (IGATEUP) vs. Supply Voltage (VCC) 09718-009 IGATEDN_SLOW (mA) 12 ADM1276 16 30 VCC = 12V 14 25 VCC = 2.95V 15 10 ∆VGATE (V) IGATEUP (µA) 20 +85°C +25°C 12 –40°C 8 6 10 4 5 10 15 20 25 VGATE (V) Figure 10. Gate Pull-Up Current (IGATEUP) vs. Gate Voltage (VGATE) 2 6 8 10 12 14 16 18 20 Figure 13. Gate Drive Voltage (ΔVGATE) vs. Supply Voltage (VCC), 5 μA Load 16 VCC = 12V 14 –10 12 –15 10 ∆VGATE (V) –5 –20 –25 VCC = 20V 6 4 –35 2 –20 0 20 40 60 80 TEMPERATURE (°C) VCC = 12V 8 –30 –40 –40 4 VCC (V) VCC = 2.95V 0 –40 09718-011 IGATEUP (µA) 0 0 09718-013 5 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 11. Gate Pull-Up Current (IGATEUP) vs. Temperature 09718-014 0 09718-010 0 2 Figure 14. Gate Drive Voltage (ΔVGATE) vs. Temperature, No Load 16 0 VCC = 12V –2 14 +85°C +25°C –4 12 –8 –40°C ISS (µA) ∆VGATE (V) –6 10 8 6 –10 –12 –14 4 –16 2 4 6 8 10 12 VCC (V) 14 16 18 20 Figure 12. Gate Drive Voltage (ΔVGATE) vs. Supply Voltage (VCC), No Load Rev. 0 | Page 12 of 48 –20 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 15. Soft Start Pull-Up Current (ISS) vs. Temperature 09718-015 2 09718-012 0 –18 ADM1276 0 1100 VCC = 12V HIGH THRESHOLD (VCC = 12V) 1000 –10 900 TIMER THRESHOLD (mV) –30 –40 –50 –60 800 700 600 500 400 300 LOW THRESHOLD (VCC = 12V) 200 –70 100 –20 0 20 40 60 80 TEMPERATURE (°C) 0 –40 09718-016 –80 –40 20 40 60 80 Figure 19. Timer Thresholds vs. Temperature 1.3 VCC = 12V 1.2 1.1 FOLDBACK THRESHOLD (V) –2 ITIMERUPPOR (µA) 0 TEMPERATURE (°C) Figure 16. Timer Pull-Up Current, Overcurrent Fault (ITIMERUPFLT) vs. Temperature 0 –20 09718-019 ITIMERUPFLT (µA) –20 –4 –6 –8 2.95V 12V 20V 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 20 40 60 80 TEMPERATURE (°C) 0 –40 FOLDBACK HYSTERESIS CURRENT (µA) 1.5 0 20 40 TEMPERATURE (°C) 60 80 60 80 80 2.5 2.0 2.95V 12V 20V 1.5 1.0 0.5 0 –40 09718-018 ITIMERDNRT (µA) 40 3.0 3.0 –20 20 Figure 20. Foldback Threshold vs. Temperature VCC = 12V 0 –40 0 TEMPERATURE (°C) Figure 17. Timer Pull-Up Current, Power-On Reset (ITIMERUPPOR) vs. Temperature 4.5 –20 09718-020 0 09718-017 –20 09718-021 0.1 –10 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 18. Timer Pull-Down Current, Retry (ITIMERDNRT) vs. Temperature Rev. 0 | Page 13 of 48 Figure 21. Foldback Hysteresis Current vs. Temperature ADM1276 220 1.8 200 1.6 180 1.4 140 120 100 80 +85°C +25°C 1.0 0.8 –40°C 0.6 60 40 0.4 20 0.2 0 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 0 30 +85°C 350 6 8 10 12 14 16 18 20 Figure 25. Circuit Breaker Offset (VCBOS) vs. Supply Voltage (VCC) 400 375 4 2 VCC (V) Figure 22. Foldback Clamp vs. Temperature VCC = 12V 25 325 300 +25°C 275 –40°C 250 VSENSECL (mV) OC RESPONSE TIME (ns) 1.2 09718-025 VCBOS (mV) 160 09718-022 FOLDBACK CLAMP (mV) 2.0 VCC = 12V 240 225 200 175 150 125 100 75 20 15 10 5 50 2 4 6 8 10 12 14 16 18 20 VCC (V) 0 –40 09718-023 Figure 23. Severe Overcurrent Response Time vs. Supply Voltage (VCC), VISET = 0.25 V 40 60 80 TA = 25°C 25 VSENSECL (mV) +85°C –40°C 20 15 10 5 2 4 6 8 10 12 VCC (V) 14 16 18 20 09718-024 OC RESPONSE TIME (ns) 275 250 225 200 175 150 125 100 75 50 25 0 20 Figure 26. Hot Swap Sense Voltage Current Limit (VSENSECL) vs. Temperature 30 +25°C 0 TEMPERATURE (°C) 400 375 350 325 300 –20 Figure 24. Severe Overcurrent Response Time vs. Supply Voltage (VCC), VISET = 1 V Rev. 0 | Page 14 of 48 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VFLB (V) Figure 27. Hot Swap Sense Voltage Current Limit (VSENSECL) vs. Foldback Voltage (VFLB) 09718-027 0 09718-026 25 ADM1276 20 50 45 40 15 VCC = 20V 30 ∆VGATE (V) VSENSEOC (mV) 35 25 20 VCC = 12V 10 VCC = 2.95V 15 5 TA = 25°C 2 4 6 8 10 12 14 16 18 20 VCC (V) –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26 IGATEUP (µA) 2.0 45 1.8 40 1.6 35 1.4 VOL_PWRGD (V) 50 30 25 20 1.0 0.8 0.6 10 0.4 5 VCC = 2.95V 1.2 15 VCC = 12V 0.2 VCC = 12V –20 0 20 40 60 80 TEMPERATURE (°C) 0 09718-029 0 –40 0 Figure 31. Gate Drive Voltage (ΔVGATE) vs. Gate Pull-Up Current (IGATEUP) Figure 28. Severe Overcurrent Voltage Threshold (VSENSEOC) vs. Supply Voltage (VCC), VISET = VVCAP VSENSEOC (mV) 0 09718-028 0 0 1 2 3 4 5 6 IOL (mA) 7 8 9 10 09718-032 5 09718-031 10 Figure 32. PWRGD Pin, VOL vs. IOL Figure 29. Severe Overcurrent Voltage Threshold (VSENSEOC) vs. Temperature, VISET = VVCAP 150 2.0 1.8 1.6 1.4 ISENSEx (µA) 100 VCC = 12V VOL (V) 1.2 1.0 VCC = 2.95V 0.8 50 0.6 0.4 1 2 3 4 5 6 7 VSENSEx (V) 8 9 10 11 12 Figure 30. SENSE+/SENSE− Input Current (ISENSEx) vs. Voltage (VSENSEx) 0 0 1 2 3 4 5 6 IOL (mA) 7 8 9 10 Figure 33. LATCH and GPO2/ALERT2 Digital Outputs, VOL vs. IOL Rev. 0 | Page 15 of 48 09718-033 0 09718-030 0.2 0 ADM1276 3.0 3.0 2.5 10 DECODE 11 DECODE 2.0 VADR (V) 1.5 1.0 1.5 1.0 0.5 0.5 +85°C +25°C –40°C 50 100 IVCAP (µA) 0 –25 09718-034 0 1100 –15 –10 –5 0 5 IADR (µA) Figure 34. VCAP Voltage (VVCAP) vs. VCAP Load (IVCAP) 1200 –20 09718-037 VVCAP (V) 01 DECODE 2.5 2.0 0 00 DECODE Figure 37. ADR Pin Voltage (VADR) vs. Current (IADR) 10 VCC = 12V 9 1000 8 7 800 ACCURACY (%) UV THRESHOLD (mV) 900 700 600 500 400 6 5 4 3 300 2 200 0 20 40 60 80 TEMPERATURE (°C) 1000 800 700 600 500 400 300 200 100 0 20 40 60 TEMPERATURE (°C) 80 09718-036 OV THRESHOLD (mV) 900 –20 5 10 15 20 SENSE VOLTAGE (mV) VCC = 12V 0 –40 128× AVERAGING 0 25 30 Figure 38. Worst-Case Current Sense Power Monitor Error vs. Current Sense Voltage (VSENSE), 0°C to 65°C, VSENSE+ = 12 V Figure 35. UV Threshold (UVTH) vs. Temperature 1100 0 09718-038 –20 09718-035 0 –40 1200 16× AVERAGING 1 100 Figure 36. OV Threshold (OVTH) vs. Temperature Rev. 0 | Page 16 of 48 ADM1276 TYPICAL APPLICATION CIRCUIT RSENSE 2.95V TO 20V SENSE+ IOUT 1.0V ISET ADM1276 CHARGE PUMP VCP LDO UV OV SENSE– + – ×50 VCC VCAP Q1 + – – 1.0V + REF SELECT 1.0V SS GATE DRIVE/ LOGIC + – CURRENTLIMIT CONTROL VCBOS TIMER ON TIMER TIMER SENSE+ VOUT IOUT GATE VOUT TIMEOUT CURRENT LIMIT TIMER ON FLB TIMEOUT 12-BIT ADC LOGIC AND PMBus PWRGD GPO2/ALERT2 LATCH SCL SDA ADR GND Figure 39. Typical Application Circuit Rev. 0 | Page 17 of 48 09718-039 2V TO 20V ADM1276 THEORY OF OPERATION RSENSE 2.95V TO 20V When circuit boards are inserted into a live backplane, discharged supply bypass capacitors draw large transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to connector pins, as well as dips on the backplane supply that can reset other boards in the system. 22Ω SENSE– SENSE+ The ADM1276 is designed to control the powering on and off of a system in a controlled manner, allowing a board to be removed from, or inserted into, a live backplane by protecting it from excess currents. The ADM1276 can reside on the backplane or on the removable board. VCC GATE ADM1276 09718-041 330nF GND POWERING THE ADM1276 To ensure correct operation of the ADM1276, the voltage on the VCC pin must be greater than or equal to the voltage on the SENSE+ pin. No sequencing of the VCC and SENSE+ rails is necessary. The SENSE+ pin can be as low as 2 V for normal operation provided that a voltage of at least 2.95 V is connected to the VCC pin. In most applications, both the VCC and SENSE+ pins are connected to the same voltage rail, but they are connected via separate traces to prevent accuracy loss in the sense voltage measurement (see Figure 40). RSENSE Figure 41. Transient Glitch Protection Using an RC Network CURRENT SENSE INPUTS The load current is monitored by measuring the voltage drop across an external sense resistor, RSENSE (see Figure 42). An internal current sense amplifier provides a gain of 50 to the voltage drop detected across RSENSE. The result is compared to an internal reference and used by the hot swap control logic to detect when an overcurrent condition occurs. RSENSE SENSE+ SENSE– + ×50 – Q1 VCC REFERENCE SENSE+ Q1 SENSE– + – OVERCURRENT GATE ADM1276 GND Figure 42. Hot Swap Current Sense Amplifier ADM1276 GATE GND The SENSE± inputs may be connected to multiple parallel sense resistors, which can affect the voltage drop detected by the ADM1276. The current flowing through the sense resistors creates an offset, resulting in reduced accuracy. 09718-040 VCC 09718-042 A supply voltage from 2.95 V to 20 V is required to power the ADM1276 via the VCC pin. The VCC pin provides the majority of the bias current for the device; the remainder of the current needed to control the gate drive and best regulate the VGS voltage is supplied by the SENSE+ pin. 2.95V TO 20V Q1 Figure 40. Powering the ADM1276 To protect the ADM1276 from unnecessary resets due to transient supply glitches, an external resistor and capacitor can be added, as shown in Figure 41. Choose the values of these components so as to provide a time constant that can filter any expected glitches. The resistor should, however, be small enough to keep voltage drops due to quiescent current to a minimum. Unless a resistor is used to limit the inrush current, do not place a supply decoupling capacitor on the rail before the FET. To achieve better accuracy, the averaging resistors sum the current from the nodes of each sense resistor, as shown in Figure 43. The typical value for the averaging resistors is 10 Ω. The averaging resistors are chosen to balance the input current to both sense pins to within 5 μA. This ensures that the same offset is seen by both sense inputs. Rev. 0 | Page 18 of 48 ADM1276 2.95V TO 20V V Q1 SS SENSE+ FLB SENSE– 1V ISET CURRENT-LIMIT REFERENCE BIAS CURRENT GATE 09718-043 VCC 0.2V Figure 43. Connection of Multiple Sense Resistors to the SENSE± Pins 0.1V CURRENT-LIMIT REFERENCE The current-limit reference voltage determines the load current level to which the ADM1276 limits the current during an overcurrent event. This reference voltage is compared to the gained-up current sense voltage to determine whether the limit is reached. An internal current-limit reference selector block continuously compares the ISET, soft start, and foldback voltages to determine which voltage is the lowest at any given time; the lowest voltage is used as the current-limit reference. This ensures that the programmed current limit, ISET, is used in normal operation, and that the soft start and foldback features reduce the current limit when required during startup and/or fault conditions. SENSE+ ×50 OVERCURRENT FLB The maximum current limit is partially determined by selecting a sense resistor to match the current sense voltage limit on the controller for the desired load current. However, as currents become larger, the sense resistor requirements become smaller, and resolution can be difficult to achieve when selecting the appropriate sense resistor. The ADM1276 provides an adjustable current sense voltage limit to handle this issue. The device allows the user to program the required current sense voltage limit from 5 mV to 25 mV. The default value of 20 mV is achieved by connecting the ISET pin directly to the VCAP pin. This configures the device to use an internal 1 V reference, which equates to 20 mV at the sense inputs (see Figure 46). SENSE– ISET SS SETTING THE CURRENT LIMIT (ISET) GATE ADM1276 GND VCAP 09718-044 VCC Q1 Figure 45. Interaction of Soft Start, Foldback, and ISET Current Limits C1 Figure 44. Current-Limit Reference Selection ISET The foldback and soft start voltages vary during different modes of operation and are, therefore, clamped to minimum levels of 200 mV and 100 mV, respectively, to prevent zero current flow due to the current limit being too low. Figure 45 provides an example of how the soft start, foldback, and ISET voltages interact during startup as the ADM1276 is enhancing the FET and charging the load capacitances. Depending on how the soft start and foldback features are configured, the hand-off point can vary to ensure that the FET is being operated within the correct limits. ADM1276 GND 09718-046 RSENSE t 09718-045 GND Figure 46. Fixed 20 mV Current Sense Limit To program the sense voltage from 5 mV to 25 mV, a resistor divider is used to set a reference voltage on the ISET pin (see Figure 47). Rev. 0 | Page 19 of 48 ADM1276 FLB (see Figure 45). This change has minimal impact on startup because the output voltage rises at a similar rate to the SS voltage. VCAP C1 SENSE+ R1 ISET SENSE– ADM1276 + – ×50 ADM1276 VCP GATE DRIVE/ LOGIC R2 REF SELECT VCAP TIMEOUT CURRENT LIMIT 1.0V CURRENT LIMIT Figure 47. Adjustable 5 mV to 25 mV Current Sense Limit SS The VCAP pin has a 2.7 V internal generated voltage that can be used to set a voltage at the ISET pin. Assuming that VISET equals the voltage on the ISET pin, size the resistor divider to set the ISET voltage as follows: 10µA CURRENT LIMIT CONTROL FLB GND Figure 48. Soft Start VISET = VSENSE × 50 FOLDBACK where VSENSE is the current sense voltage limit. The VCAP rail can also be used as the pull-up supply for setting the I2C address. Do not use the VCAP pin for any other purpose. To guarantee accuracy specifications, do not load the VCAP pin by more than 100 μA. SOFT START A capacitor connected to the SS pin determines the inrush current profile. Before the FET is enabled, the output voltage of the current-limit reference selector block is clamped at 100 mV. This, in turn, holds the hot swap sense voltage current limit, VSENSECL, at approximately 2 mV. When the FET receives a request to turn on, the SS pin is held at ground until the voltage between the SENSE+ and SENSE− pins (VSENSE) reaches the circuit breaker voltage, VCB. VCB = VSENSECL − VCBOS where VCBOS is typically 0.88 mV, making VCB = 1.12 mV. When the load current generates a sense voltage equal to VCB, a 10 μA current source is enabled, which charges the SS capacitor and results in a linear ramping voltage on the SS pin. The current-limit reference also ramps up accordingly, allowing the regulated load current to ramp up while avoiding sudden transients during power-up. The SS capacitor value is given by C SS = + – 09718-048 GND 09718-047 ISET GATE I SS × t VISET where: ISS = 10 μA. t = SS ramp time. For example, a 10 nF capacitor gives a soft start time of 1 ms. Note that the SS voltage may intersect with the FLB (foldback) voltage, and the current-limit reference may change to follow Foldback is a method to actively reduce the current limit as the voltage drop across the FET increases. It keeps the power across the FET to a minimum during power-up, overcurrent, or shortcircuit events. It also avoids the need to oversize the FET to accommodate worst-case conditions, resulting in board size and cost savings. The ADM1276 detects the voltage drop across the FET by looking at a resistor divided version of the output voltage. It is assumed that the supply voltage remains constant and within tolerance. The device, therefore, relies on the principle that the drain of the FET is at the maximum expected supply voltage, and that the magnitude of the output voltage is relative to that of the VDS of the FET. Using a resistor divider from the output voltage to the FLB pin, a relationship from VOUT, and thus VDS, to VFLB can be derived. Design the resistor divider to output a voltage equal to ISET when VOUT falls below the desired level. This should be well below the working tolerance of the supply rail. As VOUT continues to drop, the current-limit reference follows VFLB because it is now the lowest voltage input to the current-limit reference selector block. This results in a reduction of the current limit and, therefore, the regulated load current. To prevent complete current flow restriction, a clamp becomes active when the current-limit reference reaches 200 mV. The current limit cannot drop below this level. To suit the SOA characteristics of a particular FET, the required minimum current for this clamp varies from design to design. However, the current-limit reference fixes this clamp at 200 mV, which equates to 4 mV at the sense resistor. Therefore, the main ISET voltage can be adjusted to align this clamp to the required percentage current reduction. For example, if ISET equals 0.8 V, the clamp can be set at 25% of the maximum current. Rev. 0 | Page 20 of 48 ADM1276 TIMER The TIMER pin handles several timing functions with an external capacitor, CTIMER. The two comparator thresholds are VTIMERL (0.2 V) and VTIMERH (1 V). There are four timing current sources: a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and a 100 μA pull-down. These current and voltage levels, together with the value of CTIMER chosen by the user, determine the initial timing cycle time, the fault current-limit time, and the hot swap retry duty cycle. The TIMER pin capacitor value is determined using the following equation: CTIMER = (tON × 60 μA)/VTIMERH where tON is the time that the FET is allowed to spend in regulation at the set current limit. The choice of FET is based on matching this time with the SOA requirements of the FET. Foldback can be used to simplify the selection. When VCC is connected to the backplane supply, the internal supply of the ADM1276 must be charged up. In a very short time, the internal supply is fully charged up and, because the undervoltage lockout (UVLO) voltage is exceeded at VCC, the device emerges from reset. During this first short reset period, the GATE and TIMER pins are both held low. The ADM1276 then goes through an initial timing cycle. The TIMER pin is pulled high with 3 μA. When the TIMER pin reaches the VTIMERH threshold (1.0 V), the first portion of the initial timing cycle is complete. The 100 μA current source then pulls down the TIMER pin until it reaches VTIMERL (0.2 V). The initial timing cycle duration is related to CTIMER by the following equation: t INITIAL VTIMERH CTIMER 3 A (VTIMERH VTIMERL ) CTIMER 100 A For example, a 100 nF capacitor results in a delay of approximately 34 ms. If the UV and OV inputs indicate that the supply is within the defined window of operation when the initial timing cycle terminates, the device is ready to start a hot swap operation. When the voltage across the sense resistor reaches the circuit breaker trip voltage, VCB, the 60 μA timer pull-up current is activated, and the gate begins to regulate the current at the current limit. This initiates a ramp-up on the TIMER pin. If the sense voltage falls below this circuit breaker trip voltage before the TIMER pin reaches VTIMERH, the 60 μA pull-up is disabled and the 2 μA pull-down is enabled. The circuit breaker trip voltage is not the same as the hot swap sense voltage current limit. There is a small circuit breaker offset, VCBOS, which means that the timer actually starts a short time before the current reaches the defined current limit. However, if the overcurrent condition is continuous and the sense voltage remains above the circuit breaker trip voltage, the 60 μA pull-up remains active and the FET remains in regulation. This allows the TIMER pin to reach VTIMERH and initiate the GATE shutdown. On the ADM1276, the LATCH pin is pulled low immediately. In latch-off mode, the TIMER pin is switched to the 2 μA pull-down when it reaches the VTIMERH threshold. The LATCH pin remains low. While the TIMER pin is being pulled down, the hot swap controller remains off and cannot be turned back on. When the voltage on the TIMER pin goes below the VTIMERL threshold, the hot swap controller can be reenabled by toggling the UV pin or by using the PMBus OPERATION command to toggle the on bit from on to off and then on again. HOT SWAP RETRY DUTY CYCLE The ADM1276 turns off the FET after an overcurrent fault and then uses the capacitor on the TIMER pin to provide a delay before automatically retrying the hot swap operation. To configure the ADM1276 for autoretry mode, the LATCH pin is tied to either the UV pin or to the ENABLE pin. Note that a pull-up resistor is required on the LATCH pin. When an overcurrent fault occurs, the capacitor on the TIMER pin is charged with a 60 μA pull-up current. When the TIMER pin reaches VTIMERH, the GATE pin is pulled down. When the LATCH pin is tied to the UV pin or the ENABLE pin for autoretry mode, the TIMER pin is pulled down with a 2 μA current sink. When the TIMER pin reaches VTIMERL (0.2 V), it automatically restarts the hot swap operation. The duty cycle of this automatic retry cycle is set by the ratio of 2 μA/60 μA, which approximates to being on about 4% of the time. The value of the timer capacitor determines the on time of this cycle, which is calculated as follows: tON = VTIMERH × (CTIMER/60 μA) tOFF = (VTIMERH − VTIMERL) × (CTIMER/2 μA) A 100 nF capacitor on the TIMER pin gives an on time of 1.67 ms and an off time of 40 ms. The device retries indefinitely in this manner and can be disabled manually by holding the UV or ENABLE pin low, or by disconnecting the LATCH pin. To prevent thermal stress, an RC network can be used to extend the retry time to any desired level. FET GATE DRIVE CLAMPS The charge pump used on the GATE pin is capable of driving the pin to VCC + (2 × VCC), but it is clamped to less than 14 V above the SENSE± pins and less than 31 V. These clamps ensure that the maximum VGS rating of the FET is not exceeded. Rev. 0 | Page 21 of 48 ADM1276 FAST RESPONSE TO SEVERE OVERCURRENT UNDERVOLTAGE AND OVERVOLTAGE The ADM1276 monitors the supply voltage for undervoltage (UV) and overvoltage (OV) conditions. The UV and OV pins are connected to the input of an internal voltage comparator, and its voltage level is internally compared with a 1 V voltage reference. Figure 49 illustrates the voltage monitoring input connections. An external resistor network divides the supply voltage for monitoring. An undervoltage event is detected when the voltage connected to the UV pin falls below 1 V, and the gate is shut down using the 10 mA pull-down device. Similarly, when an overvoltage event occurs and the voltage on the OV pin exceeds 1 V, the gate is shut down using the 10 mA pull-down device. SENSE– SENSE+ UV OV + 1V – ×50 ADM1276 – IOUT GATE DRIVE – 1V + GND R1 UV R2 Figure 50. Using the UV Pin as an Enable Diode D1 prevents the external driver pull-up from affecting the UV threshold. Select Diode D1 using the following criteria: (VF × D1) + (VOL × EN) << 1.0 V (IF = VIN/R1) Ensure that the EN sink current does not exceed the specified VOL value. If the open-drain device has no pull-up, the diode is not required. POWER GOOD The power good (PWRGD) output can be used to indicate whether the output voltage is above a user-defined threshold and can, therefore, be considered good. The PWRGD output is derived using the FLB resistor network, composed of R1 and R2 (see Figure 51). The PWRGD pin is an open-drain output that pulls low when the voltage at the FLB pin is lower than 1.1 × VISET (power bad). When the voltage at the FLB pin is above this threshold (indicating that the output voltage has risen), the open-drain pull-down is disabled, allowing PWRGD to be pulled high. PWRGD is guaranteed to be in a valid state for VCC ≥ 1 V. Hysteresis on the FLB pin is provided by a 2 μA internal current source that is switched on when the VFLB input voltage exceeds the input threshold. The current source is disconnected when VOUT drops below the foldback threshold voltage minus the hysteresis voltage. Resistor R3 is internal to the ADM1276. The hysteresis voltage at the FLB pin can be varied by adjusting the parallel combination of Resistor R1 and Resistor R2. GATE 09718-049 + VCC Q1 D1 Figure 49. Undervoltage and Overvoltage Supply Monitoring ENABLE INPUT The ADM1276 provides a dedicated ENABLE digital input pin. The ENABLE pin allows the ADM1276 to remain off by using a hardware signal, even when the voltage on the UV pin is above 1.0 V and the voltage on the OV pin is less than 1.0 V. Although the UV pin can be used to provide a digital enable signal, using the ENABLE pin for this purpose means that the ability to monitor for undervoltage conditions is not lost. In addition to the conditions for the UV and OV pins, the ADM1276 ENABLE input pin must be high for the device to begin a power-up sequence. 2μA VOUT R1 R2 SWITCH IS ON WHEN COMPARATOR OUTPUT IS HIGH FLB R3 1.3kΩ 1.1 × VISET Figure 51. Generation of PWRGD Signal A similar function can be achieved using the UV pin directly. Alternatively, if the UV divider function is still required, the configuration shown in Figure 50 can be used. Rev. 0 | Page 22 of 48 PWRGD 09718-051 RSENSE EN ADM1276 09718-050 The ADM1276 features a separate high bandwidth current sense amplifier that is used to detect a severe overcurrent that is indicative of a short-circuit condition. A fast response time allows the ADM1276 to handle events of this type that could otherwise cause catastrophic damage if not detected and acted on very quickly. The fast response circuit ensures that the ADM1276 can detect an overcurrent event at approximately 200% to 250% of the normal current limit (ISET) and can respond to and control the current within 1 μs, in most cases. VIN VIN SYSTEM CONTROL ADM1276 VOUT MEASUREMENT The VOUT pin on the ADM1276 can be used to provide an alternate voltage for the power monitor to measure. The user can choose to measure the voltage at the SENSE+ pin or the voltage at the VOUT pin, using either the low or high input voltage range. If the VOUT pin is to be used to measure the output voltage after the FET, insert a 1 kΩ resistor in series between the source of the FET and the VOUT pin. This resistor provides some separation between the ADM1276 and the FET source during a fault condition; thus, ADM1276 operation is not affected. FET HEALTH The ADM1276 provides a method of detecting a shorted pass FET. The FET health status can be used to generate an alert on the GPO2/ALERT2 pin. By default at power-up, an alert is generated on the GPO2/ALERT2 pin of the ADM1276 when the FET health status indicates that a bad FET is present. FET health is considered bad if all of the following conditions are true: The ADM1276 is holding the FET off, for example, during the initial power-on cycle time. VSENSE > 2 mV. VGATE < ~1 V, that is, less than the FET gate threshold. POWER MONITOR The ADM1276 features an integrated ADC that accurately measures the current sense voltage, the input voltage, and (optionally) the output voltage. The measured input voltage and current being delivered to the load are multiplied to give a power value that can be read back. Each power value is also added to an accumulator that can be read back to allow an external device to calculate the energy consumption of the load. PEAK_VOUT commands can be used to read the highest peak current or voltage since the value was last cleared. An averaging function is provided for voltage and current that allows a number of samples to be averaged by the ADM1276. This function reduces the need for postprocessing of sampled data by the host processor. The number of samples that can be averaged is 2N, where N is in the range of 0 to 7. The power monitor current sense amplifier is bipolar and can measure both positive and negative currents. The power monitor amplifier has an input range of ±25 mV. Two input voltage ranges are available and can be selected using the PMBus interface: 0 V to 6 V (low input range) and 0 V to 20 V (high input range). The two basic modes of operation for the power monitor are single shot and continuous. In single shot mode, the power monitor samples the input voltage and current a number of times, depending on the averaging value selected by the user. The ADM1276 returns a single value corresponding to the average voltage and current measured. When configured for continuous mode, the power monitor continuously samples voltage and current, making the most recent sample available to be read. The single shot mode can be triggered in a number of ways. The simplest is by selecting the single shot mode using the PMON_CONFIG command and writing to the convert bit using the PMON_CONTROL command. The convert bit can also be written as part of a PMBus group command. Using a group command allows multiple devices to be written to as part of the same I2C bus transaction, with all devices executing the command when the stop condition appears on the bus. In this way, several devices can be triggered to sample at the same time. The ADM1276 can report the measured current, input voltage, and the output voltage. The PEAK_IOUT, PEAK_VIN, and Rev. 0 | Page 23 of 48 ADM1276 PMBus INTERFACE The I2C bus is a common, simple serial bus used by many devices to communicate. It defines the electrical specifications, the bus timing, the physical layer, and some basic protocol rules. SMBus is based on I2C and aims to provide a more robust and fault tolerant bus. Functions such as bus timeout and packet error checking are added to help achieve this robustness, along with more specific definitions of the bus messages used to read and write data to devices on the bus. PMBus is layered on top of SMBus and, in turn, on I2C. Using the SMBus defined bus messages, PMBus defines a set of standard commands that can be used to control a device that is part of a power chain. The ADM1276 command set is based upon the PMBus™ Power System Management Protocol Specification, Part I and Part II, Revision 1.2. This version of the standard is intended to provide a common set of commands for communicating with dc-to-dc type devices. However, many of the standard PMBus commands can be mapped directly to the functions of a hot swap controller. Part I and Part II of the PMBus standard describe the basic commands and how they can be used in a typical PMBus setup. The following sections describe how the PMBus standard and the ADM1276 specific commands are used. DEVICE ADDRESSING The ADM1276 is available in one model: the ADM1276-3. The PMBus address is 7 bits in size. The upper 5 bits (MSBs) of the address word are fixed. The base address for the ADM1276 is 01000xx (0x20). The ADM1276 has a single ADR pin that is used to select one of four possible addresses. The ADR pin connection selects the lowest two bits (LSBs) of the 7-bit address word (see Table 6). Table 6. PMBus Addresses and ADR Pin Connection Value of Address LSBs 00 01 10 11 SMBus PROTOCOL USAGE All I2C transactions on the ADM1276 are done using SMBus defined bus protocols. The following SMBus protocols are implemented by the ADM1276: Send byte Receive byte Write byte Read byte Write word Read word Block read PACKET ERROR CHECKING The ADM1276 PMBus interface supports the use of the packet error checking (PEC) byte that is defined in the SMBus standard. The PEC byte is transmitted by the ADM1276 during a read transaction or sent by the bus host to the ADM1276 during a write transaction. The ADM1276 supports the use of PEC with all the SMBus protocols that it implements. The use of the PEC byte is optional. The bus host can decide whether to use the PEC byte with the ADM1276 on a messageby-message basis. There is no need to enable or disable PEC in the ADM1276. The PEC byte is used by the bus host or the ADM1276 to detect errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC byte read during a read transaction is incorrect, it can decide to repeat the read if necessary. If the ADM1276 determines that the PEC byte sent during a write transaction is incorrect, it ignores the command (does not execute it) and sets a status flag. Within a group command, the host can choose to send or not send a PEC byte as part of the message to the ADM1276. ADR Pin Connection Connect to GND 150 kΩ resistor to GND No connection (floating) Connect to VCAP Rev. 0 | Page 24 of 48 ADM1276 W is the write bit. A is the acknowledge bit (0). A is the acknowledge bit (1). SMBus MESSAGE FORMATS Figure 52 to Figure 60 show all the SMBus protocols supported by the ADM1276, along with the PEC variant. In these figures, unshaded cells indicate that the bus host is actively driving the bus; shaded cells indicate that the ADM1276 is driving the bus. “A” represents the acknowledge bit. The acknowledge bit is typically active low (Logic 0) if the transmitted byte is successfully received by a device. However, when the receiving device is the bus master, the acknowledge bit for the last byte read is a Logic 1, indicated by A. Figure 52 to Figure 60 use the following abbreviations: S is the start condition. Sr is the repeated start condition. P is the stop condition. R is the read bit. SLAVE ADDRESS W A DATA BYTE A S SLAVE ADDRESS W A DATA BYTE A P PEC A P PEC A P 09718-052 S MASTER TO SLAVE SLAVE TO MASTER Figure 52. Send Byte and Send Byte with PEC SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS R A DATA BYTE A P 09718-053 S MASTER TO SLAVE SLAVE TO MASTER Figure 53. Receive Byte and Receive Byte with PEC SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE A P PEC A P 09718-054 S MASTER TO SLAVE SLAVE TO MASTER Figure 54. Write Byte and Write Byte with PEC SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A S SLAVE ADDRESS W A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE A P PEC A P 09718-055 S MASTER TO SLAVE SLAVE TO MASTER Figure 55. Read Byte and Read Byte with PEC S SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A SLAVE ADDRESS W A COMMAND CODE A DATA BYTE LOW A DATA BYTE HIGH A P PEC A P 09718-056 S MASTER TO SLAVE SLAVE TO MASTER Figure 56. Write Word and Write Word with PEC Rev. 0 | Page 25 of 48 ADM1276 S SLAVE ADDRESS W DATA BYTE HIGH S A SLAVE ADDRESS COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A A COMMAND CODE A Sr SLAVE ADDRESS R A DATA BYTE LOW A R A BYTE COUNT = N A A BYTE COUNT = N A P W DATA BYTE HIGH A PEC A P 09718-057 A MASTER TO SLAVE SLAVE TO MASTER Figure 57. Read Word and Read Word with PEC S SLAVE ADDRESS DATA BYTE 1 S W A DATA BYTE 2 A SLAVE ADDRESS DATA BYTE 1 COMMAND CODE W A SLAVE ADDRESS A COMMAND CODE DATA BYTE 2 DATA BYTE N A Sr A SLAVE ADDRESS A DATA BYTE N P R A PEC A P 09718-058 A A Sr MASTER TO SLAVE SLAVE TO MASTER Figure 58. Block Read and Block Read with PEC ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE A HIGH DATA BYTE A ONE OR MORE DATA BYTES A HIGH DATA BYTE A ONE OR MORE DATA BYTES DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A P 09718-059 Sr MASTER TO SLAVE SLAVE TO MASTER Figure 59. Group Command ONE OR MORE DATA BYTES S DEVICE 1 ADDRESS W A COMMAND CODE 1 A LOW DATA BYTE Sr DEVICE 2 ADDRESS W A COMMAND CODE 2 A LOW DATA BYTE Sr DEVICE N ADDRESS W A COMMAND CODE N A LOW DATA BYTE A HIGH DATA BYTE A PEC 1 A A PEC 2 A A PEC N A P ONE OR MORE DATA BYTES A HIGH DATA BYTE ONE OR MORE DATA BYTES A 09718-060 HIGH DATA BYTE MASTER TO SLAVE SLAVE TO MASTER Figure 60. Group Command with PEC GROUP COMMANDS The PMBus standard defines what are known as group commands. Group commands are single bus transactions that send commands or data to more than one device at the same time. Each device is addressed separately, using its own address; there is no special group command address. A group command transaction can contain only write commands that send data to a device. It is not possible to use a group command to read data from devices. From an I2C protocol point of view, a normal write command consists of the following: • • • • Rev. 0 | Page 26 of 48 I2C start condition. Slave address bits and a write bit (followed by an acknowledge from the slave device). One or more data bytes (each of which is followed by an acknowledge from the slave device). I2C stop condition to end the transaction. ADM1276 A group command differs from a nongroup command in that after the data is written to one slave device, a repeated start condition is placed on the bus followed by the address of the next slave device and data. This continues until all of the devices have been written to, at which point the stop condition is placed on the bus by the master device. The format of a group command and a group command with PEC is shown in Figure 59 and Figure 60. It is possible to determine at any time whether the hot swap output is enabled using the STATUS_BYTE or the STATUS_WORD command (see the Status Commands section). The OPERATION command can also clear any latched faults in the status registers. To clear latched faults, set the on bit to 0 and then reset it to 1. DEVICE_CONFIG Command Each device that is written to as part of the group command does not immediately execute the command written. The device must wait until the stop condition appears on the bus. At that point, all devices execute their commands at the same time. The DEVICE_CONFIG command configures certain settings within the ADM1276, for example, enabling or disabling foldback in the hot swap controller, or modifying the duration of the severe overcurrent glitch filter. This command is also used to configure the polarity of the second IOUT current warnings. Using a group command, it is possible, for example, to turn multiple PMBus devices on or off simultaneously. In the case of the ADM1276, it is also possible to issue a power monitor command that initiates a conversion, causing multiple ADM1276 devices to sample together at the same time. The OPERATION command is disabled at power-up. If the OPERATION command is received, the ADM1276 responds with a no acknowledge. To allow use of the OPERATION command, the OPERATION_CMD_EN bit must be set via the DEVICE_CONFIG command. HOT SWAP CONTROL COMMANDS POWER_CYCLE Command OPERATION Command The POWER_CYCLE command can be used to request that the ADM1276 be turned off for ~4 seconds and then turned back on. This command can be useful if the processor that controls the ADM1276 is also powered off when the ADM1276 is turned off. This command allows the processor to request that the ADM1276 turn off and on again as part of a single command. The GATE pin that drives the FET is controlled by a dedicated hot swap state machine. The UV and OV input pins, the TIMER and SS pins, and the current sense all feed into the state machine and they control when and how strongly the gate is turned off. It is also possible to control the hot swap GATE output using commands over the PMBus interface. The OPERATION command can be used to request the hot swap output to turn on. However, if the UV pin indicates that the input supply is less than required, the hot swap output is not turned on, even if the OPERATION command indicates that the output should be enabled. If the OPERATION command is used to disable the hot swap output, the GATE pin is held low, even if all hot swap state machine control inputs indicate that it can be enabled. ADM1276 INFORMATION COMMANDS CAPABILITY Command The CAPABILITY command can be used by host processors to determine the I2C bus features that are supported by the ADM1276. The features that can be reported include the maximum bus speed, whether the device supports the packet error checking (PEC) byte, and the SMBAlert reporting function. PMBUS_REVISION Command The PMBUS_REVISION command reports the version of Part I and Part II of the PMBus standard. The default state of Bit 7 (also named the on bit) of the OPERATION command is 1; therefore, the hot swap output is always enabled when the ADM1276 emerges from UVLO. If the on bit is never changed, the UV input or the ENABLE input is the hot swap master on/off control signal. MFR_ID, MFR_MODEL, and MFR_REVISION Commands By default at power-up, the OPERATION command is disabled and must be enabled using the DEVICE_CONFIG command. This prevents inadvertent shutdowns of the hot swap controller by software. If the on bit is set to 0 while the UV signal is high, the hot swap output is turned off. If the UV signal is low or if the OV signal is high, the hot swap output is already off and the status of the on bit has no effect. If the on bit is set to 1, the hot swap output is requested to turn on. If the UV signal is low or if the OV signal is high, setting the on bit to 1 has no effect, and the hot swap output remains off. The MFR_ID, MFR_MODEL, and MFR_REVISION commands return ASCII strings that can be used to facilitate detection and identification of the ADM1276 on the bus. These commands are read using the SMBus block read message type. This message type requires that the ADM1276 return a byte count corresponding to the length of the string data that is to be read back. STATUS COMMANDS The ADM1276 provides a number of status bits that are used to report faults and warnings from the hot swap controller and the power monitor. These status bits are located in six different registers that are arranged in a hierarchy. The STATUS_BYTE and STATUS_WORD commands provide 8 bits and 16 bits of high level information, respectively. The STATUS_BYTE and STATUS_WORD commands contain the most important status Rev. 0 | Page 27 of 48 ADM1276 bits, as well as pointer bits that indicate whether any of the four other status registers need to be read for more detailed status information. In the ADM1276, a particular distinction is made between faults and warnings. A fault is always generated by the hot swap controller and is defined by hardware component values. Three events can generate a fault: • • • Overcurrent condition that causes the hot swap timer to time out. Overvoltage condition on the OV pin. Undervoltage condition on the UV pin. When a fault occurs, the hot swap controller always takes some action, usually to turn off the GATE pin, which is driving the FET. A fault can also generate an SMBAlert on the GPO2/ALERT2 pin. All warnings in the ADM1276 are generated by the power monitor, which samples the voltage and current and then compares these measurements to the threshold values set by the various limit commands. A warning has no effect on the hot swap controller, but it may generate an SMBAlert on the GPO2/ALERT2 output pin. When a status bit is set, it always means that the status condition— fault or warning—is active or was active at some point in the past. When a fault or warning bit is set, it is latched until it is explicitly cleared using either the OPERATION or the CLEAR_FAULTS command. Some other status bits are live, that is, they always reflect a status condition and are never latched. STATUS_BYTE and STATUS_WORD Commands The STATUS_BYTE and STATUS_WORD commands can be used to obtain a snapshot of the overall part status. These commands indicate whether it is necessary to read more detailed information using the other status commands. The low byte of the word returned by the STATUS_WORD command is the same byte returned by the STATUS_BYTE command. The high byte of the word returned by the STATUS_WORD command provides a number of bits that can be used to determine which of the other status commands needs to be issued to obtain all active status bits. STATUS_INPUT Command The STATUS_INPUT command returns a number of bits relating to voltage faults and warnings on the input supply. STATUS_VOUT Command The STATUS_VOUT command returns a number of bits relating to voltage faults and warnings on the output supply. STATUS_IOUT Command The STATUS_IOUT command returns a number of bits relating to current faults and warnings on the output supply. STATUS_MFR_SPECIFIC Command The STATUS_MFR_SPECIFIC command is a standard PMBus command, but the contents of the byte returned are specific to the ADM1276. CLEAR_FAULTS Command The CLEAR_FAULTS command is used to clear fault and warnings bits when they are set. Fault and warnings bits are latched when they are set. In this way, a host can read the bits any time after the fault or warning condition occurs and determine which problem actually occurred. If the CLEAR_FAULTS command is issued and the fault or warning condition is no longer active, the status bit is cleared. If the condition is still active—for example, if an input voltage is below the undervoltage threshold of the UV pin—the CLEAR_FAULTS command attempts to clear the status bit, but that status bit is immediately set again. GPO AND ALERT PIN SETUP COMMANDS A multipurpose pin is provided on the ADM1276: GPO2/ALERT2. The GPO2/ALERT2 pin can be configured over the PMBus in one of three output modes, as follows: • • • General-purpose digital output. Output for generating an SMBAlert when one or more fault/warning status bits become active in the PMBus status registers. Digital comparator. In digital comparator mode, the current, voltage, and power warning thresholds are compared to the values read or calculated by the ADM1276. The comparison result sets the output high or low according to whether the value is greater or less than the warning threshold that has been set. For an example of how to configure this pin to generate an SMBAlert and how to respond and clear the condition, see the Example Use of SMBus Alert Response Address section. ALERT2_CONFIG Command Using combinations of bit masks, the ALERT2_CONFIG command can be used to select the status bits that, when set, generate an SMBAlert signal to a processor, or control the digital comparator mode. They can also be used to set a GPO mode on the GPO2/ALERT2 pin, so that it is under software control. If this mode is set, the SMBAlert masking bits are ignored. POWER MONITOR COMMANDS The ADM1276 provides a high accuracy, 12-bit current and voltage power monitor. The power monitor can be configured in a number of different modes of operation and can run in either continuous mode or single shot mode with a number of different sample averaging options. Rev. 0 | Page 28 of 48 ADM1276 The power monitor can measure the following quantities: • • • Each time a power calculation is done, the 24-bit power value is added to a 24-bit energy accumulator register. This is a twos complement representation as well, so the MSB is always zero. Each time this energy accumulator register rolls over from 0x7FFFFF to 0x000000, a 16-bit rollover counter is incremented. The rollover counter is straight binary, with a maximum value of 0xFFFF before it rolls over. Input voltage (VIN). Output voltage (VOUT). Output current (IOUT). The following quantities are then calculated: • • Input power (PIN). Input energy (EIN). A 24-bit straight binary power sample counter is also incremented by 1 each time a power value is calculated and added to the energy accumulator. PMON_CONFIG Command The power monitor can run in a number of different modes with different input voltage range settings. The PMON_CONFIG command is used to set up the power monitor. The settings that can be configured are as follows: • • • • Single shot or continuous sampling. VOUT sampling enable/disable. Voltage input range. Current and voltage sample averaging. Modifying the power monitor settings while the power monitor is sampling is not recommended. To ensure correct operation of the device and to avoid any potential spurious data or the generation of status alerts, stop the power monitor before any of these settings are changed. PMON_CONTROL Command Power monitor sampling can be initiated via hardware or via software using the PMON_CONTROL command. This command can be used with single shot or continuous mode. READ_VIN, READ_VOUT, and READ_IOUT Commands The ADM1276 power monitor measures the voltage developed across the sense resistor to provide a current measurement. The input voltage from the SENSE+ pin is always measured, and the output voltage present on the VOUT pin is available if enabled with the PMON_CONFIG command. READ_PIN, READ_PIN_EXT, READ_EIN, and READ_EIN_EXT Commands The 12-bit VIN input voltage and 12-bit IOUT current measurement values are multiplied by the ADM1276 to give the input power value. This is accomplished by using fixed point arithmetic, and produces a 24-bit value. It is assumed that the numbers are in the 12.0 format, meaning that there is no fractional part. Note that only positive IOUT values are used to avoid returning a negative power. This 24-bit value can be read from the ADM1276 using the READ_PIN_EXT command, where the most significant bit (MSB) is always a zero because PIN_EXT is a twos complement binary value that is always positive. The sixteen most significant bits of the 24-bit value are used as the value for PIN. The MSB of the 16-bit PIN word is always zero, as PIN is a twos complement binary value, that is always positive. These registers can be read back using one of two commands, depending on the level of accuracy required for the energy accumulator and the desire to limit the frequency of reads from the ADM1276. A bus host can read these values, and by calculating the delta in the energy accumulated, the delta in the number of samples, and the time delta since the last read, the host can calculate the average power since the last read, as well as the energy consumed since then. The time delta is calculated by the bus host based on when it sends its commands to read from the device, and is not provided by the ADM1276. To avoid loss of data, the bus host must read at a rate that ensures the rollover counter does not wrap around more than once, and if the counter does wrap around that the next value read for PIN is less than the previous one. The READ_EIN command returns the top 16 bits of the energy accumulator, the lower eight bits of the rollover counter, and the full 24 bits of the sample counter. The READ_EIN_EXT command returns the full 24 bits of the energy accumulator, the full 16 bits of the rollover counter, and the full 24 bits of the sample counter. The use of the longer rollover counter means that the time interval between reads of the part can be increased from seconds to minutes, without losing any data. PEAK_IOUT, PEAK_VIN, PEAK_VOUT, and PEAK_PIN Commands In addition to the standard PMBus commands for reading voltage and current, the ADM1276 provides commands that can report the maximum peak voltage, current, or power value since the peak value was last cleared. The peak values are updated only after the power monitor has sampled and averaged the current and voltage measurements. Individual peak values are cleared by writing a 0 value with the corresponding command. WARNING LIMIT SETUP COMMANDS The ADM1276 power monitor can monitor a number of different warning conditions simultaneously and report any current or voltage values that exceed the user-defined thresholds using the status commands. Rev. 0 | Page 29 of 48 ADM1276 All comparisons performed by the power monitor require the measured value to be strictly greater or less than the threshold value. The same equations are used for voltage, current, and power conversions, the only difference being the values of the m, b, and R coefficients that are used. At power-up, all threshold limits are set to either minimum scale (for undervoltage or undercurrent conditions) or to maximum scale (for overvoltage or overcurrent or overpower conditions). This effectively disables the generation of any status warnings by default; warning bits are not set in the status registers until the user explicitly sets the threshold values. Table 7 lists all the coefficients required for the ADM1276. The coefficients shown are independent of the value of the external sense resistor used in a given application. This means that an additional calculation must be performed to take the sense resistor value into account when converting to or from a realworld current or power value. VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT Commands The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT commands are used to set the OV and UV thresholds on the input voltage, as measured at the SENSE+ pin. The current sense voltage coefficients shown in Table 7 convert between the voltage that appears across the sense resistor(s), expressed in millivolts, and the direct format value that is used by the ADM1276 as a threshold or reported as a current measurement. VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT Commands Example 1. IOUT_OC_WARN_LIMIT requires a current-limit value expressed in direct format. The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_ LIMIT commands are used to set the OV and UV thresholds on the output voltage, as measured at the VOUT pin. If the required current limit is 10 A, and the sense resistor is 2 mΩ, then the first step is to determine the current sense voltage. This is simply V = IR, giving 20 mV in this case. IOUT_OC_WARN_LIMIT Command Using Equation 1, and expressing X, in units of millivolts Y = ((807 × 20) + 20,475) × 10−1 The IOUT_OC_WARN_LIMIT command sets the OC threshold for the current flowing through the sense resistor. Y = 3661.5 = 3662 (rounded up to integer form) IOUT_WARN2_LIMIT Command Writing a value of 3662 with the IOUT_OC_WARN_LIMIT command sets an overcurrent warning at 10 A. The IOUT_WARN2_LIMIT command provides a second current warning threshold that can be programmed. The polarity of this warning can be set to overcurrent or undercurrent using the DEVICE_CONFIG command. Example 2. The READ_IOUT command returns a direct format value of 3339 representing the current flowing through a sense resistor of 1 mΩ. PIN_OP_WARN_LIMIT Command To convert this value to the current sense voltage, use Equation 2 The PIN_OP_WARN_LIMIT command is used to set the overpower threshold for the power delivered to the load. X = 1/807 × (3339 × 101 − 20,475) X = 16.00 mV PMBus DIRECT FORMAT CONVERSION To convert to current in amps, use The ADM1276 uses the PMBus direct format internally to represent real-world quantities such as voltage, current, and power values. A direct format number takes the form of a 2-byte, twos complement, binary integer value. I = V/R where R is expressed in milliohms. It is possible to convert in real-world quantities. Equation 1 converts from real-world quantities to PMBus direct values, and Equation 2 converts PMBus direct format values to real-world values. Y = (mX + b) × 10R (1) −R X = 1/m × (Y × 10 − b) (2) where: Y is the value in PMBus direct format. X is the real-world value. m is the slope coefficient, a 2-byte, twos complement integer. b is the offset, a 2-byte, twos complement integer. R is a scaling exponent, a 1-byte, twos complement integer. This means that when READ_IOUT returns a value of 3339, 16.00 A is flowing in the sense resistor. Because power is equal to voltage × current, power value conversions are affected by the value of the sense resistor in a similar manner. The coefficients in Table 7 can be used to convert direct format values to resistor scaled power values and vice versa, which then need to be scaled by the resistor value. When converting from real-world power to direct format, the power (in watts) is multiplied by the value of the sense resistor expressed in ohms to give the resistor scaled power value. The resistor scaled power value can then be inserted into Equation 1 with the appropriate conversion coefficients to obtain the direct format value. When converting from direct format to real-world power, the direct format value is first converted with Equation 2, and then Rev. 0 | Page 30 of 48 ADM1276 divided by the sense resistor value in ohms to obtain the realworld power in watts. There are also two input voltage ranges, thus, there are two sets of coefficients for converting to and from the power value. If the required power limit is 350 W and the sense resistor is 1 mΩ, the first step is to determine the resistor scaled power value. PRESSCALED = P × R Note the following: PRESSCALED = 350 × 0.001 • PRESSCALED = 0.35 • The same calculations that are used to convert power values also apply to the energy accumulator value returned by the READ_EIN command because the energy accumulator is a summation of multiple power values. The READ_PIN_EXT and READ_EIN_EXT commands return 24-bit extended precision versions of the 16-bit values returned by READ_PIN and READ_EIN. The direct format values must be divided by 256 prior to being converted with the coefficients shown in Table 7. Example 3. The PIN_OP_WARN_LIMIT command requires a power limit value expressed in direct format. where: P is the real-world power expressed in watts. R is the sense resistor value expressed in ohms. PRESSCALED is the resistor scaled version of power. Using Equation 1, and working with the 0 V to 20 V range, Y = ((6043 × 0.35 + 0) × 101 Y = 21,150.5 = 21,151 (rounded up to integer form) Writing a value of 21,151 with the PIN_OP_WARN_LIMIT command sets an overpower warning at 350 W. Table 7. PMBus Conversion to Real-World Coefficients Coefficient m b R Current Sense Voltage 807 20,475 −1 0 V to 6 V Range 6720 0 −1 Voltage 0 V to 20 V Range 19,199 0 −2 Rev. 0 | Page 31 of 48 Power (Resistor Scaled) 0 V to 6 V Range 0 V to 20 V Range 2115 6043 0 0 +2 +1 ADM1276 VOLTAGE AND CURRENT CONVERSION USING LSB VALUES The direct format voltage and current values returned by the READ_VIN, READ_VOUT, and READ_IOUT commands, and the corresponding peak versions, are the data output directly by the ADM1276 ADC. Because the voltages and currents are 12-bit ADC output codes, they can also be converted to real-world values when there is knowledge of the size of the LSB on the ADC. The m, b, and R coefficients defined for the PMBus conversion are required to be whole integers by the standard and have, therefore, been rounded slightly. Using this alternative method, with the exact LSB values, can provide somewhat more accurate numerical conversions. To convert an ADC code to current in amperes, the following formulas can be used: VSENSE = LSB25 mV × (IADC − 2048) IOUT = VSENSE/(RSENSE × 0.001) where: VSENSE = (VSENSE+) − (VSENSE−). LSB25 mV = 12.4 μV. IADC is the 12-bit ADC code. IOUT is the measured current value in amperes. RSENSE is the value of the sense resistor in milliohms. Table 8. Voltage Ranges and LSB Values Voltage Range, LSBxV 0 V to 6 V 0 V to 20 V LSB Magnitude 1.488 mV 5.208 mV To convert a current in amperes to a 12-bit value, the following formula can be used (round the result to the nearest integer): VSENSE = IA × RSENSE × 0.001 ICODE = 2048 + (VSENSE/LSB25 mV) where: VSENSE = (VSENSE+) − (VSENSE−). IA is the current value in amperes. RSENSE is the value of the sense resistor in milliohms. ICODE is the 12-bit ADC code. LSB25 mV = 12.4 μV. To convert a voltage to a 12-bit value, the following formula can be used (round the result to the nearest integer): VCODE = (VA/LSBxV) − 0.5 To convert an ADC code to a voltage, the following formula can be used: VM = LSBxV × (VADC + 0.5) where: VM is the measured value in volts. VADC is the 12-bit ADC code. LSBxV values are based on the voltage range (see Table 8). where: VCODE is the 12-bit ADC code. VA is the voltage value in volts. LSBxV values are based on the voltage range (see Table 8). Rev. 0 | Page 32 of 48 ADM1276 GPO2/ALERT2 PIN BEHAVIOR The ADM1276 provides a very flexible alert system, whereby one or more fault/warning conditions can be indicated to an external device. FAULTS AND WARNINGS A PMBus fault on the ADM1276 is always generated due to an analog event and causes a change in state in the hot swap output, turning it off. The three defined fault sources are as follows: • • • Undervoltage (UV) event detected on the UV pin. Overvoltage (OV) event detected on the OV pin. Overcurrent (OC) event that causes a hot swap timeout. Faults are continuously monitored, and, as long as power is applied to the device, they cannot be disabled. When a fault occurs, a corresponding status bit is set in one or more STATUS_xxx registers. the GPO2/ALERT2 pin active. By default, the active state of the GPO2/ALERT2 pin is low. For example, to use GPO2/ALERT2 to monitor the VOUT UV warning from the ADC, the followings steps must be performed: 1. 2. If a VOUT sample is taken that is below the configured VOUT UV value, the GPO2/ALERT2 pin is taken low, signaling an interrupt to a processor. HANDLING/CLEARING AN ALERT A value of 1 in a status register bit field always indicates a fault or warning condition. Fault and warning bits in the status registers are latched when set to 1. To clear a latched bit to 0— provided that the fault condition is no longer active—use the CLEAR_FAULTS command or use the OPERATION command to turn the hot swap output off and then on again. When faults/warnings are configured on the GPO2/ALERT2 pin, the pin becomes active to signal an interrupt to the processor. (The pin is active low, unless inversion is enabled.) The ALERT2 signal on the GPO2/ALERT2 pin functions as an SMBAlert. A processor can respond to the interrupt in one of two basic ways: • A warning is less severe than a fault and never causes a change in the state of the hot swap controller. The sources of a warning are defined as follows: • • • • • • • • • Set a threshold level with the VOUT_UV_WARN_LIMIT command. Start the power monitor sampling on VOUT. CML: a communications error occurred on the I2C bus. HS timer was active (HSTA): the current regulation was active, but did not necessarily shut the system down. IOUT OC warning from the ADC. IOUT Warning 2 from the ADC. VIN UV warning from the ADC. VIN OV warning from the ADC. VOUT UV warning from the ADC. VOUT OV warning from the ADC. PIN OP warning from the VIN × IOUT calculation. • GENERATING AN ALERT A host device can periodically poll the ADM1276 using the status commands to determine whether a fault/warning is active. However, this polling is very inefficient in terms of software and processor resources. The ADM1276 has a GPO2/ALERT2 output pin that can be used to generate interrupts to a host processor. If there is only one device on the bus, the processor can simply read the status bytes and issue a CLEAR_FAULTS command to clear all the status bits, which causes the deassertion of the GPO2/ALERT2 line. If there is a persistent fault—for example, an undervoltage on the input—the status bits remain set after the CLEAR_FAULTS command is executed because the fault has not been removed. However, the GPO2/ALERT2 line is not pulled low unless a new fault or warning becomes active. If the cause of the SMBAlert is a power monitor generated warning and the power monitor is running continuously, the next sample generates a new SMBAlert after the CLEAR_FAULTS command is issued. If there are several devices on the bus, the processor can issue an SMBus alert response address command to find out which device asserted the SMBAlert line. The processor can read the status bytes from that device and issue a CLEAR_FAULTS command. SMBus ALERT RESPONSE ADDRESS The SMBus alert response address (ARA) is a special address that can be used by the bus host to locate any devices that need to talk to it. A host typically uses a hardware interrupt pin to monitor the SMBus alert pins of a number of devices. When the host interrupt occurs, the host issues a message on the bus using the SMBus receive byte or receive byte with PEC protocol. By default at power-up, the open-drain GPO2/ALERT2 output is high impedance, so the pin can be pulled high through a resistor. The FET health bad warning is active by default on the GPO2/ALERT2 pin at power-up. Any one or more of the faults and warnings listed in the Faults and Warnings section can be enabled and cause an alert, making The special address used by the host is 0x0C. Any devices that have an SMBAlert signal return their own 7-bit address as the seven MSBs of the data byte. The LSB value is not used and can be either 1 or 0. The host reads the device address from the received data byte and proceeds to handle the alert condition. Rev. 0 | Page 33 of 48 ADM1276 More than one device may have an active SMBAlert signal and attempt to communicate with the host. In this case, the device with the lowest address dominates the bus and succeeds in transmitting its address to the host. The device that succeeds disables its SMBus alert signal. If the host sees that the SMBus alert signal is still low, it continues to read addresses until all devices that need to talk to it have successfully transmitted their addresses. EXAMPLE USE OF SMBus ALERT RESPONSE ADDRESS 2. 4. 5. 6. The full sequence of steps that occurs when an SMBAlert is generated and cleared is as follows: 1. 3. A fault or warning is enabled using the ALERT2_CONFIG command, and the corresponding status bit for the fault or warning changes from 0 to 1, indicating that the fault or warning has just become active. The GPO2/ALERT2 pin becomes active (low) to signal that an SMBAlert is active. Rev. 0 | Page 34 of 48 The host processor issues an SMBus alert response address command to determine which device has an active alert. If there are no other active alerts from devices with lower I2C addresses, this device makes the GPO2/ALERT2 pin inactive (high) during the no acknowledge bit period after it sends its address to the host processor. If the GPO2/ALERT2 pin stays low, the host processor must continue to issue SMBus alert response address commands to devices to find out the addresses of all devices whose status it must check. The ADM1276 continues to operate with the GPO2/ALERT2 pin inactive and the contents of the status bytes unchanged until the host reads the status bytes and clears them, or until a new fault occurs. That is, if a status bit for a fault/warning that is enabled on the GPO2/ALERT2 pin and that was not already active (equal to 1) changes from 0 to 1, a new alert is generated, causing the GPO2/ALERT2 pin to become active again. ADM1276 PMBus COMMAND REFERENCE Command codes are in hexadecimal format. Table 9. PMBus Command Summary Command Code 0x01 0x03 0x19 0x42 0x43 0x4A 0x57 0x58 0x6B 0x78 0x79 0x7A 0x7B 0x7C 0x80 0x86 0x88 0x8B 0x8C 0x97 0x98 0x99 0x9A 0x9B 0xD0 0xD1 0xD2 0xD3 0xD4 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC Command Name OPERATION CLEAR_FAULTS CAPABILITY VOUT_OV_WARN_LIMIT VOUT_UV_WARN_LIMIT IOUT_OC_WARN_LIMIT VIN_OV_WARN_LIMIT VIN_UV_WARN_LIMIT PIN_OP_WARN_LIMIT STATUS_BYTE STATUS_WORD STATUS_VOUT STATUS_IOUT STATUS_INPUT STATUS_MFR_SPECIFIC READ_EIN READ_VIN READ_VOUT READ_IOUT READ_PIN PMBUS_REVISION MFR_ID MFR_MODEL MFR_REVISION PEAK_IOUT PEAK_VIN PEAK_VOUT PMON_CONTROL PMON_CONFIG ALERT2_CONFIG IOUT_WARN2_LIMIT DEVICE_CONFIG POWER_CYCLE PEAK_PIN READ_PIN_EXT READ_EIN_EXT SMBus Transaction Type Read/write byte Send byte Read byte Read/write word Read/write word Read/write word Read/write word Read/write word Read/write word Read byte Read word Read byte Read byte Read byte Read byte Block read Read word Read word Read word Read word Read byte Block read Block read Block read Read/write word Read/write word Read/write word Read/write byte Read/write byte Read/write word Read/write word Read/write byte Send byte Read/write word Block read Block read Number of Data Bytes 1 0 1 2 2 2 2 2 2 1 2 1 1 1 1 1 (byte count) + 6 (data) 2 2 2 2 1 1 (byte count) + 3 (data) 1 (byte count) + 9 (data) 1 (byte count) + 1 (data) 2 2 2 1 1 2 2 1 0 2 1 (byte count) + 3 (data) 1 (byte count) + 8 (data) Rev. 0 | Page 35 of 48 Default Value at Reset 0x80 Not applicable 0xB0 0x0FFF 0x0000 0x0FFF 0x0FFF 0x0000 0x7FFF 0x00 0x0000 0x00 0x00 0x00 0x00 0x06, 0x0000, 0x00, 0x000000 0x0000 0x0000 0x0000 0x0000 0x22 0x03 + ASCII “ADI” 0x09 + ASCII “ADM1276-3” 0x01 + ASCII “0” 0x0000 0x0000 0x0000 0x01 0xAF 0x8000 0x0000 0x00 Not applicable 0x0000 0x03, 0x000000 0x08, 0x000000, 0x0000, 0x000000 ADM1276 OPERATION Code: 0x01, read/write byte. Value after reset: 0x80. Table 10. Bit Descriptions for OPERATION Command Bits [7] Bit Name On [6:0] Reserved Settings 0 1 0000000 Description Hot swap output is disabled. Default. Hot swap output is enabled. Always reads as 0000000. CLEAR_FAULTS Code: 0x03, send byte, no data. CAPABILITY Code: 0x19, read byte. Value after reset: 0xB0. Table 11. Bit Descriptions for CAPABILITY Command Bits [7] [6:5] [4] [3:0] Bit Name Packet error checking Maximum bus speed SMBALERT# Reserved Settings 1 01 1 0000 Description Always reads as 1. Packet error checking (PEC) is supported. Always reads as 01. Maximum supported bus speed is 400 kHz. Always reads as 1. Device supports SMBAlert and alert response address (ARA). Always reads as 0000. VOUT_OV_WARN_LIMIT Code: 0x42, read/write word. Value after reset: 0x0FFF. Table 12. Bit Descriptions for VOUT_OV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VOUT_OV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overvoltage threshold for the VOUT pin measurement, expressed in ADC codes. VOUT_UV_WARN_LIMIT Code: 0x43, read/write word. Value after reset: 0x0000. Table 13. Bit Descriptions for VOUT_UV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VOUT_UV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Undervoltage threshold for the VOUT pin measurement, expressed in ADC codes. IOUT_OC_WARN_LIMIT Code: 0x4A, read/write word. Value after reset: 0x0FFF. Table 14. Bit Descriptions for IOUT_OC_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved IOUT_OC_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overcurrent threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. IOUT_WARN2_LIMIT Code: 0xD7, read/write word. Value after reset: 0x0000. Table 15. Bit Descriptions for IOUT_WARN2_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved IOUT_WARN2_LIMIT Settings 0000 Description Always reads as 0000. Threshold for the IOUT measurement through the sense resistor, expressed in ADC codes. This value can be either an undercurrent or an overcurrent, depending on the state of the IOUT_WARN2_SELECT bit that is set using the DEVICE_CONFIG command. Rev. 0 | Page 36 of 48 ADM1276 VIN_OV_WARN_LIMIT Code: 0x57, read/write word. Value after reset: 0x0FFF. Table 16. Bit Descriptions for VIN_OV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VIN_OV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Overvoltage threshold for the SENSE+ pin measurement, expressed in ADC codes. VIN_UV_WARN_LIMIT Code: 0x58, read/write word. Value after reset: 0x0000. Table 17. Bit Descriptions for VIN_UV_WARN_LIMIT Command Bits [15:12] [11:0] Bit Name Reserved VIN_UV_WARN_LIMIT Settings 0000 Description Always reads as 0000. Undervoltage threshold for the SENSE+ pin measurement, expressed in ADC codes. PIN_OP_WARN_LIMIT Code: 0x6B, read/write word. Value after reset: 0x7FFF. Table 18. Bit Descriptions for PIN_OP_WARN_LIMIT Command Bits [15] [14:0] Bit Name Reserved PIN_OP_WARN_LIMIT Settings 0 Description Always reads as 0. Overpower threshold for the VIN × IOUT power calculation. STATUS_BYTE Code: 0x78, read byte. Value after reset: 0x00. Table 19. Bit Descriptions for STATUS_BYTE Command Bits [7] [6] Bit Name Reserved HOTSWAP_OFF Behavior Live [5] [4] Reserved IOUT_OC_FAULT Latched [3] VIN_UV_FAULT Latched [2] [1] Reserved CML_ERROR Latched [0] NONE_OF_THE_ABOVE Live Settings 0 0 1 0 0 1 0 1 0 0 1 0 1 Description Always reads as 0. The hot swap gate drive output is enabled. The hot swap gate drive output is disabled, and the GATE pin is pulled down. This can be due to, for example, an overcurrent fault that causes the ADM1276 to latch off, an undervoltage condition on the UV pin, or the use of the OPERATION command to turn the output off. Always reads as 0. No overcurrent output fault detected. The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down. No undervoltage input fault detected on the UV pin. An undervoltage input fault was detected on the UV pin. Always reads as 0. No communications error detected on the I2C/PMBus interface. An error was detected on the I2C/PMBus interface. Errors detected are an unsupported command, an invalid PEC byte, and an incorrectly structured message. No other active status bit to be reported by any other status command. Active status bits are waiting to be read by one or more status commands. Rev. 0 | Page 37 of 48 ADM1276 STATUS_WORD Code: 0x79, read word. Value after reset: 0x0000. Table 20. Bit Descriptions for STATUS_WORD Command Bits [15] Bit Name VOUT_STATUS Behavior Live [14] IOUT_STATUS Live [13] INPUT_STATUS Live [12] MFR_STATUS Live [11] POWER_GOOD# Live Settings 0 1 0 1 0 1 0 1 0 1 [10:8] [7:0] Reserved STATUS_BYTE 000 Description There are no active status bits to be read by STATUS_VOUT. There are one or more active status bits to be read by STATUS_VOUT. There are no active status bits to be read by STATUS_IOUT. There are one or more active status bits to be read by STATUS_IOUT. There are no active status bits to be read by STATUS_INPUT. There are one or more active status bits to be read by STATUS_INPUT. There are no active status bits to be read by STATUS_MFR_SPECIFIC. There are one or more active status bits to be read by STATUS_MFR_SPECIFIC. The voltage on the FLB pin is above the required threshold, indicating that output power is considered good. This bit is the logical inversion of the PWRGD pin on the part. The voltage on the FLB pin is below the required threshold, indicating that output power is considered bad. Always reads as 000. This byte is the same as the byte returned by the STATUS_BYTE command. STATUS_VOUT Code: 0x7A, read byte. Value after reset: 0x00. Table 21. Bit Descriptions for STATUS_VOUT Command Bits [7] [6] Bit Name Reserved VOUT_OV_WARN Behavior Latched Settings 0 0 1 [5] VOUT_UV_WARN Latched 0 1 [4:0] Reserved 00000 Description Always reads as 0. No overvoltage condition on the output supply detected by the power monitor. An overvoltage condition on the output supply was detected by the power monitor. No undervoltage condition on the output supply detected by the power monitor. An undervoltage condition on the output supply was detected by the power monitor. Always reads as 00000. STATUS_IOUT Code: 0x7B, read byte. Value after reset: 0x00. Table 22. Bit Descriptions for STATUS_IOUT Command Bits [7] Bit Name IOUT_OC_FAULT [6] [5] Reserved IOUT_OC_WARN Behavior Latched Latched Settings 0 1 0 0 1 [4:0] Reserved 00000 Description No overcurrent output fault detected. The hot swap controller detected an overcurrent condition and the time limit set by the capacitor on the TIMER pin has elapsed, causing the hot swap gate drive to shut down. Always reads as 0. No overcurrent condition on the output supply detected by the power monitor using the IOUT_OC_WARN_LIMIT command. An overcurrent condition was detected by the power monitor using the IOUT_OC_WARN_LIMIT command. Always reads as 00000. Rev. 0 | Page 38 of 48 ADM1276 STATUS_INPUT Code: 0x7C, read byte. Value after reset: 0x00. Table 23. Bit Descriptions for STATUS_INPUT Command Bits [7] Bit Name VIN_OV_FAULT Behavior Latched [6] VIN_OV_WARN Latched Settings 0 1 0 1 [5] VIN_UV_WARN Latched 0 1 [4] VIN_UV_FAULT Latched [3:1] [0] Reserved PIN_OP_WARN Latched 0 1 000 0 1 Description No overvoltage detected on the OV pin. An overvoltage was detected on the OV pin. No overvoltage condition on the input supply detected by the power monitor. An overvoltage condition on the input supply was detected by the power monitor. No undervoltage condition on the input supply detected by the power monitor. An undervoltage condition on the input supply was detected by the power monitor. No undervoltage detected on the UV pin. An undervoltage was detected on the UV pin. Always reads as 000. No overpower condition on the input supply detected by the power monitor. An overpower condition on the input supply was detected by the power monitor. STATUS_MFR_SPECIFIC Code: 0x80, read byte. Value after reset: 0x00. Table 24. Bit Descriptions for STATUS_MFR_SPECIFIC Command Bits [7] Bit Name FET_HEALTH_BAD Behavior Latched [6] UV_CMP_OUT Live [5] OV_CMP_OUT Live [4] [3] Reserved HS_INLIM Latched [2:1] HS_SHUTDOWN_CAUSE Latched Settings 0 1 0 1 0 1 0 0 1 00 01 [0] IOUT_WARN2 Latched 10 11 0 1 Description FET behavior appears to be as expected. FET behavior suggests that the FET may be shorted. Input voltage to UV pin is above threshold. Input voltage to UV pin is below threshold. Input voltage to OV pin is below threshold. Input voltage to OV pin is above threshold. Always reads as 0. The ADM1276 has not actively limited the current into the load. The ADM1276 has actively limited current into the load. This bit differs from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately, whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the capacitor on the TIMER pin elapses. The ADM1276 is either enabled and working correctly, or has been shut down using the OPERATION command. An IOUT_OC_FAULT condition occurred that caused the ADM1276 to shut down. A VIN_UV_FAULT condition occurred that caused the ADM1276 to shut down. A VIN_OV_FAULT condition occurred that caused the ADM1276 to shut down. No overcurrent condition on the output supply detected by the power monitor using the IOUT_WARN2_LIMIT command. An undercurrent or overcurrent condition on the output supply was detected by the power monitor using the IOUT_WARN2_LIMIT command. The polarity of the threshold condition is set by the IOUT_WARN2_SELECT bit using the DEVICE_CONFIG command. Rev. 0 | Page 39 of 48 ADM1276 READ_EIN Code: 0x86, block read. Value after reset: 0x06, 0x0000, 0x00, 0x000000. Table 25. Byte Descriptions for READ_EIN Command Byte [0] Byte Name Byte count Value 0x06 [2:1] Energy count 0x0000 [3] Rollover count 0x00 [6:4] Sample count 0x000000 Description Always reads as 0x06, the number of data bytes that the block read command should expect to read. Energy accumulator value in direct format. Byte 2 is the high byte, and Byte 1 is the low byte. Internally, the energy accumulator is a 24-bit value, but only the most significant 16 bits are returned with this command. Use the READ_EIN_EXT command to access the nontruncated version. Number of times that the energy count has rolled over from 0x7FFF to 0x0000. This is a straight 8-bit binary value. This is the total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 6 is the high byte, Byte 5 is the middle byte, and Byte 4 is the low byte. This is a straight 24-bit binary value. READ_VIN Code: 0x88, read word. Value after reset: 0x0000. Table 26. Bit Descriptions for READ_VIN Command Bits [15:12] [11:0] Bit Name Reserved VIN Settings 0000 Description Always reads as 0000. Input voltage from the SENSE+ pin measurement, expressed in ADC codes. READ_VOUT Code: 0x8B, read word. Value after reset: 0x0000. Table 27. Bit Descriptions for READ_VOUT Command Bits [15:12] [11:0] Bit Name Reserved VOUT Settings 0000 Description Always reads as 0000. Output voltage from the VOUT pin measurement, expressed in ADC codes. READ_IOUT Code: 0x8C, read word. Value after reset: 0x0000. Table 28. Bit Descriptions for READ_IOUT Command Bits [15:12] [11:0] Bit Name Reserved IOUT Settings 0000 Description Always reads as 0000. Output current from the measurement through the sense resistor, expressed in ADC codes. READ_PIN Code: 0x97, read word. Value after reset: 0x0000. Table 29. Bit Descriptions for READ_PIN Command Bits [15] [14:0] Bit Name Reserved PIN Settings 0 Description Always reads as 0. Input power from the VIN × IOUT calculation. PMBUS_REVISION Code: 0x98, read byte. Value after reset: 0x22. Table 30. Bit Descriptions for PMBUS_REVISION Command Bits [7:4] [3:0] Bit Name Part I revision Part II revision Settings 0010 0010 Description Always reads as 0010, PMBus Specification Part I, Revision 1.2. Always reads as 0010, PMBus Specification Part II, Revision 1.2. Rev. 0 | Page 40 of 48 ADM1276 MFR_ID Code: 0x99, block read. Value after reset: 0x03 + ASCII “ADI.” Table 31. Byte Descriptions for MFR_ID Command Byte [0] Byte Name Byte count Value 0x03 [1] [2] [3] Character 1 Character 2 Character 3 0x41 or “A” 0x44 or “D” 0x49 or “I” Description Always reads as 0x03, the number of data bytes that the block read command expects to read. Always reads as 0x41. Always reads as 0x44. Always reads as 0x49. MFR_MODEL Code: 0x9A, block read. Value after reset: 0x09 + ASCII “ADM1276-3.” Table 32. Byte Descriptions for MFR_MODEL Command Byte [0] Byte Name Byte count Value 0x09 [1] [2] [3] [4] [5] [6] [7] [8] [9] Character 1 Character 2 Character 3 Character 4 Character 5 Character 6 Character 7 Character 8 Character 9 0x41 or “A” 0x44 or “D” 0x4D or “M” 0x31 or “1” 0x32 or “2” 0x37 or “7” 0x36 or “6” 0x2D or “–“ 0x33 or “3” Description Always reads as 0x09, the number of data bytes that the block read command expects to read. Always reads as 0x41. Always reads as 0x44. Always reads as 0x4D. Always reads as 0x31. Always reads as 0x32. Always reads as 0x37. Always reads as 0x36. Always reads as 0x2D. Always reads as 0x33. MFR_REVISION Code: 0x9B, block read. Value after reset: 0x01 + ASCII “0.” Table 33. Byte Descriptions for MFR_REVISION Command Byte [0] Byte Name Byte count Value 0x01 [1] Character 1 0x30 or “0” Description Always reads as 0x01, the number of data bytes that the block read command expects to read. Always reads as 0x30, Revision 0 of the ADM1276. PEAK_IOUT Code: 0xD0, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 34. Bit Descriptions for PEAK_IOUT Command Bits [15:12] [11:0] Bit Name Reserved PEAK_IOUT Settings 0000 Description Always reads as 0000. Returns the peak IOUT current since the register was last cleared. PEAK_VIN Code: 0xD1, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 35. Bit Descriptions for PEAK_VIN Command Bits [15:12] [11:0] Bit Name Reserved PEAK_VIN Settings 0000 Description Always reads as 0000. Returns the peak VIN voltage since the register was last cleared. Rev. 0 | Page 41 of 48 ADM1276 PEAK_VOUT Code: 0xD2, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 36. Bit Descriptions for PEAK_VOUT Command Bits [15:12] [11:0] Bit Name Reserved PEAK_VOUT Settings 0000 Description Always reads as 0000. Returns the peak VOUT voltage since the register was last cleared. PMON_CONTROL Code: 0xD3, read/write byte. Value after reset: 0x01. Table 37. Bit Descriptions for PMON_CONTROL Command Bits [7:1] [0] Bit Name Reserved Convert Settings 0000000 0 1 Description Always reads as 0000000. Power monitor is not running. Default. Start the sampling of current and voltage with the power monitor. In single shot mode, this bit clears itself after one complete cycle. In continuous mode, this bit must be written to 0 to stop sampling. PMON_CONFIG Code: 0xD4, read/write byte. Value after reset: 0xAF. Modifying the power monitor settings while the power monitor is sampling is not supported. The power monitor must be stopped before any setting in Table 38 is changed to ensure correct operation and to prevent the generation of any potential spurious data and status alerts. Table 38. Bit Descriptions for PMON_CONFIG Command Bits [7] Bit Name PMON_MODE [6] VOUT_SELECT [5] VRANGE [4] [3] Reserved Reserved [2:0] Averaging Settings 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111 Description This setting selects single shot sampling mode. Default. This setting selects continuous sampling mode. Default. The power monitor samples the input voltage on the SENSE+ pin and IOUT. The power monitor samples the input voltage on the SENSE+ pin, IOUT, and the voltage on the VOUT pin. Sets the voltage input range from 0 V to 6 V (low input voltage range). Default. Sets the voltage input range from 0 V to 20 V (high input voltage range). Reserved. This bit must always be written as 0. Default. This bit must be set to 1 for the power monitor current sense to operate correctly. Disables sample averaging for current and voltage. Sets sample averaging for current and voltage to two samples. Sets sample averaging for current and voltage to four samples. Sets sample averaging for current and voltage to eight samples. Sets sample averaging for current and voltage to 16 samples. Sets sample averaging for current and voltage to 32 samples. Sets sample averaging for current and voltage to 64 samples. Default. Sets sample averaging for current and voltage to 128 samples. Rev. 0 | Page 42 of 48 ADM1276 ALERT2_CONFIG Code: 0xD6, read/write word. Value after reset: 0x8000. Table 39. Bit Descriptions for ALERT2_CONFIG Command Bits [15] Bit Name FET_HEALTH_BAD_EN2 Settings 0 1 [14] IOUT_OC_FAULT_EN2 [13] VIN_OV_FAULT_EN2 [12] VIN_UV_FAULT_EN2 [11] CML_ERROR_EN2 [10] IOUT_OC_WARN_EN2 [9] IOUT_WARN2_EN2 [8] VIN_OV_WARN_EN2 [7] VIN_UV_WARN_EN2 [6] VOUT_OV_WARN_EN2 [5] VOUT_UV_WARN_EN2 [4] HS_INLIM_EN2 [3] PIN_OP_WARN_EN2 [2:1] GPO2_MODE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00 01 10 11 [0] GPO2_INVERT 0 1 Description Disables generation of an SMBAlert when the FET_HEALTH_BAD bit is set. Default. Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active from power-up for a FET problem to be detected and flagged immediately without the need for software to set this bit. Default. Disables generation of an SMBAlert when the IOUT_OC_FAULT bit is set. Generates an SMBAlert when the IOUT_OC_FAULT bit is set. Default. Disables generation of an SMBAlert when the VIN_OV_FAULT bit is set. Generates an SMBAlert when the VIN_OV_FAULT bit is set. Default. Disables generation of an SMBAlert when the VIN_UV_FAULT bit is set. Generates an SMBAlert when the VIN_UV_FAULT bit is set. Default. Disables generation of an SMBAlert when the CML_ERROR bit is set. Generates an SMBAlert when the CML_ERROR bit is set. Default. Disables generation of an SMBAlert when the IOUT_OC_WARN bit is set. Generates an SMBAlert when the IOUT_OC_WARN bit is set. Default. Disables generation of an SMBAlert when the IOUT_WARN2 bit is set. Generates an SMBAlert when the IOUT_WARN2 bit is set. Default. Disables generation of an SMBAlert when the VIN_OV_WARN bit is set. Generates an SMBAlert when the VIN_OV_WARN bit is set. Default. Disables generation of an SMBAlert when the VIN_UV_WARN bit is set. Generates an SMBAlert when the VIN_UV_WARN bit is set. Default. Disables generation of an SMBAlert when the VOUT_OV_WARN bit is set. Generates an SMBAlert when the VOUT_OV_WARN bit is set. Default. Disables generation of an SMBAlert when the VOUT_UV_WARN bit is set. Generates an SMBAlert when the VOUT_UV_WARN bit is set. Default. Disables generation of an SMBAlert when the HS_INLIM bit is set. Generates an SMBAlert when the HS_INLIM bit is set. Default. Disables generation of an SMBAlert when the PIN_OP_WARN bit is set. Generates an SMBAlert when the PIN_OP_WARN bit is set. Default. GPO2 is configured to generate SMBAlerts. GPO2 can be used as a general-purpose digital output pin. The GPO2_INVERT bit is used to change the output state. Reserved. GPO2 is configured for digital comparator mode. The output pin continuously shows for the selected warning(s) if the relevant warning threshold has been exceeded. In effect, this is an unlatched SMBAlert. If multiple bits are selected, the output values are OR’ed together. Only warning threshold comparisons affect the pin in this mode. If other bits such as VIN_UV_FAULT_EN2 are set, they are ignored in this mode of operation. Default. The GPO2 pin is active low. GPO2 is active high. Rev. 0 | Page 43 of 48 ADM1276 DEVICE_CONFIG Code: 0xD8, read/write byte. Value after reset: 0x00. Table 40. Bit Descriptions for DEVICE_CONFIG Command Bits [7] Bit Name OC_GLITCH_TIME Settings 0 [6] FLB_DISABLE 1 0 1 [5] OPERATION_CMD_EN 0 [4] IOUT_WARN2_SELECT [3:0] Reserved 1 0 1 0000 Description Default. The long duration glitch filter is used when a severe overcurrent fault is detected. The short duration glitch filter is used when a severe overcurrent fault is detected. Default. Foldback is enabled and can affect the hot swap current sense limit. Foldback is disabled and does not affect the hot swap current sense limit. This setting can be useful if the sole purpose of the FLB pin is to act as a power-good input. Default. The OPERATION command is disabled, and the ADM1276 issues a no acknowledge if the command is received. This setting provides some protection against a card accidentally turning itself off. The OPERATION command is enabled, and the ADM1276 responds to it. Default. Configures IOUT_WARN2_LIMIT as an undercurrent threshold. Configures IOUT_WARN2_LIMIT as an overcurrent threshold. Always reads as 0000. POWER_CYCLE Code: 0xD9, send byte, no data. PEAK_PIN Code: 0xDA, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value). Table 41. Bit Descriptions for PEAK_PIN Command Bits [15] [14:0] Bit Name Reserved PEAK_PIN Settings 0 Description Always reads as 0. Returns the peak input power since the register was last cleared. READ_PIN_EXT Code: 0xDB, block read. Value after reset: 0x03, 0x000000. Table 42. Byte Descriptions for READ_PIN_EXT Command Byte [0] Byte Name Byte count Value 0x03 [3:1] PIN extended 0x000000 Description Always reads as 0x03, the number of data bytes that the block read command expects to read. Result of the VIN × IOUT calculation that has not been truncated. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte. READ_EIN_EXT Code: 0xDC, block read. Value after reset: 0x08, 0x000000, 0x0000, 0x000000. Table 43. Byte Descriptions for READ_EIN_EXT Command Byte [0] Byte Name Byte count Value 0x08 [3:1] Energy count extended 0x000000 [5:4] Rollover count extended 0x0000 [8:6] Sample count 0x000000 Description Always reads as 0x08, the number of data bytes that the block read command expects to read. 24-bit energy accumulator in direct format. Byte 3 is the high byte, Byte 2 is the middle byte, and Byte 1 is the low byte. Number of times that the energy counter has rolled over from 0x7FFF to 0x0000. This is a straight 16-bit binary value. Byte 5 is the high byte, and Byte 4 is the low byte. Total number of PIN samples acquired and accumulated in the energy count accumulator. Byte 8 is the high byte, Byte 7 is the middle byte, and Byte 6 is the low byte. Rev. 0 | Page 44 of 48 ADM1276 OUTLINE DIMENSIONS PIN 1 INDICATOR 5.10 5.00 SQ 4.90 0.35 0.28 0.23 0.65 BSC 20 16 15 1 EXPOSED PAD 5 PIN 1 INDICATOR 3.25 3.10 SQ 2.95 11 0.80 0.75 0.70 0.70 0.60 0.40 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHC. 111908-A TOP VIEW Figure 61. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-20-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADM1276-3ACPZ ADM1276-3ACPZ-RL 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Lead LFCSP_WQ 20-Lead LFCSP_WQ Z = RoHS Compliant Part. Rev. 0 | Page 45 of 48 Package Option CP-20-9 CP-20-9 ADM1276 NOTES Rev. 0 | Page 46 of 48 ADM1276 NOTES Rev. 0 | Page 47 of 48 ADM1276 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09718-0-3/11(0) Rev. 0 | Page 48 of 48