INTEGRATED CIRCUITS
SA2400A
Single chip transceiver for
2.45 GHz ISM band
Product data
2002 Nov 04
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
• An I/Q upconverter from baseband directly to 2.45 GHz, with
1. DESCRIPTION
The SA2400A is a fully integrated single IC RF transceiver designed
for 2.45 GHz wireless LAN (WLAN) applications. It is a direct
conversion radio architecture that is fabricated on an advanced
30 GHz fT BiCMOS process. The SA2400A combines a receiver,
transmitter, and LO generation into a single IC. The receiver
consists of a low-noise amplifier, down-conversion mixers, fully
integrated channel filters, and an Automatic Gain Control (AGC) with
an on-chip closed loop. The transmitter contains power ramping,
filters, up-conversion, and pre-drivers. The LO generation is formed
by an entirely on-chip VCO and a fractional-N synthesizer.
+8 dBm output power, –40 dBc typical carrier leakage (calibrated)
and 3 µs (typical) Rx to Tx switching time, and comprising the
following:
– Wide band IQ modulator producing better than 14% EVM for
11 Msymbols/s QPSK modulation
– Integrated reconstruction and spectral shaping filters at I and Q
modulation input that is driven by an external D/A. High
common mode rejection to input ground bounce.
– FIR-DACs for digital I/Q input feeding the analog signal path
and including additional filtering for spectral shaping.
Typical system performance parameters for the receiver are 93 dB
gain, 7.5 dB noise figure, input-referred third-order intercept point
(IIP3) of +1 dBm, AGC settling time of 8 µs, and Tx-to-Rx switching
time of 3 µs. The transmitter typical system performance parameters
are an output power range from –7 dBm to +8 dBm in 1 dB steps,
–40 dBc carrier leakage after calibration, 22 dB sideband
suppression, in-band common mode rejection of 30 dB, and
Rx-to-Tx switching time of 3 µs.
– 2.45 GHz power amplifier driver with +8 dBm maximum output,
15 dB adjustable gain in 1 dB steps and a second switched
output at –1.5 dBm power level with similar gain adjustments
that are set by a separate register.
– Completely on-chip calibration for Carrier Leakage
compensation.
– Internal power ramping with 2 µs delay and 0.5 µs ramp-up
time.
• A fractional-N frequency synthesizer with on-chip VCO and XO
• A 3-wire bus for control of most blocks
• An additional high speed 3-wire bus for full control of Rx-Gain and
2. FUNCTIONAL BLOCKS AND FEATURES
The block diagram of the SA2400A Direct Conversion transceiver is
given in Figure 1. It consists of the following functional blocks:
• A 79 dB adjustable gain range direct conversion zero IF receiver
DC-offset compensation parameters with 44Mbits/s.
with 3 µs (typical) Tx to Rx switching time, and comprising the
following:
• Fast Tx-Rx switching based on a single digital input pin.
• Reference currents and voltage for supply of Baseband Processor
– Front-end LNA with two internal gain states
and PA-chip.
– A fast on-chip closed loop composite RF and IF AGC with
zoomed analog RSSI output and 8 µs settling time
– Quadrature downconverters from 2.45 GHz RF directly to
zero IF
3. APPLICATIONS
• IEEE 802.11 and 802.11b radios
– On-chip fast baseband DC cancellation with automatically
stepped bandwidths of 10 MHz, 1 MHz, 100 kHz, and 10 kHz,
settling within 8–13 µs for a DC error of 10% that decays to 1%.
– Supports DSSS and CCK modulation
– Supports data rates: 1, 2, 5.5, and 11 Mbps
– Fully integrated channel filters, appropriate for 11 Msymbols/s
QPSK modulation RF bandwidth.
• 2.45 GHz ISM band wireless communication devices
Table 1. Ordering Information
PACKAGE
TYPE NUMBER
SA2400ABE
2002 Nov 04
NAME
DESCRIPTION
VERSION
LQFP48
plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
2
853-2320 28727
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
4. BLOCK DIAGRAM
2
RX_OUT_I
A/D
RSSI
2
RSSI
RF_IN
2
RX_OUT_Q
AGCRESET
AGC
STATE MACHINE
AGCSET
0
SEN
SCLK
SDATA
CONTROL
90
TXRX
:2
FILTER
TUNING
TX_HI
0
V_TUNE
PLL
90
XO
CP
LOCK
XTAL
2
2
2
TX_OUT_HI
FIRDAC
DATA_I
FIRDAC
DATA_Q
2
TX_OUT_LO
A/D
D/A
POWER
DETECTOR
TXCAL
STATE MACHINE
D/A
SR02386
Figure 1. SA2400A functional block diagram.
2002 Nov 04
3
REF_CLK
TX_IN_I
TX_IN_Q
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
A_GND
TX_HI
A_V DD
TX_OUT_LO
A_GND
TX_OUT_HI_P
TX_OUT_HI_M
A_GND
SEN
SDATA
SCLK
TX/RX
48
47
46
45
44
43
42
41
40
39
38
37
5. PINNING INFORMATION
AGCRESET
1
36
TX_IN_I_P/
TX_DATA_I
AGCSET
2
35
TX_IN_I_M/
TX_DATA_Q
IDCOUT
3
34
TX_IN_Q_P
A_GND
4
33
TX_IN_Q_M
GND_LNA
5
32
A_V DD
RF_IN_P
6
31
RX_OUT_Q_P
RF_IN_N
7
30
RX_OUT_Q_M
GND_LNA
8
29
RX_OUT_I_P
A_V DD
9
28
RX_OUT_I_M
TEST1
10
27
D_GND
TEST2
11
26
REF_CLK_OUT
V_2P5
12
25
PLL_GND
13
14
15
16
17
18
19
20
21
22
23
24
RSSI
D_VDD
V_TUNE
VCO_GND
VCO_VDD
VCO_P
VCO_M
VDD _PLL
CP
LOCK
XTAL_1
XTAL_2
SA2400A
Figure 2. Pin configuration.
2002 Nov 04
4
SR02387
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 2. Pin description
PIN type is designated by A = Analog, D = Digital, I = Input, O = Output
SYMBOL
PIN
DESCRIPTION
TYPE
SYMBOL
PIN
DESCRIPTION
TYPE
AGCRESET
1
AGC start input
DI
PLL_GND
25
Synthesizer Ground
AGCSET
2
AGC settled output
DO
REF_CLK_OUT
26
Reference clock output
AO
D_GND
27
Digital and Analog Ground
RX_OUT_I_M
28
Receive output
AO
RX_OUT_I_P
29
Receive output
AO
AO
IDCOUT
3
Tx-mode:
DC reference current
A_GND
4
Analog Ground
GND_LNA
5
Analog Ground
RX_OUT_Q_M
30
Receive output
AO
RF_IN_P
6
RF input (positive)
AI
RX_OUT_Q_P
31
Receive output
AO
RF_IN_N
7
RF input (negative)
AI
A_VDD
32
Analog Supply
GND_LNA
8
Analog Ground
TX_IN_Q_M
33
Transmit input
AI
A_VDD
9
Analog Supply
TX_IN_Q_P
34
Transmit input
AI
TEST_1
10
Test pin
Transmit input
AI/DI
11
Test pin
TX_IN_I_M/
TX_DATA_Q
35
TEST_2
V_2P5
12
DC reference voltage
AO
TX_IN_I_P/
TX_DATA_I
36
Transmit input
AI/DI
RSSI
13
RSSI output signal
AO
TX/RX
37
Tx/Rx mode select
DI
D_VDD
14
Digital Supply
SCLK
38
Three-wire bus clock
DI
V_TUNE
15
VCO tuning voltage
SDATA
39
Three wire bus data
DI/O
VCO_GND
16
VCO ground
SEN
40
Three wire bus enable
DI
VCO_VDD
17
VCO Supply
A_GND
41
Analog Ground
VCO_P
18
VCO output/
External VCO input
TX_OUT_HI_M
42
Transmit output, high power
AO
TX_OUT_HI_P
43
Transmit output, high power
AO
A_GND
44
Analog Ground
TX_OUT_LO
45
Transmit output, low power
AO
A_VDD
46
Analog Supply
TX_HI
47
Transmit output power level
select
A_GND
48
Analog Ground
VCO_M
19
VCO output/
External VCO input
VDD_PLL
20
Synthesizer Supply
CP
21
Charge pump output
AI
AI/O
AI/O
LOCK
22
Synthesizer lock indicator
AO
XTAL_1
23
Crystal input
AI
XTAL_2
24
Crystal input
AI
2002 Nov 04
5
AO
DI
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
high-pass will then remain set to the 10 kHz cutoff frequency until a
new AGC cycle is started.
6. FUNCTIONAL DESCRIPTION
The SA2400A transceiver is intended for operation in the 2.45 GHz
band, specifically for IEEE 802.11b 1 and 2 Mbits/s DSSS, and
5.5 and 11 Mbits/s CCK standards. Throughout this document, the
operating RF frequency refers to the ISM band between 2.4 GHz
and 2.5 GHz.
Whenever there is a frequency change in the high-pass filter lower
cutoff, the DC offset can change from a very low value to about 50%
(1 MHz ≥ 100 kHz step) or 10% (100 kHz ≥ 10 kHz step) of the
signal level. This DC offset then decays according to the high-pass
response of the filter.
6.1 RF VCO
The cutoff frequency of the high-pass filter can also be selected
manually by using the RXMGC mode.
The local oscillator is common to both the transmitter and the
receiver. The RF VCO is a differential 4.8 GHz oscillator with the
frequency determining components internal to the IC. The VCO is
connected internally to a frequency divider and a quadrature
generator circuit which produces the LO for the IQ up- and
downmixer. The divider output is also internally connected to the
synthesizer, which can be programmed in order to produce steps of
0.5 MHz for the desired LO frequency.
6.6 AGC
The receiver contains a fully integrated Automatic Gain Control loop.
It works by adjusting the internal gain such that the Rx output
amplitude, as measured by the RSSI (see below), meets a
predefined target value.
By default, the AGC is always set to a default maximum gain
(adjustable by register value GMAX) whenever the SA2400A enters
the RECEIVE mode of operation from another operational mode. It
takes 5 µs for the receiver to settle when it enters this mode, which
includes the time for DC offsets to be removed with a 1 MHz lower
cut-off frequency of the high-pass filtering. This lower cut-off
frequency of 1 MHz remains unchanged as long as the AGC
remains in the default maximum gain state.
At the time of power-up, the VCO must be calibrated by invoking the
VCOCALIB mode by means of the three-wire bus. This operation
will select an appropriate frequency band in the VCO, thus
compensating for process tolerances. The calibration takes up to
2.2 ms, after which the IC automatically enters the SLEEP mode.
The synthesizer registers 0x00 through 0x03 must be
re-programmed after completing the VCOCALIB.
The 2.45 GHz LO can also be injected externally.
The AGC must be invoked by providing a 0-to-1 transition on the
AGCRESET pin, and keeping the signal on that pin to 1 for at least
5 µs.
6.2 RF Low Noise Amplifier
The RF LNA has differential inputs and an external balun is needed
in the case of single-ended operation. It has two gain states which
are controlled internally by the on-chip automatic gain control, or
manually via the 3-wire bus.
By successively reducing the gain from its initial maximum value,
the loop searches for the correct gain value to provide a nominal
output amplitude of 500 mVpeak, differential for a QPSK signal (within
±3 dB dynamic error) at the output pins. This is achieved after a
maximum of 8 µs. This time is defined by wait periods necessary to
settle the receiver after gain switching actions. The individual wait
periods can be adjusted by means of register settings.
6.3 Downconversion mixers
The RF signal is converted down directly to baseband by quadrature
image-reject mixers.
6.4 Receiver low-pass filter, baseband amplifiers
After completing the AGC settling process, the AGCSET pin is set to
1 by the algorithm. The receiver gain then will not change again until
another pulse is issued on the AGCRESET pin.
The I and Q low-pass filters are fully integrated Chebychev active
filters. The I and Q pass band extends from DC to a –3 dB corner at
7 MHz.
For a subsequent AGC operation, the receiver needs to enter its
maximum gain state again. If another AGCRESET signal (as
described above) is issued, the settling period will take an extra
3 µs, up to a total of 11 µs, since the first 3 µs will be spent on
entering maximum gain mode and settling the receiver thereafter. To
shorten this operation, the receiver can be forced to maximum gain
(e.g., at a time when no signal is present) by issuing a 0–1–0 pulse
of maximum 1 µs pulse width on the AGCRESET pin. The receiver
will then enter maximum gain mode (the AGCSET signal will not be
set to 1 after this), and a following 0-to-1 transition on the
AGCRESET pin will start the settling sequence from maximum gain,
which will then take a maximum of 8 µs.
Additional adjustable gain is provided in baseband amplifiers to
achieve a total adjustable gain range of 79 dB. The Rx output is
provided in the form of differential I and Q signals, which must be
DC coupled to the ADC inputs on a base band IC.
6.5 DC cancellation
The Rx chain also integrates a high-pass filter (DC notch) for
cancellation of the DC offset inherent to zero-IF operation. The
high-pass filter has a programmable lower 3 dB cutoff frequency of
10 MHz, 1 MHz, 100 kHz or 10 kHz. The DC offset cancellation
occurs simultaneously with the AGC settling process. During the
AGC settling phase (see below) the cutoff frequency is dynamically
selected between 10 MHz and 1 MHz to quickly reduce DC offset
values from +50 dBc to below –20 dBc relative to a –76 dBm
antenna input signal before the RSSI (see below) is internally
sampled. After the AGC settling, the high pass is configured for
100 kHz for 5 µs before switching to a final 10 kHz cutoff frequency.
The low value of 10 kHz is required for minimizing the signal
distortion created by a high-pass function at zero frequency. The
2002 Nov 04
SA2400A
The receiver gain can also be selected manually by using the
RXMGC mode.
The settling target can be adjusted by ±7 dB from the nominal level
of 500 mVpeak, differential by means of register settings.
Note: When doing measurements with a single-tone RF signal, the
amplitude at the Rx outputs after settling the AGC will be lower, at
about 300 mVpeak, differential.
6
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
streams. In this case, integrated FIR–DACS provide additional
filtering. The data streams are sampled with the reference clock. For
timing specifications, please see the transmitter parameters section.
6.7 AGC Handshake
On the digital input pin AGCRESET, a 0-to-1 transition clears
AGCSET output to logic 0 and starts the AGC cycle. At the end of
the AGC settling, the AGCSET output is asserted to logic 1. The
AGCRESET input can then be reset to logic 0. At any time in the
RECEIVE mode the AGC can be forced to the maximum gain by
giving the AGCRESET signal as described, but by additionally
re-setting it to logic 0 within 1 µs. The AGCSET indication is not
given in this case and the receiver settling time is 3 µs. The channel
filters will be set to have a lower cut-off of 1 MHz. For a timing
diagram, please see the receiver parameters section.
The wide band IQ upconverter includes spectral shaping
reconstruction filters (4th order low-pass Butterworth with 9.75 MHz
3 dB upper cut-off frequency).
At +8 dBm maximum transmitter output level the out-of-band (FCC
forbidden band) spurious signal power is less than –77 dBc
(integrated over 1 MHz with a 100 kHz resolution bandwidth) for the
11 Msymbols/sec CCK modulation (footnote 1). This implies that the
spectral regrowth is dominated by any external PA that may be used
to boost the transmission power level.
6.8 RSSI
The Receive Signal Strength Indicator (RSSI) is implemented as an
error signal comparing the signal level at the Rx output to the
nominal value of 500 mVpeak,differential. It has a –10 dBc to +10 dBc
operational range relative to the nominal signal level. Since the
RSSI acts on the modulated RF signal envelope that is extracted
from the baseband I and Q signals, it includes DC offsets, and will
therefore show transient decaying errors when the AC coupling
lower cut-off frequency is changed.
In analog mode, it is assumed that the input baseband IQ signals as
delivered from the Baseband IC are pulse shaped.
By using the on-chip calibration loop, the transmitter Carrier
Leakage can be reduced to levels far less than required by the
standard. An RF power meter detects the LO level, converts it into a
digital signal and a state machine determines the compensation
values which are fed through a DAC directly to the IQ inputs. This
mode is activated by setting the IC into the DCALIB mode by means
of 3-wire bus programming. This calibration is designed to
compensate for any DC offsets delivered by the ADCs on the
Baseband IC. The DCALIB cannot be used when the IC is using the
digital-input Tx mode.
The RSSI signal reflects on a logarithmic scale the amplitude of the
instantaneous modulated RF signal (envelope). The RSSI signal is
filtered by a low-pass filter with 0.5 MHz upper cut-off frequency.
The SA2400A receiver is designed to give at least –10 dBc RSSI at
maximum gain, when there is no signal present, i.e., with only
thermal noise. However, due to process spreads (e.g., gain, noise
figure, IQ low-pass filter bandwidth, etc.), the RSSI may show higher
than –10 dBc. In case a calibration is required for setting this noise
power to –10 dBc, the AGC’s maximum gain (GMAX) can be
changed in the range of 85 to 54 dB in steps of 1 dB via register
settings. The programmed value of maximum gain is never altered
by the AGC settling or by forcing the AGC to maximum gain. Only
the RXMGC mode can set the AGC gain to values higher than
GMAX. The RXMGC mode does not change the value of GMAX.
The IQ gain and phase imbalance, reconstruction filter roll-off and
in-channel noise produce a modulation EVM of less than 12% for
11 Msymbols/sec QPSK. The transmitter has two switched outputs,
one with –1.5 dBm output power and the other one with +8 dBm
output power. The input pin TX_HI is used to select between the two
RF output ports.
The 8 dBm output port is differential and is designed to work
seamlessly (no external filtering required) with the SA2411 power
amplifier.
Upon entering the Tx mode, the ramping up of the RF Tx signal is
delayed by an internal power ramping circuit. The ramping up time is
fixed, while the delay prior to ramping up can be programmed by
register settings.
6.9 Receiver blocking immunity
The receiver is designed to exceed the IEEE802.11 specifications
for the blocking and intermodulation. It can accept continuous or
randomly pulsed interfering single- or multi-tone signals that are
more than 35 dB stronger than the wanted signal, and up to
–10 dBm of interference level. The spurious I and Q outputs are
maintained to smaller than –20 dBc of the wanted signal level.
Note: When switching out of the Transmit mode (either into Receive
mode by transition on TXRX pin, or into another mode by 3-wire
programming), the reference clock input (pins XTAL_1 and XTAL_2)
needs to be active since a digital timer is being used.
6.10 Transmitter and IQ upconverter
6.11 Reference current and voltage outputs
The transmitter inputs are designed to be driven from a Baseband
IC in one of two modes: a) in analog mode, differential I and Q
inputs expect current signals driven by DACs in the Baseband IC; or
b) in digital mode, single-ended inputs expect two binary data
The IC provides a temperature-constant reference current of 1 mA
or 300 µA (selectable), active in Tx mode, as well as a 2.5 V
reference voltage.
1.
For a CCK signal, the peak signal power is 21.7 dB lower than the total power integrated over the 22 MHz band. The SA2400A guarantees better than 56 dBc
suppression of the second sidelobe (greater than 22 MHz frequency offset). Consequently, the power level in the forbidden bands is at least 77 dBc below the transmitted
integrated power.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
7. OPERATING CONDITIONS
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Tstg
Storage temperature
–55
+150
°C
VDD
Supply voltage
–0.5
+3.85
V
Voltage applied to inputs
–0.5
VDD+0.5
V
Short circuit duration, to GND or VDD
–
1
second
Table 4. Recommended Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
Tamb
Ambient operating temperature (Note 1)
–30
–
+85
°C
VDD
Supply voltage
2.85
3.3
3.6
V
NOTE:
1. When the digital input mode is used, the lower limit of the ambient operating temperature is higher than –30 °C. Preliminary characterization
results suggest a limit of –20 °C. This does not apply if the analog input mode is used.
8. OPERATIONAL MODES AND CURRENT CONSUMPTION
(See also Table 18).
Table 5. Operational modes and current consumption
Tamb = 25 °C; VCC = 3.3 V.
Chip state
Main mode
(register 0x04)
Other conditions
POWER-UP
SLEEP
XO on,
clock output on
SLEEP
SLEEP
XO off
TX HI
TX/RX or
FASTTXRXMGC
TX LO
RX
Description
Duration
(max.)
Current (mA)
Min
Typ
Max
n/a
1.8
2.2
2.7
Note 1.
n/a
–
–
0.05
TXRX = HIGH;
TX_HI = HIGH
Synthesizer ON.
Transmitter ON with 8 dBm driver.
Maximum gain.
n/a
120
143
170
TX/RX or
FASTTXRXMGC
TXRX = HIGH;
TX_HI = LOW
Synthesizer ON.
Transmitter ON with –1.5 dBm driver.
Maximum gain.
n/a
81
95
105
TX/RX or
RXMGC or
FASTTXRXMGC
TXRX = LOW
Synthesizer ON. Receiver ON.
Receiver gain control by:
n/a
81
95
105
•
•
•
TX/RX ⇒ internal AGC
RXMGC ⇒ 3-wire bus programming
FASTTXRXMGC ⇒ fast 3-wire bus
WAIT
WAIT
Only Synthesizer and Xtal oscillator ON
n/a
27
31
34
FCALIB
FCALIB
Calibrates cut-off frequency of Tx and Rx
filters internally. Automatic transition to
SLEEP mode upon completion.
3 µs
–
n/a
–
DCALIB
DCALIB
Calibration to reduce transmitter carrier
leakage. Automatic transition to SLEEP
mode upon completion.
20 µs
–
n/a
–
VCOCALIB
VCOCALIB
Calibrates internal VCO.
2200 µs
–
n/a
–
RESET
RESET
Resets IC into power-up state (SLEEP
mode and all registers at default values)
n/a
–
n/a
–
Maintain TX mode
for 5 µs before
calibration.
Quiescent IQ input.
Analog mode used.
NOTE:
1. All digital inputs connected to GND or VDD.
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
initiated by a 0-to-1 change on the AGC_RESET digital input pin. At
any time in the RECEIVE mode, the AGC can be forced to the
maximum gain setting by giving a 1 µs pulse on the AGC_RESET
input while the TX/RX input is held at logic 0.
8.1 RESET
Shuts down all blocks except the 3-wire digital section, and
programs internal registers to known default values that are
described in section 13. This ensures that the SA2400A transmitter,
receiver, synthesizer and other blocks enter a known state when
made active. The SA2400A enters the SLEEP state automatically
after the RESET state. Before entering either the TXRX or RXMGC
active states, the internal registers can be reprogrammed to change
their values from the default values. A power-up of the digital supply
also forces the SA2400A to the RESET mode.
8.6 FASTTXRXMGC
It is similar to the RXMGC mode, except that the manual AGC gain
programming can be done faster, as described in Section 14.5.
8.7 FCALIB
This mode needs to be programmed after power ON in order to
internally calibrate the cut-off frequency of the on-chip transmit and
receive active filters. Upon completion of the calibration, the IC will
automatically switch to Main Mode = SLEEP. This calibration takes a
maximum of 3 µs measured from the end of the programming
sequence. The result of this calibration can be read out from register
word 0x04.
8.2 SLEEP
All blocks (except the xtal osc) are OFF. The xtal osc can be
separately shut down. Note that the 3-wire bus will remain
operational in all modes as long as the digital supply is ON. The
SA2400A retains programmed values of all active modes when it
comes out of the sleep mode. This includes the synthesizer
operation. Programmed via 3-wire bus.
8.8 DCALIB
Only the PLL and Receiver are operating. The AGC gain is manually
set by the value of a register field.
If the analog Tx inputs are used, this mode needs to be programmed
at least once after power ON in order to reduce the transmitter
carrier leakage. This mode should be programmed after being in TX
mode for at least 5 µs. Upon completion of the calibration, the IC will
automatically switch to Main Mode = SLEEP. This calibration takes a
maximum of 20 µs measured from the end of the programming
sequence. The result of this calibration can be read out from register
0x07.
8.5 TXRX
8.9 VCOCALIB
In this mode the logic level on the TX/RX input pin determines the
operational mode: 1 = TRANSMIT, 0 = RECEIVE. This way, no
3-wire bus programming is necessary to switch between Tx and Tx,
resulting in faster switching. When entering the RECEIVE mode
(either via 3-wire programming to TXRX mode with TX/RX pin at
logic zero, or by a 1-to-0 transition of TX/RX pin when already in the
TXRX mode), the Receiver is set to maximum gain. An AGC cycle is
This mode needs to be programmed at least once after power ON in
order to calibrate the internal VCO. Upon completion of the
calibration, the IC will automatically switch to Main Mode = SLEEP.
This calibration takes a maximum of 2.2 ms from the end of the
programming sequence. After this calibration, the synthesizer must
be re-programmed by writing the register words 0x00 through 0x03.
The result of this calibration can be read out from register 0x08.
8.3 WAIT
The PLL is on. Receiver and the transmitter are both OFF. This
mode is useful for a quick turn-around to either TXRX or RXMGC
modes. Transition to or from this mode is done via the 3-wire bus.
8.4 RXMGC
2002 Nov 04
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Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
9. SA2400A RECEIVER
The baseband output signal extends from DC to 8 MHz, and the out-of-band frequency begins from 11 MHz. The modulated test signal used is
11 Msymbols/sec QPSK with raised cosine filtering (50% excess bandwidth for 11 Msymbols/sec). The LO frequency is the same as the
Receiver channel center frequency, as the IF output is at 0 Hz.
Table 6. SA2400A Receiver properties
Tamb = 25 °C; VCC = 3.3 V; fLO = 2.45 GHz.
Specification
Conditions
Min
RF input frequency range
Typical
2.4
S11 (RF input)
Incl balun+matching. 50 Ω unbalanced. Note 3.
LNA in high gain (see reg. description 0x06)
LNA in low gain
Typ
Max
Units
2.5
GHz
–10
–7
–
–
dB
dB
Maximum Rx voltage gain
RF input to I or Q outputs
90
93
–
dB
Max RF input level
Including application, AGCTARGET = +5. Note 1.
–10
–
–
dBm
To maintain nominal IQ output levels as defined
below (“nominal I and Q output voltage”)
–20
–
–
dBm
IQ Output DC error (relative to signal,
5 µs after AGC set)
–80 dBm < Pinput < –20 dBm, 1 MHz sinewave
output. Note 3.
–
–
–20
dBc
AGC settling time
(indicated by AGC_SET digital
output)
Initiated by AGC_RESET input. Constant RF input
within this settling time. Begins after TX to RX
switching time. Measured from AGC_RESET 0–1
transition. AGC delay registers (0x05) at default or
smaller values. Note 2.
a) First instance
b) 2nd or subsequent instances
–
–
–
–
8
11
µs
µs
–
–
0
µs
–
–
3
µs
AGC Max Gain settling time
AGC forced to GMAX by:
a) TX to RX mode transition.
(measured after 5 µs TX–RX settling time).
b) Pulse on AGC_RESET pin
(measured from end of programming)
Note 2.
AGC Max Gain adjustment range
Note 2.
54 to 85, in steps of 1
AGC error (I, Q signal levels)
RF input between –75 to –20 dBm. AGC_RESET
used. AGC delay registers (0x05) at default values.
a) Random (varies each AGC cycle)
b) Slow (varies with VCC, Temperature).
c) Static (fixed, part to part)
–3
–1
–1
–
–
–
3
1
1
dB
dB
dB
DC cancellation time
( ft AGCRESET)
(after
With constant RF input during this time. Note 3.
a) DC offset < 50% of output signal level
b) DC offset <10% of output signal level
–
–
–
–
8
13
µs
µs
TX to RX switching time
Output signal within 1 dB of final value,
frequency error within 25 ppm of final value. Note 3.
–
3
3.5
µs
Noise Figure
(I l balun+matching)
b l
t hi )
(Incl
Less than the piece-wise linear interpolation. Note 3.
Pinput = –85 dBm (LNA in high gain mode)
–75 dBm
–60 dBm (LNA in low gain mode)
–45 dBm
–
–
–
–
7.5
7.5
24
24
9
9
25
25
dB
dB
dB
dB
Input IP3
(50 Ω source resistance)
2 interfering tones of power Pinterferer each, at 13
and 23 MHz offsets from LO.
IP3 to be more than the piece-wise linear
interpolation:
Pinterferer = –39 dBm
–5
1
–
dBm
1 dB compression of wanted signal
Including matching, receiver at minimum gain.
–10
0
–
dBm
Desens by jammer
–45 dBm wanted signal at 1 MHz offset, +40 dBc
jammer at 25 MHz offset. Note 3.
–
–
1
dB
2002 Nov 04
10
dB
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Specification
Conditions
Min
Typ
Max
Units
LO leakage to antenna
All gain modes. Incl balun
–
–75
–57
dBm
Residual sideband Rejection
Measured with single tone at 2 MHz offset from
carrier. Includes both IQ gain and phase error.
Notes 3, 7.
22
29
–
dB
Ripple band width of filter
Note 4.
5.6
6.3
7.0
MHz
3 dB band width of filter
Indicative, not tested. Note 4.
–
7
–
MHz
In-band amplitude ripple
DC to ripple band width edge. Note 3.
–
–
0.6
dB peak
Out-of-band attenuation
Relative to minimum in-band gain
> 11 MHz
> 22 MHz
25
55
–
–
–
–
dB
dB
Lower 3 dB cut-off frequency of AC
coupling
li
Cascade of two 1st order high-pass filters.
a) NARROW BAND
b) INTERMEDIATE BAND
c) WIDE BAND
–
–
–
10
100
1000
–
–
–
kHz
kHz
kHz
Output load resistance
Pin to GND, differential.
15
–
–
kΩ
Output load capacitance
Pin to GND
–
–
6
pF
Nominal I & Q output voltage
Differential at the load specified. Note 6.
–
0.5
–
V peak
Maximum I & Q output voltage
Saturated, differential
–
–
1.5
V peak
Common mode IQ voltage
Programmable (see 0x04)
Mode 1
Mode 2
VCC/2–0.25 VCC/2
1.0
1.25
VCC/2+0.25
1.5
V
V
1 dB compression level at output
1 MHz tone, differential. Maximum gain.
1
–
–
V peak
Total Harmonic Distortion
(measured at max and min gains)
Input 1 – 5 MHz signal, 1 V peak differential
sinusoidal at output, output spurs measured
differential up to 100 MHz. Ratio of rms total
spurious distortion to rms fundamental.
Receiver in minimum gain. Note 3.
–
2
4
%
Note 5.
Receiver in maximum gain. Note 3.
–
5
10
%
Phase Imbalance
Signal tone input at 2 MHz offset from carrier.
Indicative, not tested.
–
4
–
deg
I, /I to Q, /Q amplitude imbalance
ratio of signal at I pin to /I pin;
Same for Q and /Q pins.
–
0.1
–
dB
RSSI voltage in settled state
(internal AGC)
Corresponds to I, Q output signal levels when
AGC_RESET is used, with RF input
between –10 and –80 dBm.
1 MHz tone, 0.5 V peak differential.
ACGTARGET = 0
1.25
1.55
1.95
V
RSSI voltage difference
1 dB change in input power compared to
settled state
–
64.5
–
mV
RSSI minimum voltage
Signal power = –10 dBc
–
0.9
–
V
RSSI maximum output voltage
Signal power = +10 dBc
–
2.2
–
V
RSSI error
–10 dBc < signal power < +10 dBc
–
±1
–
dB
NOTES:
1. Corresponds to –15 dBm input level at IC input, assuming typical 5 dB loss from the antenna to the IC input. The AGCTARGET register
should be set to “+5” which causes the AGC to settle to an output amplitude greater than the specified nominal value. A resistive divider
network at the output can be used to adjust the actual IQ output levels to the BB ADC range.
2. Guaranteed by design.
3. Verified by bench characterization and found to have sufficient margin for production.
4. At power-up time, the filter bandwidth is undefined. It needs to be calibrated with the internal tuner (FCALIB mode).
5. For unsymmetrical loading, attach the same load impedance to the unused pin; condition: for 80% of nominal output voltage swing.
6. Nominal I/Q output levels are understood as the levels the SA2400A will settle to after an AGCRESET action is performed with an RF input
signal modulated by a Barker sequence, and with AGCTARGET = 0.
7. RSB = 20*log(sqrt([1+K2 + 2Kcosϕ]/[1+K2 – 2Kcosϕ])), where K = linear gain imbalance, and ϕ = phase imbalance.
2002 Nov 04
11
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
9.1 AGC handshake and timing
Th,agcreset
Tr,agcreset
Tdsettle
TXRX
AGCRESET
AGCSET
Treset
Trestart
Tdrxon
Rx
TURN-ON
REGULAR SETTLING
SET
MAXGAIN
REGULAR
SETTLING
SR02417
Figure 3. AGC handshake and timing.
Table 7. AGC timing
Symbol
Parameter
Condition
Min
Typ
Max
Units
AGC logic level requirements
VIH
HIGH-level logic input voltage
0.5×VDD
–
VDD+0.3
V
VIL
LOW-level logic input voltage
–0.3
–
0.2×VDD
V
AGCRESET timing
Tr,agcreset
Input rise time
Th,agcreset
, g
Input hold time
Trestart
–
10
40
ns
To execute AGC settling
5
8
–
µs
To set AGC to max. Gain
–
0.5
1
µs
1
–
–
µs
Time between AGC cycles (Note 1)
AGCSET timing
Tdrxon
Settling time after switching to Rx
–
–
5
µs
Treset
Clearing time after AGCRESET
–
–
180
ns
Tdsettle
AGC settling time
–
–
11
µs
NOTES:
1. In certain time interval further AGCRESET rising edges will not be detected. This applies for 4.3 µs < Trestart < 4.8 µs.
2002 Nov 04
12
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
10. SA2400A TRANSMITTER
The IQ baseband input signal used is 11 Msymbols/sec QPSK with pulse shaping and 44 MHz D/A sampling rate. The source EVM is less than
3%. The LO frequency is the same as the Transmitter channel center frequency, as the transmit IF input is at 0 Hz.
Table 8. SA2400A Transmitter properties
Tamb = 25 °C; VCC = 3.3 V.
Specification
Conditions
Min
Typ
Max
Units
RF output frequency
Typical
2.4
–
2.5
GHz
RF output power incl balun,
for a CCK modulated signal
Output1, maximum
4.5
8.0
–
dBm
Output2, maximum
–5
–1.5
–
dBm
Gain step size
Output1 and Output2
–
1
–
dB
# gain steps
Output1 and Output2
–
15
–
Spectral Mask (Output1)
N
Note
1.
1
–11 to + 11 MHz, 100 kHz band
–22 to –11 and 11 to 22 MHz, 100 kHz band
< –22, > 22 MHz, 100 kHz band
–
–
–
–
–40
–60
0
–36
–56
dBc
dBc
dBc
Spectral Mask (Output2)
Note 1.
–11 to + 11 MHz, 100 kHz band
–22 to –11 and 11 to 22 MHz, 100 kHz band
< –22, > 22 MHz, 100 kHz band
–
–
–
–
–
–
0
–30
–50
dBc
dBc
dBc
Power ramping up time
10% to 90% ramp up. Note 2.
–
0.5
–
µs
Power ramping up delay
(Note 3)
From programming to TRANSMIT mode (TXRX mode, or 0-to-1
change of TX/RX pin). Note 2.
–
2
–
µs
Power ramping down
Note 2.
a) 90% to 10% ramp down
b) 10% to carrier leakage level
–
–
0.5
0.5
–
–
µs
µs
Analog input mode selected. No signal input, only quiescent current.
a) Uncalibrated
b) Calibrated
–
–
–
–40
–25
–30
dBc
dBc
Carrier Leakage
Digital input mode selected.
–
–40
–28
dBc
Carrier Leakage Adjustment
Adjustment range of input current offset
–10
–
+10
µA
Residual Sideband Rejection
Includes both IQ phase and gain imbalance
22
–
–
dB
Error Vector Magnitude
11 Msymbols/s QPSK. Both RF outputs. Measured with maximum
gain. Note 2.
–
12
14
%
RX to TX switching time
Note 2.
a) Output power within 1 dB of final value. Includes 2.5 µs for
power-up delay and ramping.
b) Frequency step settles to within 25 ppm of final value
–
3
3.5
µs
–
3
3.5
µs
IQ filter bandwidth
Upper 3 dB cut off frequency, after calibration. Note 2.
9.25
9.75
10.25
MHz
In-band IQ Common Mode
Rejection Ratio
1–6 MHz common mode signal at –30 dBc relative to IQ differential
signal. Measured at upconverted transmitter output. Note 2.
30
–
–
dB
Out-of-band IQ Common
Mode Rejection Ratio
22–100 MHz common mode signal at –10 dBc relative to IQ
differential signal. Measured at upconverted transmitter output
relative to in-band 1 MHz tone. Note 2.
40
–
–
dB
IQ input signal current range
Into each arm of differential inputs that sink current to ground.
Analog input selected. Note 4.
50
–
550
µA
IQ input quiescent current
Into each arm of differential inputs that sink current to ground.
Analog input selected.
–
300
–
µA
Resulting I/Q bias voltage
With 300 µA quiescent current into each arm of differential inputs.
Analog input selected.
0.6
0.7
0.8
V
IQ AC input impedance
Analog input selected.
IQ input voltage
Digital input selected
2002 Nov 04
13
–
320
–
Ω
Logic LOW
–
–
0.2VDD
V
Logic HIGH
0.8VDD
–
–
V
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
Specification
Conditions
IQ input timing
Digital input selected, sampling on falling edge,
l i to REF_CLK_OUT
REF CLK OUT
relative
SA2400A
Min
Typ
Max
Units
Set-up time
–
4
–
ns
Hold time
–
4
–
ns
NOTES:
1. The 44 MHz common mode digital ground bounce on the I and Q inputs is assumed to be less than –30 dBc relative to signal level.
2. Verified by bench characterization and found to have sufficient margin for production.
3. The power ramping-up delay can be programmed to 2, 3, 4, 5 µs. See the 3-wire bus control register map. The default is 2 µs.
4. The differential input signal current is the difference between the I and /I (Q and /Q) instantaneous currents. The peak differential current is
therefore (Imax–Imin)/2 = 500 µA.
11. VCO AND SYNTHESIZER
Table 9 lists the synthesizer specifications. The synthesizer has the same specification as the SA8027 fractional PLL main loop without the PHI
speed-up mode. The phase comparator frequency used is typically 4 MHz (in fractional mode). The charge pump current is internally
programmed using the 3-wire bus (Synthesizer Register C). The recommended charge pump current is 480 µA. An external reference input of
44 MHz or 22 MHz is supported.
Table 9. Synthesizer and VCO Specifications
Tamb = 25 °C; VCC = +3 V
LIMITS
PARAMETER
TEST CONDITIONS
UNITS
Min
Typ
Max
2.4
–
2.5
GHz
VCO
VCO output frequency range
VCO gain (KVCO)
Vtune = 1.2 V
70
85
100
MHz/V
Open Loop VCO Phase Noise
Note 1. 1/f2 roll off region; 0.5 MHz offset
–
–113
–107
dBc/Hz
External VCO input levels
Differential; when device configured for
external VCO
–10
–
0
dBm
512
–
65535
–
–
22
44
–
–
Main divider
N divider range
Reference divider
Fixed reference input (XTAL_1 and XTAL_2)
f
frequency
MHz
MHz
R divider range (non-fractional)
SM = ‘000’
4
–
1023
Reference input level
XTAL_1 input
350
–
1300
mVpp
Input parallel resistance (XTAL_1, XTAL_2)
f = 44 MHz; indicative, not tested
10
–
–
kΩ
Input parallel capacitance (XTAL_1, XTAL_2)
f = 44 MHz; indicative, not tested
–
–
1.5
pF
–
–
4.0
MHz
–20
–
+20
%
0.6
–
VDD − 0.7
V
Phase detector
Phase detector frequency
Charge pump
Charge pump current accuracy
Vcp = 0.5 VCC
Charge pump compliance voltage
Output current variation vs. Vcp (Note 2)
Vcp in compliance range
–5
–
+5
%
Charge pump sink to source current
Matching
Vcp = 0.5 VCC
–10
–
+10
%
Charge pump “off” current leakage
Vcp = 0.5 VCC
–5
±1
5
nA
NOTES:
1. This is measured at the Output1 RF port with the SA2400A in transmit mode, with static DC offset signals to the transmitter I and Q inputs.
The phase detector and divide-by-N phase noise is such that when configured as a phase locked loop with a 30 kHz loop band width, the
phase noise at frequencies between 1 kHz and 30 kHz will be no worse than –80 dBc/Hz. The total closed loop spur power within a 22 MHz
band around the carrier is less than –30 dBc.
(I 2 * I 1)
2. The relative output current variation is defined as: DI ZOUT + 2
Ť I2 ) I1 Ť
I OUT
with I1 @ V1 = 0.6 V, I2 @ V2 = VCC – 0.7 V (see Figure 4).
2002 Nov 04
14
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
CURRENT
IZOUT
I2
I1
VOLTAGE
V1
V2
VPH
I2
I1
SR00602
Figure 4.
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump.
12. FUNCTIONAL DESCRIPTION
12.1 Main Fractional-N divider
The divider consists of a fully programmable bipolar prescaler
followed by a CMOS counter. Total divide ratios range from 512 to
65535.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator.
Also, the fractional accumulator is incremented by the value of NF.
The accumulator works with modulo Q set by FM (Synthesizer
Register A). When the accumulator overflows, the overall division
ratio N will be increased by 1 to N + 1, the average division ratio
over Q main divider cycles (either 5 or 8) will be
Nfrac N
12.2 Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a 3-bit binary counter. The
3-bit SM register (see Figure 5) determines which of the five output
pulses are selected as the main phase detector input.
NF
Q
SM=“000”
SM=“001”
SM=“010”
SM=“011”
TO
MAIN
PHASE
DETECTOR
SM=“100”
REFERENCE
INPUT
DIVIDE BY R
/2
/2
/2
/2
SR02354
Figure 5. Reference Divider
2002 Nov 04
15
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
dead zone (caused by finite time taken to switch the current sources
on or off) is cancelled by forcing the pumps ON for a minimum time
(τ) at every cycle (backlash time) providing improved linearity.
12.3 Phase detector (see Figure 6)
The reference and main divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by the control bit CP (Synthesizer Register C). The
VCC
1
fREF
REF DIVIDER
P–TYPE
CHARGE PUMP
P
D
Q
CLK
R
R
τ
1
fRF
MAIN
DIVIDER
D
IPH
R
N–TYPE
CHARGE PUMP
CLK
Q
M
N
GND
fREF
R
M
τ
P
τ
N
IPH
SR02355
Figure 6. Phase Detector Structure with Timing
2002 Nov 04
16
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
accumulator value and is adjusted by FDAC values (bits FC7–0 in
Synthesizer B). The fractional compensation current is derived from
the main charge pump in that it follows all the current scaling through
programming or speed-up operation. For a given charge pump,
12.4 Main output charge pumps and fractional
compensation currents (see Figure 7)
The main charge pumps on pin CP are driven by the main phase
detector and the charge pump current value is determined by bit CP
(Synthesizer Register C). The fractional compensation is derived
from the contents of the fractional accumulator FRD and by the
program value of the FDAC. The timing for the fractional
compensation is derived from the main divider. The charge pumps
will enter speed-up mode after sending a Synthesizer Register A
word and stays active until a different word is sent.
ICOMP = (IPUMP / 128) * (FDAC / 5*128) * FRD
FRD is the fractional accumulator value.
The target values for FDAC are: 128 for FM = 1 (modulo 5) and
80 for FM = 0 (modulo 8).
12.6 Lock Detect
The output LOCK maintains a logic ‘1’ when main phase detector
indicates a lock condition. The lock condition is defined as a phase
difference of less than 1 period of the frequency at the input
XTAL_1, XTAL_2. Out of lock (logic ‘0’) is indicated when the
synthesizer is powered down.
12.5 Principle of fractional compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If ICOMP is the
compensation current and IPUMP is the pump current:
12.7 Power-down mode
IPUMP_TOTAL = IPUMP + ICOMP.
The power-on signal is defined by the bit ON in Synthesizer Register
B. If ON = ‘1’, the synthesizer section is powered on/off as defined
by the chip mode (register 0x04). If ON = ‘0’, it is defined as inverted
to the chip mode. When the synthesizer is reactivated after
power-down, the main and reference dividers are synchronized to
avoid possibility of random phase errors on power-up.
The compensation is done by sourcing a small current, ICOMP, see
Figure 8, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
REF. DIVIDER
OUTPUT R
MAIN DIVIDER
OUTPUT M
N
DETECTOR
OUTPUT
N
2
N+1
N
4
1
N+1
3
0
ACCUMULATOR
FRACTIONAL
COMPENSATION
CURRENT
PULSE
WIDTH
MODULATION
mA
OUTPUT ON
PUMP
µA
PULSE LEVEL
MODULATION
SR01416
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output.
Figure 7. Waveforms for NF = 2 Modulo 5 → fraction = 2/5
fRF
FRACTIONAL
ACCUMULATOR
MAIN DIVIDER
ICOMP
IPUMP
fREF
Σ
LOOP FILTER
& VCO
SR01800
Figure 8. Current Injection Concept
2002 Nov 04
17
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
13. SA2400A OTHER FUNCTIONALITY
Table 10 specifies functionality not described elsewhere in this document.
Table 10. SA2400A Other Functionality
Tamb = 25 °C; VCC = 3.3 V
LIMITS
PARAMETER
TEST CONDITIONS
Reference voltage output, pin V_2P5
Reference current output, pin IDCOUT
Typ
Max
ILOAD < 2 mA, CLOAD < 10 pF;
switched on via register 0x04 bit 14 = ‘1’
2.25
2.5
2.75
V
Register 0x04 bit 12 = ‘1’;
“sink current” measured from supply to IC pin
0.25
0.3
0.35
mA
Register 0x04 bit 13 = ‘1’;
“source current” measured from IC pin to ground
0.85
1.0
1.15
mA
The 3-wire bus interface contains an internal counter (state
machine) which determines beginning and end of address and data
word, the “write” pulse to the internal registers, and the direction of
the bi-directional SDATA pin. Consequently, with the 32nd rising
SCLK edge of a WRITE cycle, the current data word is stored in the
internal register of the programmed address. Following SCLK edges
will be taken as the beginning of the following cycle. No
programming on SEN is needed to separate cycles.
14. 3-WIRE BUS/LOGIC CONTROL
A simple 3-line bi-directional serial bus is used to program the
circuit. The 3 lines are SDATA, SCLK and SEN. The SDATA line is
bi-directional while the SCLK and SEN signals are always supplied
externally:
• The pin SEN is an “enable” signal. It is level sensitive: If SEN is of
LOW value, the 3-wire bus interface on the SA2400A is enabled.
This means that each rising edge on the SCLK pin (see below)
will be taken as a shift cycle, and address/data bits are expected
on SDATA (see below). If SEN is HIGH, the 3-wire bus interface
is disabled. No register settings will change regardless of activity
on SCLK and SDATA.
If the SEN signal is switched to HIGH (i.e., DISABLE) at any time,
the current cycle will be disregarded. Any bits that have been shifted
in so far via SDATA will be disregarded. The internal counter is reset
to zero.
• The pin SCLK is the “shift clock” input. If the 3-wire bus is
14.1 Description of WRITE cycle
enabled, address or data bits will be clocked in from the SDATA
pin with rising edges of SCLK. In output mode, SDATA bits are
set on the falling edge of SCLK in order to be sampled on the
rising edge by the controller.
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
enabled.
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
The bit values on SDATA are taken over with rising edges on
SCLK.
• The pin SDATA is the bi-directional “data” pin. It is internally
configured as “input” or “output” depending on the operation
(WRITE or READ).
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising
edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.
Each operation consists of 32 bits. Out of these, the first 7 bits form
an address word, followed by a READ/WRITE indicator bit. The
following 24 bits are the data word corresponding to the chosen
address.
4. (SCLK edges 9 through 32) 24 data bits are clocked in, LSB first,
with rising edges of SCLK. With the 32nd rising edge of SCLK,
the whole data word is stored in the internal register according to
the selected address.
tr
Tcyc
1
2
3
A0
A1
A2
UNITS
Min
4
5
6
7
8
tf
9
10
11
32
1
SCLK
SEN
SDATA
Ton
A3
A4
A5
A6
R/W
D0
D1
Thold
D23
SR02288
Figure 9. WRITE cycle timing diagram of the 3-wire bus
2002 Nov 04
D2
Tsetup
18
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
3. (SCLK edge 8) The READ/WRITE bit is clocked in with the rising
edge of SCLK. ‘1’ = WRITE, ‘0’ = READ.
14.2 Description of READ cycle
1. (start) SEN is LOW or is changed to LOW, i.e., 3-wire interface is
enabled.
4. (SCLK edges 9 through 32) 24 data bits are clocked out, LSB
first. The bits will be available on the SDATA pin with the falling
edges of SCLK (so bits can be accepted by the baseband IC
with the following rising edge).
2. (SCLK edge 1 through 7) 7 address bits are clocked in, LSB first.
The bit values on SDATA are taken over with rising edges on
SCLK.
Tcyc
1
2
3
4
A0
A1
A2
A3
5
tr
6
7
8
9
tf
10
11
32
1
SCLK
SEN
SDATA
Ton
A4
A5
A6
R/W
Tsetup
D0
D1
D2
D23
Tdout
SR02289
Thold
Figure 10. READ cycle timing diagram of the 3-wire bus
The fully static CMOS design uses virtually no current when the bus is inactive. It can always capture new data even during power-down. The
data remains latched during power-down (sleep mode).
14.3 3-wire bus/logic control AC characteristics
Table 11. 3-wire bus/logic control AC characteristics
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNITS
Serial Bus Logic Level Requirements
VIH
HIGH logic input voltage
0.5×VDD
–
VDD + 0.3
V
VIL
LOW logic input voltage
–0.3
–
0.2×VDD
V
Serial Programming Clock, SCLK
tr
Input rise time
–
10
40
ns
tf
Input fall time
–
10
40
ns
Tcyc
Clock period
22
100
–
ns
10
–
–
ns
Enable Programming, SEN
Ton
Delay to rising clock edge
Data Programming, SDATA
Tsetup
Input data to clock set-up time
–
10
–
–
ns
Thold
Input data to clock hold time
–
10
–
–
ns
Tdout
Output data to clock delay time
(falling edge)
–
–
–
10
ns
2002 Nov 04
19
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
14.4 3-wire bus control register map
14.4.1 Data Format
Table 12. Format of programmed data
LAST IN (MSB)
23
22
21
20
19
18
17
FIRST IN (LSB)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 13. Overview
Address
Description
00
Synthesizer: Main divider settings WRITE ONLY
01
Synthesizer: Reference divider and fractional compensation WRITE ONLY
02
Synthesizer: charge pump current and additional division WRITE ONLY
03
Synthesizer: test modes WRITE ONLY
04
Main operation modes, filter tuner, other controls
05
Rx AGC adjustment settings
06
Manual receiver control settings
07
Transmitter settings
08
VCO settings (only bits 0 through 9)
NOTES:
1. The synthesizer registers (addresses 00 to 03) cannot be read.
2. After programming register 0x01 it is necessary to also program register 0x00 to load the content of FC[7:0] into the internal working register.
3. After programming register 0x00 it is necessary to program some other register (e.g., 0x04) to avoid keeping the charge pump current
setting in php-speedup mode.
4. After running the VCOCALIB mode, it is necessary to re-program registers 0x00 through 0x03.
Table 14. Address 00: Synthesizer Register A
Note: Bits 22, 23 not used.
Main divider register
Bit
21
Name
FM
Default
0
20
19
18
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
1
0
NF[2:0]
1
0
9
8
7
6
5
4
3
2
0
1
1
0
0
1
1
1
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
N[15:0]
Bit
Description
FM
Fractional modulus select. 0–>/8; 1–>/5; default: 0
NF[2:0]
Fractional increment value (0 to 7); default: 4
N[15:0]
Main divider division ration (512 to 65535); default: 615
1
0
unused
Table 15. Address 01: Synthesizer Register B
Note: Bits 22, 23 not used.
Bit
21
20
19
18
Name
Default
17
16
15
14
13
12
11
R[9:0]
0
0
0
0
0
0
10
L
1
0
1
1
1
ON
0
1
FC[7:0]
1
0
1
Bit
Description
R[9:0]
Reference divider ratio (4 to 1023); default: 11
L[1:0]
lock detect mode
00–> inactive
01–> inactive
10–>lock detect normal mode
11–>inactive
ON
Power On/Off 1: as defined by chip mode (register 0x04) 0: inverted chip mode control
FC[7:0]
Fractional compensation charge pump current DAC (0 to 255); default: 80
2002 Nov 04
20
0
1
0
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 16. Address 02: Synthesizer Register C
Note: Bits 22, 23 not used.
21
Bit
20
19
18
17
16
Name
15
14
13
12
11
10
9
8
7
unused
Default
0
0
0
0
0
0
0
6
5
CP[1:0]
0
0
0
0
0
0
0
1
0
4
3
SM[2:0]
0
0
Bit
Description
CP[1:0]
Charge pump current setting
SM[2:0]
Comparison divider select
Adds an extra divider at the end of the reference divider: extra division ratio = 2^SM (SM = 0 to 4)
CP[1:0]
php
php-speedup
00
480 µA
2.4 mA
01
160 µA
800 µA
10
480 µA
2.4 mA
11
160 µA
800 µA
0
2
1
‘0’
unused
0
0
0
0
php-speedup is activated when the speed-up bit is 1 (Tspu in synthesizer register D). php-speedup is also entered after sending a synthesizer
register A word and stays active until a different word is sent. To prevent frequency deviations when leaving the speedup mode when
programming new words, it is recommended to keep the speedup mode always disabled by setting the Tphpsu (0x03, bit 16) to ‘1’.
NOTE: The only recommended charge pump current setting mode is CP[1:0] = 10, php-speedup not activated.
Table 17. Address 03: Synthesizer Register D
Note: Bits 22, 23 not used.
Bit
21
20
Name
Default
19
18
17
‘00000’
0
0
0
0
0
16
15
Tphpsu
Tspu
0
0
14
13
12
11
9
8
7
6
5
4
3
2
‘000000000000’
0
0
0
0
Bit
Description
Tphpsu
1 –> disable PHP speedup pump, overrides function of Tspu
Tspu
1 –> speedup ON
0 –> speedup OFF
2002 Nov 04
10
21
0
0
0
0
1
0
unused
0
0
0
0
0
0
0
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 18. Address 04: Main chip operation modes, filter tuner, other controls
Bit
23
22
0
0
Name
Default
21
20
‘0000’
0
0
19
18
adc
fterr
0
0
17
16
15
Filttune
0
1
1
14
13
12
11
10
9
8
7
6
5
4
v2p5
I1m
I0p3
n.u.
in22
clk
xo
digin
rxlv
veo
vei
0
0
1
0
0
1
1
0
0
0
0
Bit #
Name
Description
0–3
Chip mode
Main mode of operation. Coding according to following table:
Bit3
Bit2
Bit1
Bit0
Mode
0
0
0
0
SLEEP
0
0
0
1
TX/RX
0
0
1
0
WAIT
0
0
1
1
RXMGC
0
1
0
0
FCALIB
0
1
0
1
DCALIB
0
1
1
0
FASTTXRXMGC
0
1
1
1
RESET
1
0
0
0
VCOCALIB
3
2
1
0
Chip mode
0
0
0
0
Notes on modes:
• All calibration modes (*CALIB) require the crystal oscillator to be ON (bit XO = 1).
• DCALIB (Tx LO leakage calibration) requires being in Tx mode for 5 µs before calibration.
4
vei
Use external vco input (vcoextin)
5
veo
Make internal vco available at vco pads (vcoextout)
6
rxlv
Rx output common mode voltage: 0–VDD/2, 1–1.25 V
7
digin
Use digital Tx inputs (FIRDAC)
8
xo
Xtal oscillator ON
9
clk
Reference clock output ON
10
in22
Xtal input frequency: 0–44 MHz, 1–22 MHz
11
Not used
12
I0p3
External reference current (pad idcout): 0.3 mA to ground
13
I1m
External reference current (pad idcout): 1.0 mA from supply
14
v2p5
External reference voltage (pad v2p5) ON
15–17
filttune
Rx and Tx filter tuning bits:
Write: (with test mode only), these bits set tuning value
Read: (in normal mode) tuner setting can be read out here
18
fterr
Filter tuner error (read only): result is 1 when tuner exceeded range
19
adc
‘1’: in Rx mode, the RSSI-ADC is always on. ‘0’: the RSSI-ADC is only on during AGC operation.
Table 19. Address 05: AGC adjustment settings
Bit
23
Name
Default
22
21
20
Rx AGC target
±(0)
val(000)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Rx AGC Gmax
AGC_bbdel/ADCval
AGC_lnadel/sample2
AGC_rxondel/sample1
79 dB – 11001
7(1.3 µs) – 00111
15(2.7 µs) – 01111
27(4.9 µs) – 11011
Bit #
Name
Description
0–4
AGC_rxondel/s1
Write: Programmable delay for AGC algorithm: Rx turn-on to AGCSET. In units of 182 ns (5.5 MHz)
Read: 1st sample of RSSI in AGC cycle
5–9
AGC_lnadel/s2
Write: Programmable delay for AGC algorithm: Settling time after LNA gain switching. In units of 182 ns (5.5 MHz)
Read: 2nd sample of RSSI in AGC cycle
10–14
AGC_bbdel/ADCval
Write: Programmable delay for AGC algorithm: Settling time after baseband gain switching. In units of 182 ns
(5.5 MHz)
Read: Output of RSSI/Tx–peak detector ADC in 5-bit Gray code
15–19
AGC Gmax
Rx AGC gain limit (54 dB + programmed value) (valid: 54 through 85)
20–23
AGC target
Adjustment value to AGC settling target, range –7 dB … 7 dB (sign plus three bits)
2002 Nov 04
22
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Table 20. Address 06: Manual receiver control settings
Bit
23
22
21
Name
ahsn
osQ
Default
0
0
20
19
18
rxosQval
±(0)
17
16
15
osI
val (000)
14
13
rxosIval
±(0)
0
val (000)
12
11
ten
Corner f
1
10
0
0
9
8
7
6
1
1
1
1
5
4
3
2
1
0
1
1
1
Receiver gain
1
1
1
Bit #
Name
Description
0–9
receiver gain
Write: In RXMGC mode, this sets the receiver gain.
Read: In other modes, the AGC controlled gain is available for readout here.
Bit positions: 0–plus1dB; 1–vga2dB; 2–vga4dB; 3–vga8dB; 4–vga16dB; 5–vga10dB; 6–filter6dB2; 7–filter10dB;
8–filter6dB1; 9–lna16dB
10–11
corner freq.
DC offset cancellation cornerpoint select.
Write: In RXMGC mode, this sets the cornerpoint.
Read: In other modes, the cornerpoint as controlled by the AGC is available for readout here.
Code: 00–10 kHz, 01–100 kHz, 10–1 MHz, 11–10 MHz
12
ten
Use 10 MHz offset cancellation cornerpoint for brief period after each gain change
13–22
Rx offset I,Q
Receiver output driver manual offset adjustment. Code: {rxosXon,rxosXval} = ‘0xxxx’ → offset = 0;
{rxosXon,rxosXval} = ‘10000’ → offset = 8 mV; {rxosXon,rxosXval} = ‘11000’ → offset = –8 mV;
{rxosXon,rxosXval} = ‘10001’ → offset = 16 mV etc.
13–16
rxosIval
Rx offset correction, I channel, value (sign plus three bits)
17
rxosIon
Rx offset correction, I channel, ON
18–21
rxosQval
Rx offset correction, Q channel, value (sign plus three bits)
22
rxosQon
Rx offset correction, Q channel, ON
23
ahsn
AGC with high Signal-to-Noise (switch LNA at step 52 instead of step 60).
Recommended to set to ‘1’.
Table 21. Address 07: Transmitter settings
Bit
23
22
Name
Default
21
20
19
‘0000’
0
0
18
osQ
0
0
17
±(0)
0
16
15
14
TxosQval
13
12
osI
val (000)
11
10
txosIval
±(0)
0
9
8
7
6
txramp
val (000)
0
0
5
4
3
2
1
0
Tx gain hi
Tx gain low
0 dB (0000)
15 dB (1111)
Bit #
Name
Description
0–3
Tx gain low
Transmitter gain settings for TXLO output
4–7
Tx gain hi
Transmitter gain settings for TXHI output
8–9
txramp
Tx ramp-up delay programming: 00–1 µs, 01–2 µs, 10–3 µs, 11–4 µs. Ramp-up time always 1 µs.
10–19
Tx offset I, Q
Tx carrier leakage calibration:
Write: with test mode, these bits set the offset.
Read: in normal mode, automatically controlled settings can be read out here (sign plus three bits).
Code: {txosXon,txosXval} = ‘0xxxx’ → offset = 0; {txosXon,txosXval} = ‘10000’ → offset = 2.5 µA;
{txosXon,txosXval} = ‘11000’ → offset = –2.5 µA; {txosXon,txosXval} = ‘10001’ → offset = 5.0 µA etc.
10–13
txosIval
Tx offset correction, I channel, value (sign plus three bits)
14
txosIon
Tx offset correction, I channel ON
15–18
txsoQval
Tx offset correction, Q channel, value (sign plus three bits)
19
txosQon
Tx offset correction, Q channel ON
Table 22. Address 08: VCO settings
Bit
23
22
21
20
19
x
x
x
x
x
name
default
18
17
16
15
14
13
12
11
10
9
x
x
x
x
0
these bits do not exist on IC
x
x
x
x
x
8
7
not used
0
0
6
5
4
‘0’
‘0’
vcerr
0
0
0
3
2
1
0
vcoband
0
0
0
0
Bit #
Name
Description
0–3
vcoband
VCO band.
Write: with test mode, these bits set the VCO band.
Read: in normal mode, the result ot the calibration (VCOCAL) can be read out here (0000 = highest frequencies).
4
vcerr
VCO calibration error flag (no band with low enough frequency could be found).
2002 Nov 04
23
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
14.4.2 Programming Example
SA2400A
14.5 Fast serial interface for Receiver–AGC
programming
Program synthesizer for 2.412 GHz band
• Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz ⇒
When the chip is in mode “FASTTXRXMGC” the internal AGC block
is disabled. Instead, the 10 bits controlling the receiver gain and the
two bits controlling the DC offset cancellation corner frequency can be
programmed directly via a dedicated second serial interface. This
interface is active when in FASTTXRXMGC mode and when
SEN=HIGH. (SEN acts as a switch between the regular serial
interface and the dedicated bus).
reference division ratio R = 11
• Target frequency is 2412 MHz, fcomp = 4 MHz ⇒ main divider ratio
N = 603 (no fractional N)
– write this word to register 00: 00 0 000 0000001001011011 00
(note two leading zeros – unused bits 22, 23)
14.5.1 Description of “fast programming” cycle
1. Set the chip to FASTTXRXMGC mode by programming
register 4 with the correct value.
2. Set the SEN pin to HIGH.
3. With each rising edge on pin SCLK, a new data bit is expected at
pin AGCRESET. No address is needed. The sequence of the
bits is the same as described for register 6, bits 0–11. The
programming order is LSB first.
4. With the 12th rising edge on SCLK, an internal counter will
automatically parallel-load the shifted-in data bits into an internal
register. The bits will immediately effect the receiver settings.
5. The regular 3-wire bus is still accessible and can be
programmed when SEN is LOW. Clock activity on SCLK will not
affect receiver gain settings when SEN is LOW.
– write this word to register 01: 00 0000001011 00 1 0 xxxxxxxx
(x = no significance)
Program synthesizer for 2.462 GHz band
• Input Xtal is 44 MHz, comparison frequency fcomp = 4 MHz ⇒
reference division ratio R = 11
• Target frequency is 2462 MHz, fcomp = 4 MHz ⇒ main divider ratio
N = 615.5 (fractional 4/8)
– write this word to register 00: 00 0 100 0000001001100111 00
– write this word to register 01: 00 0000001011 00 1 0 01010000
Fractional compensation setting should be set in the application
(depends on the loop parameters) with the help of the SA8027
application note. The nominal value is FC = 640 / FM
(FM = modulus, see address 00).
Tcyc
tr
tf
1
2
31
32
A0
A1
D23
D23
1
2
3
4
5
11
12
1
SCLK
SEN
SDATA
XX
A0
D0
AGCRESET
D1
D2
D3
Ton
D4
D10
D11
XX
Tsetup
Thold
3–WIRE BUS PROGRAMMING
SR02311
“FAST BUS” PROGRAMMING
Figure 11. “Fast programming” cycle timing diagram
14.6 Fast serial interface AC characteristics
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
Min
Typ
Max
UNITS
Serial Bus Logic Level Requirements
VIH
HIGH logic input voltage
0.5×VDD
–
VDD + 0.3
V
VIL
LOW logic input voltage
–0.3
–
0.2×VDD
V
Serial Programming Clock, SCLK
tr
Input rise time
–
10
40
ns
tf
Input fall time
–
10
40
ns
Tcyc
Clock period
22
100
–
ns
10
–
–
ns
Enable Programming, SEN
Ton
Delay to rising clock edge
Data Programming, AGCRESET
Tsetup
Input data to clock set-up time
10
–
–
ns
Thold
Input data to clock hold time
10
–
–
ns
2002 Nov 04
24
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
15. PERFORMANCE CURVES
30.5
3.5
SIDE BAND REJECTION (dB)
3.0
TIME (µs)
2.5
2.0
1.5
1.0
FREQ. (µs)
0.5
30.0
29.5
29.0
28.5
28.0
Pout (µs)
0
–40
–15
10
35
60
27.5
–40
85
–15
TEMPERATURE (°C)
10
35
60
SR02418
SR02420
Figure 12. TX to RX switching time versus temperature
(VDD = 3.3 V)
Figure 15. RX residual sideband suppression versus
temperature (VDD = 3.3 V)
32.5
3.5
32.0
SIDE BAND REJECTION (dB)
4.0
TIME (µs)
3.0
2.5
2.0
1.5
1.0
FREQ. (µs)
0.5
31.5
31.0
30.5
30.0
29.5
29.0
Pout (µs)
0
28.5
2.7
3.0
3.3
3.6
2.7
3.0
SUPPLY VOLTAGE, VDD (V)
3.3
3.6
SUPPLY VOLTAGE, VDD (V)
SR02419
SR02821
Figure 13. TX to RX switching time versus supply voltage
(Tamb = 25 °C)
Figure 16. RX residual sideband suppression versus
supply voltage (Tamb = 25 °C)
30
0
25
–10
20
POWER (dBm)
NOISE FIGURE (dB)
85
TEMPERATURE (°C)
2.7V
15
2.85V
10
–20
–30
–40
3V
3.3V
–50
5
3.6V
0
–85
–60
–75
–65
–55
–45
9.50E+07
INPUT POWER (dBm)
9.90E+07
1.01E+08
1.03E+08
1.05E+08
FREQUENCY (Hz)
SR02427
SR02822
Figure 14. Noise Figure versus input power
2002 Nov 04
9.70E+07
Figure 17. Spectrum of RX sideband rejection at 4 MHz offset
25
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
ERROR VECTOR MAGNITUDE (%)
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE, VDD (V)
SR02460
SR02824
Figure 18. TX ramp-up (1 µs/div).
Figure 21. Transmitter error vector magnitude (EVM) versus
supply voltage (Tamb = 25 °C).
3.5
25
LOW
3.0
HIGH
2.5
TIME (µs)
NF (dB)
20
15
2.0
1.5
1.0
10
FREQ. (µs)
0.5
5
–85
–80
–75
–70
–65
–60
–55
–50
–45
0
–40
–40
Pout (µs)
–15
10
Pin (dBm)
35
60
SR02461
SR02425
Figure 19. Noise Figure vs. input power
for two LNA switching modes.
Figure 22. RX to TX switching time versus temperature
(VDD = 3.3 V).
12
3.5
3.0
10
2.5
8
TIME (µs)
ERROR VECTOR MAGNITUDE (%)
85
TEMPERATURE (°C)
6
2.0
1.5
4
1.0
FREQ. (µs)
2
0
–40
0.5
–15
10
35
60
0
2.7
85
TEMPERATURE (°C)
3.0
3.3
3.6
SUPPLY VOLTAGE, VDD (V)
SR02423
SR02426
Figure 20. Transmitter error vector magnitude (EVM) versus
temperature (VDD = 3.3 V).
2002 Nov 04
Pout (µs)
Figure 23. RX to TX switching time versus supply voltage
(Tamb = 25 °C).
26
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
SR02459
Figure 24. TX constellation and EVM.
2002 Nov 04
27
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
6.00
5.00
2.70 V
4.00
MEAN (µA)
3.00
2.85 V
2.00
1.00
3.00 V
0.00
3.30 V
–1.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02445
Figure 25. Total sleep ICC.
124.00
2.70 V
120.00
MEAN (MHz)
2.85 V
116.00
3.00 V
112.00
3.30 V
108.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02446
Figure 26. VCO 0011 bandwidth.
2448.00
2.70 V
2420.00
2.85 V
MEAN (MHz)
2392.00
3.00 V
3.30 V
2364.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02447
Figure 27. VCO 0111 f1.
105.00
2.70 V
96.00
2.85 V
MEAN (mA)
87.00
3.00 V
3.30 V
78.00
–30
0
25
70
TEMPERATURE (°C)
85
3.60 V
SR02448
Figure 28. Total TX LOW ICC.
2002 Nov 04
28
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
0.00
2.70 V
MEAN (dBm)
2.85 V
–5.00
3.00 V
3.30 V
–10.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02449
Figure 29. Output power TX LOW, g = 1111.
160.00
2.70 V
150.00
MEAN (mA)
2.85 V
140.00
3.00 V
130.00
3.30 V
120.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02450
Figure 30. Total TX HIGH ICC.
10.00
2.70 V
MEAN (dBm)
2.85 V
5.00
3.00 V
3.30 V
0.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02451
Figure 31. Output power TX HIGH, g = 1111.
–108.00
2.70 V
–110.00
2.85 V
MEAN (dBc/Hz)
–112.00
3.00 V
3.30 V
–114.00
–30
0
25
70
85
TEMPERATURE (°C)
3.60 V
SR02452
Figure 32. PLL phase noise @ 500 kHz.
2002 Nov 04
29
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
–34.00
2.70 V
–41.00
2.85 V
MEAN (dBc)
–48.00
3.00 V
–55.00
3.30 V
–62.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02453
Figure 33. TX HIGH spectral mask, adjacent channel.
–30.00
2.70 V
–40.00
2.85 V
MEAN (dBc)
–50.00
3.00 V
3.30 V
–60.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02454
Figure 34. TX LOW spectral mask, adjacent channel.
104.00
2.70 V
98.00
2.85 V
MEAN (mA)
92.00
3.00 V
86.00
3.30 V
80.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02455
Figure 35. Total RX ICC.
94.00
2.70 V
92.00
90.00
MEAN (dB)
2.85 V
88.00
3.00 V
86.00
3.30 V
84.00
–30
0
25
70
TEMPERATURE (°C)
85
3.60 V
SR02456
Figure 36. RXMGC I max gain.
2002 Nov 04
30
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
94.00
2.70 V
92.00
90.00
MEAN (dB)
2.85 V
88.00
3.00 V
86.00
3.30 V
84.00
–30
0
25
70
85
3.60 V
TEMPERATURE (°C)
SR02457
Figure 37. RXMGC Q max gain.
6.85
2.70 V
6.70
MEAN (MHz)
2.85 V
6.55
3.00 V
6.40
3.30 V
6.25
–30
0
25
70
85
TEMPERATURE (°C)
3.60 V
SR02458
Figure 38. RX filter ripple bandwidth.
2002 Nov 04
31
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
2002 Nov 04
32
SA2400A
SOT313-2
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
REVISION HISTORY
Rev
Date
Description
_1
20021104
Product data; initial version.
Engineering Change Notice 853–2320 28727 (date: 20020809).
2002 Nov 04
33
SA2400A
Philips Semiconductors
Product data
Single chip transceiver for 2.45 GHz ISM band
SA2400A
Data sheet status
Level
Data sheet status [1]
Product
status [2] [3]
Definitions
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 11-02
For sales offices addresses send e-mail to:
[email protected].
Document order number:
2002 Nov 04
34
9397 750 09632