PHILIPS SA8027

INTEGRATED CIRCUITS
SA8027
2.5 GHz low voltage, low power
RF fractional-N/IF integer
frequency synthesizer
Product data
Supersedes data of 2001 Jul 18
2001 Aug 21
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
GENERAL DESCRIPTION
The SA8027 BICMOS device integrates programmable dividers,
charge pumps and phase comparators to implement phase-locked
loops. The device is designed to operate from 3 NiCd cells, in
pocket phones, with low current and nominal 3 V supplies.
The synthesizer operates at VCO input frequencies up to 2.5 GHz.
The synthesizer has fully programmable main, auxiliary and
reference dividers. All divider ratios are supplied via a 3-wire serial
programming bus. The main divider is a fractional-N divider with
programmable integer ratios from 512 to 65535.
Separate power and ground pins are provided to the charge pumps
and digital circuits. The ground pins should be externally connected
to prevent large currents from flowing across the die and causing
damage. VDDCP must be equal to or greater than VDD.
LOCK
1
20 PON
TEST
2
19 STROBE
VDD
3
18 DATA
GND
4
17 CLOCK
RFin+
5
16 REFin+
RFin–
6
15 REFin–
GNDCP
7
14 RSET
PHP
8
13 VDDCP
PHI
9
12 AUXin
11 PHA
GNDCP 10
SR01649
TEST
LOCK
PON
STROBE
DATA
1
24
23
22
21
20
19
GND
2
18
CLOCK
GNDPre
3
17
REFin+
RFin+
4
RFin–
5
GNDCP
RSET
6
14
VDDCP
7
8
9
13
N/C
10
11
12
N/C
REFin–
15
PHA
TOP VIEW
AUXin
16
GNDCP
APPLICATIONS
• 500 to 2500 MHz wireless equipment
• Cellular phones (all standards)
• WLAN
• Portable battery-powered radio equipment.
VDDPre
PHI
FEATURES
• Low phase noise
• Low power
• Fully programmable main and auxiliary dividers
• Programmable Normal & Integral charge pumps outputs
• Fast Locking Adaptive mode design
• Internal fractional spurious compensation
• Hardware and software power down
• Split supply for VDD and VDDCP
• Loop filter bandwidth programmability
PHP
The charge pump current (gain) is fully programmable, while ISET is
set by an external resistance at the RSET pin (refer to section 1.5,
Main Output Charge Pumps and Fractional Compensation
Currents). The phase/frequency detector charge pump outputs allow
for implementing a passive loop filter.
V DD
Figure 1. TSSOP20 Pin Configuration
SR02176
Figure 2. HBCC24 Pin configuration
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDD
Supply voltage
CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.7
–
3.6
VDDCP
Analog supply voltage
V
VDDCP w VDD
2.7
–
3.6
IDDCP+IDD
Supply current
V
Main and Aux. on
–
7.7
–
IDDCP+IDD
mA
Total supply current in power-down mode
–
1
–
µA
fVCO
Input frequency
500
–
2500
MHz
fAUX
Input frequency
100
–
550
MHz
fREF
Crystal reference input frequency
5
–
40
MHz
fPC
Maximum phase comparator frequency
–
4
MHz
Tamb
Operating ambient temperature
–40
+85
°C
–
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
SA8027DH
TSSOP20
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
SA8027W
HBCC24
Plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm (Note 1)
SOT564-1
NOTE:
1. The SA8027W will be released for production Q2, 2001.
2001 Aug 21
2
853–2244 26947
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
17
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
ADDRESS DECODER
CONTROL
LATCH
CLOCK
DATA
STROBE
18
19
SA8027
VDD
VDDCP
3
13
PUMP
CURRENT
SETTING
14
PUMP
BIAS
RSET
LOAD SIGNALS
FRAC
COMP
LATCH
5
RF/MAINin+
RF/MAINin–
MAIN DIVIDER
6
8
PHASE
DETECTOR
PHP
AMP
SM
9
LATCH
PHI
16
REFin+
REFERENCE
DIVIDER
REFin–
2 2 22
15
LOCK
SELECT
SA
LATCH
IF/AUXin
1
PHASE
DETECTOR
12
AUX DIVIDER
LOCK
11
PHA
20
PON
AMP
TEST
2
4
7, 10
GND
GNDCP
SR02357
Figure 3. Block Diagram (TSSOP20)
TSSOP20 PIN DESCRIPTION
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
LOCK
1
Lock detect output
PHA
11
Auxiliary charge pump output
TEST
2
Test (should be either grounded or
connected to VDD)
AUXin
12
Input to auxiliary divider
VDDCP
13
Charge pump supply voltage
RSET
14
External resistor from this pin to ground
sets the charge pump current
VDD
3
Digital supply
GND
4
Digital ground
RFin+
5
RF input to main divider
REFin–
15
Reference input
RFin–
6
RF input to main divider
REFin+
16
Reference input
GNDCP
7
Charge pump ground
CLOCK
17
Programming bus clock input
PHP
8
Main normal charge pump
DATA
18
Programming bus data input
PHI
9
Main integral charge pump
STROBE
19
Programming bus enable input
GNDCP
10
Charge pump ground
PON
20
Power down control
2001 Aug 21
3
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
18
2–BIT SHIFT
REGISTER
22–BIT SHIFT
REGISTER
ADDRESS DECODER
CONTROL
LATCH
CLOCK
DATA
STROBE
19
20
SA8027
VDD
VDDpre
VDDCP
24
1
14
PUMP
CURRENT
SETTING
15
PUMP
BIAS
RSET
LOAD SIGNALS
FRAC
COMP
LATCH
4
RF/MAINin+
RF/MAINin–
MAIN DIVIDER
5
7
PHASE
DETECTOR
PHP
AMP
SM
8
LATCH
PHI
17
REFin+
REFERENCE
DIVIDER
REFin–
2 2 22
16
LOCK
SELECT
SA
LATCH
IF/AUXin
22
PHASE
DETECTOR
11
AUX DIVIDER
LOCK
10
PHA
21
PON
AMP
TEST
23
2
3
6, 9
GND
GNDpre
GNDCP
SR02358
Figure 4. Block Diagram (HBCC24)
HBCC24 PIN DESCRIPTION
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
VDDPre
1
Prescaler supply voltage
VDDCP
14
Charge pump supply voltage
GND
2
Digital ground
RSET
15
GNDPre
3
Prescaler ground
External resistor from this pin to ground
sets the charge pump current
RFin+
4
RF input to main divider
REFin–
16
Reference input
REFin+
17
Reference input
CLOCK
18
Programming bus clock input
DATA
19
Programming bus data input
STROBE
20
Programming bus enable input
PON
21
Power down control
LOCK
22
Lock detect output
TEST
23
Test (should be either grounded or
connected to VDD)
VDD
24
Digital supply
RFin–
5
RF input to main divider
GNDCP
6
Charge pump ground
PHP
7
Main normal charge pump
PHI
8
Main integral charge pump
GNDCP
9
Charge pump ground
PHA
10
Auxiliary charge pump output
AUXin
11
Input to auxiliary divider
N/C
12
Not connected
N/C
13
Not connected
2001 Aug 21
4
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
Limiting values
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
Digital supply voltage
–0.3
+3.6
V
VDDCP
Analog supply voltage
–0.3
+3.6
V
∆(VDDCP–VDD)
Difference in voltage between VDDCP and VDD (VDDCP ≥ VDD)
–0.3
+0.9
V
Vin
All input pins
–0.3
VDD + 0.3
V
∆VGND
Difference in voltage between GNDCP and GND (these pins should be
connected together)
–0.3
+0.3
V
Tstg
Storage temperature
–55
+125
°C
Tamb
Operating ambient temperature
–40
+85
°C
Tj
Maximum junction temperature
150
°C
Thermal characteristics
SYMBOL
Rth j–a
2001 Aug 21
PARAMETER
Thermal resistance from junction to ambient in free air
5
VALUE
UNIT
135
K/W
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
CHARACTERISTICS
VDDCP = VDD = +3.0 V, Tamb = +25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
Digital supply voltage
VDDCP
Analog supply voltage
VDDCP w VDD
2.7
–
3.6
V
2.7
–
3.6
V
ITotal
Synthesizer operational supply current
VDD = +3.0 V
(with main and aux on)
–
7.7
–
mA
IStandby
Total supply current in power-down mode
logic levels 0 or VDD
–
1
–
µA
500
–
2500
MHz
–18
–
0
dBm
80
–
632
mVPP
RFin main divider input
fVCO
VCO input frequency
VRFin
AC-coupled input signal level
Rin (external) = Rs = 50 Ω;
single-ended
drive;
g
max. limit is indicative
@ 500 to 2500 MHz
ZRFin
Input impedance (real part)
fVCO = 2.4 GHz
–
300
–
Ω
CRFin
Typical pin input capacitance
fVCO = 2.4 GHz
–
1
–
pF
Nmain
Main divider ratio
512
–
65535
fPCmax
Maximum loop comparison frequency
–
–
4
MHz
100
–
550
MHz
–15
–
0
dBm
112
–
632
mVPP
indicative, not tested
AUX divider input
fAUXin
Input frequency range
Rin (external)
(
) = RS = 50 Ω;
max. limit is indicative
VAUXin
AC coupled input signal level
AC-coupled
ZAUXin
Input impedance (real part)
fVCO = 500 MHz
–
3.9
–
kΩ
CAUXin
Typical pin input capacitance
fVCO = 500 MHz
–
0.5
–
pF
NAUX
Auxiliary division ratio
128
–
16383
5
–
40
MHz
360
–
1300
mVPP
Reference divider input
fREFin
Input frequency range from TCXO
VREFin
AC-coupled input signal level
single-ended drive;
max. limit is indicative
ZREFin
Input impedance (real part)
fREF = 20 MHz
–
10
–
kΩ
CREFin
Typical pin input capacitance
fREF = 20 MHz
–
1
–
pF
RREF
Reference division ratio
SA = SM = ”000”
4
–
1023
6
7.5
15
kΩ
–
1.22
–
V
Charge pump current setting resistor input
RSET
External resistor from pin to ground
VSET
Regulated voltage at pin
RSET = 7.5 kΩ
Charge pump outputs; RSET = 7.5 kΩ
ICP
Charge pump current ratio to ISET1
IMATCH
Sink-to-source current matching
IZOUT
Output current variation versus VPH
ILPH
Charge pump off leakage current
VPH
Charge pump voltage compliance
2001 Aug 21
2
Current gain = IPH/ISET
–15
+15
%
VPH = 1/2 VDDCP
–10
+10
%
VPH in compliance range
–10
+10
%
VPH = 1/2 VDDCP
–10
+10
nA
VDDCP–0.7
V
0.6
6
–
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
CHARACTERISTICS (continued)
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
GSM
–
–90
–
dBc/Hz
–
–83
–
dBc/Hz
–
–85
–
dBc/Hz
–
–77
–
dBc/Hz
Phase noise (condition RSET = 7.5 kΩ, CP = 00)
Synthesizer’s contribution to close-in phase noise
of 900 MHz RF signal at 1 kHz offset.
L(f)
Synthesizer’s contribution to close-in phase noise
of 1800 MHz RF signal at 1 kHz offset.
Synthesizer’s contribution to close-in phase noise
of 800 MHz RF signal at 1 kHz offset.
Synthesizer’s contribution to close-in phase noise
of 2100 MHz RF signal at 1 kHz offset.
fREF = 13MHz, TCXO,
fCOMP = 1MHz
indicative, not tested
TDMA
fREF = 19.44MHz, TCXO,
fCOMP = 240kHz
indicative, not tested
Interface logic input signal levels
VIH
HIGH level input voltage
0.7*VDD
–
VDD+0.3
V
VIL
LOW level input voltage
–0.3
–
0.3*VDD
V
ILEAK
Input leakage current
–0.5
–
+0.5
µA
–
–
0.4
V
VDD–0.4
–
–
V
logic 1 or logic 0
Lock detect output signal (in push/pull mode)
VOL
LOW level output voltage
Isink = 2 mA
VOH
HIGH level output voltage
Isource = –2 mA
NOTES:
V SET
bias current for charge pumps
1. I SET + R
SET
2. The relative output current variation is defined as:
DI OUT
(I 2 * I 1)
+2
; with I 1 @ V 1 + 0.6 V, I 2 @ V 2 + V DDCP –0.7 V (See Figure 5.)
|I 2 ) I 1|
I OUT
CURRENT
IZOUT
I2
I1
VOLTAGE
V1
V2
VPH
I2
I1
SR00602
Figure 5. Relative Output Current Variation
2001 Aug 21
7
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
1.0 FUNCTIONAL DESCRIPTION
1.2 Auxiliary divider
The AUXin input drives a pre-amplifier to provide the clock to the
first divider stage. The pre-amplifier has a high input impedance,
dominated by pin and pad capacitance. The circuit operates with
signal levels from –15 dBm to 0 dBm (112 to 632 mVpp), and at
frequencies as high as 550 MHz. The divider consists of a fully
programmable bipolar prescaler followed by a CMOS counter. Total
divide ratios range from 128 to 16383.
1.1 Main Fractional-N divider
The RFin inputs drive a pre-amplifier to provide the clock to the first
divider stage. For single ended operation, the signal should be fed to
one of the inputs while the other one is AC grounded. The
pre-amplifier has a high input impedance, dominated by pin and pad
capacitance. The circuit operates with signal levels from –18 dBm to
0 dBm, and at frequencies as high as 2.5 GHz. The divider consists
of a fully programmable bipolar prescaler followed by a CMOS
counter. Total divide ratios range from 512 to 65535.
1.3 Reference divider
The reference divider consists of a divider with programmable
values between 4 and 1023 followed by a three bit binary counter.
The 3 bit SM (SA) register (see Figure 6) determines which one of
the 5 output pulses are selected as the main (auxiliary) phase
detector input, thus allowing the main PFD and auxiliary PFD to
operate at different frequencies.
The fractional modulus is selected by programming FMOD in the
A word. There are 2 modulus to select from: when FMOD = 0,
modulo 8 is selected; when FMOD = 1, modulo 5 is selected.
At the completion of a main divider cycle, a main divider output
pulse is generated which will drive the main phase comparator. Also,
the fractional accumulator is incremented by the value of NF. The
accumulator works with modulo set by FMOD. When the
accumulator overflows, the overall division ratio N will be increased
by 1, to N + 1. The average division ratio over modulo main divider
cycles (either 5 or 8) will be
ǒ
Nfrac + N ) NF
f MOD
SA8027
1.4 Phase detector (see Figure 7)
The reference and main (aux) divider outputs are connected to a
phase/frequency detector that controls the charge pump. The pump
current is set by an external resistor in conjunction with control bits
CP0 and CP1 in the C-word (see Table 1). The dead zone (caused
by finite time taken to switch the current sources on or off) is
cancelled by forcing the pumps ON for a minimum time (τ) at every
cycle (backlash time) providing improved linearity.
Ǔ
The output of the main divider will be modulated with a fractional
phase ripple. The phase ripple is proportional to the contents of the
fractional accumulator and is nulled by the fractional compensation
charge pump. Thus, fVCO = fcomp *
ǒ
N ) NF
f MOD
Ǔ
.
The reloading of a new main divider ratio is synchronized to the
state of the main divider to avoid introducing a phase disturbance.
SM=”000”
SM=”001”
SM=”010”
SM=”011”
TO
MAIN
PHASE
DETECTOR
SM=”100”
REFERENCE
INPUT
DIVIDE BY R
/2
/2
/2
/2
SA=”100”
SA=”011”
SA=”010”
TO
AUXILIARY
PHASE
DETECTOR
SA=”001”
SA=”000”
SR01415
Figure 6. Reference Divider
2001 Aug 21
8
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
VCC
“1”
fREF
REF DIVIDER
P–TYPE
CHARGE PUMP
P
D
Q
CLK
R
R
τ
“1”
AUX/MAIN
DIVIDER
D
IPH
R
N–TYPE
CHARGE PUMP
CLK
Q
X
N
GND
fREF
R
X
τ
P
τ
N
IPH
SR01451
Figure 7. Phase Detector Structure with Timing
2001 Aug 21
9
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
The compensation is done by sourcing a small current, ICOMP, see
Figure 9, that is proportional to the fractional error phase. For proper
fractional compensation, the area of the fractional compensation
current pulse must be equal to the area of the fractional charge
pump ripple. The width of the fractional compensation pulse is fixed
to 128 VCO cycles, the amplitude is proportional to the fractional
accumulator value and is adjusted by FDAC values (bits FC7–0 in
the B-word). The fractional compensation current is derived from the
main charge pump in that it follows all the current scaling through
external resistor setting, RSET, programming or speed-up operation.
For a given charge pump,
1.5 Main Output Charge Pumps and Fractional
Compensation Currents (see Figure 8)
The main charge pumps on pins PHP and PHI are driven by the
main phase detector and the charge pump current values are
determined by the current at pin RSET in conjunction with bits CP0,
CP1 in the C-word (see Table 1). The main charge pumps will enter
speed up mode after the A-word is set and strobe goes High. When
strobe goes Low, charge pump will exit speed up mode. The
fractional compensation is derived from the current at RSET, the
contents of the fractional accumulator (FRD) and by the program
value of the FDAC. The timing for the fractional compensation is
derived from the main divider.
ICOMP = ( IPUMP / 128 ) * ( FDAC / 5*128) * FRD
FRD is the fractional accumulator value and is automatically
updated.
1.6 Principle of Fractional Compensation
The fractional compensation is designed into the circuit as a means
of reducing or eliminating fractional spurs that are caused by the
fractional phase ripple of the main divider. If ICOMP is the
compensation current and IPUMP is the pump current, then for each
charge pump:
The theoretical values for FDAC are: 128 for FMOD = 1 (modulo 5)
and 80 for FMOD = 0 (modulo 8).
IPUMP_TOTAL = IPUMP + ICOMP.
REFERENCE R
MAIN M DIVIDE RATIO
N
N
N+1
N
N+1
CHARGE PUMP OUTPUT
2
4
1
3
0
ACCUMULATOR VALUE (FRD)
FRACTIONAL COMPENSATION
CURRENT (ICOMP)
PULSE
WIDTH
MODULATION
mA
IPUMP–TOTAL
µA
PULSE LEVEL
MODULATION
SR02359
GRAPHS NOT TO SCALE.
NOTE: For a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump output.
Figure 8. Waveforms for NF = 2 Modulo 5 → fraction = 2/5
fRF
FRACTIONAL
ACCUMULATOR
MAIN DIVIDER
ICOMP
IPUMP
fREF
Σ
LOOP FILTER
& VCO
SR01800
Figure 9. Current Injection Concept
2001 Aug 21
10
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
1.7 Charge Pumps
SA8027
Table 1. Main and auxiliary charge pump currents
The PHP and PHI charge pumps are driven by the main phase
detector, while the PHA charge pump is driven by the auxiliary
phase detector. The ISET value (refer to Table 1) is determined by
the external resistor attached to the RSET pin.
The charge pump, by default, will automatically go into speed-up
mode (which can deliver up to 15*ISET for PHP_SU, and 36*ISET for
PHI), based on the strobe pulse width following the A word, to
reduce switching speed for large tuning voltage steps (i.e., large
frequency steps). Figure 10 shows the recommended passive loop
filter configuration. Note: This charge pump architecture eliminates
the need for added active switches and reduces external component
count. Furthermore, the programmable charge pump gains provide
some programmability to the loop filter bandwidth.
CP1
CP0
IPHA
IPHP
IPHP–SU
IPHI
0
0
1.5xlSET
3xISET
15xlSET
36xlSET
0
1
0.5xlSET
1xlSET
5xlSET
12xlSET
1
0
1.5xlSET
3xlSET
15xlSET
0
1
1
0.5xlSET
1xlSET
5xlSET
0
NOTES:
1. ISET = VSET/RSET: bias current for charge pumps.
2. CP1 is used to disable the PHI pump, IPHP–SU is the total current
at pin PHP during speed up condition.
1.8 Lock Detect
The duration of speed-up mode is determined by the strobe pulse
width following the A word. Recommended optimal strobe width is
equal to the total loop filter capacitance charge time from state 1 to
state 2. The strobe width must not exceed this charge time. The
strobe width is controlled by the CPU (× number of clock cycles).
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector (AND/ORed) with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than "1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock
(logic ‘0’) is indicated when both counters are powered down.
In addition, charge pumps will stay in speed-up mode continuously
while Tspu = 1 (in D word). The speed-up mode can also be
disabled by programming Tdis-spu = 1 (in D word).
1.9 Power-down mode
R2
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits in
B-word. If PON = 0, then the part is powered up when PD = 1. PON
can be used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after power-down, the main and reference
dividers are synchronized to avoid possibility of random phase
errors on power-up.
VCO
PHP[PHP–SU]
R1
C2
PHI
C3
C1
SR02356
Figure 10. Typical passive 3-pole loop filter
2001 Aug 21
11
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
sent: C, B, and A, in that order. A typical programming sequence is
illustrated in Figure 12. Table 2 shows the format and the contents of
each word. The D word is used for testing purposes and should be
initially set to 0 for normal operation. When sending the B-word, data
bits FC7–0 for the fractional compensation DAC are not loaded
immediately. Instead they are stored in temporary registers. Only
when the A-word is loaded, these temporary registers are loaded
together with the main divider ratio.
2.0 SERIAL PROGRAMMING BUS
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter divide ratios, fractional compensation DAC,
selection and enable bits. The programming data is structured into
24 bit words; each word includes 2 or 3 address bits. Figure 11
shows the timing diagram of the serial input. When the STROBE
goes active HIGH, the clock is disabled and the data in the shift
register remains unchanged. Depending on the address bits, the
data is latched into the selected working registers or temporary
registers. In order to fully program the synthesizer, 3 words must be
2.1 Serial bus timing characteristics (see Figure 11)
VDD = VDDCP =+3.0 V; Tamb = +25 °C unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
tr
Input rise time
–
10
40
ns
tf
Input fall time
–
10
40
ns
Tcy
Clock period
100
–
–
ns
40
–
–
ns
1/fCOMP
–
–
ns
20
–
–
ns
Enable programming; STROBE
tSTART
Delay to rising clock edge
tW
Minimum inactive pulse width
tSU;E
Enable set-up time to next clock edge
Register serial input data; DATA
tSU;DAT
Input data to clock set-up time
20
–
–
ns
tHD;DAT
Input data to clock hold time
20
–
–
ns
Application information
tSU;DAT
tHD;DAT
tf
Tcy
tSU;E
tr
CLK
≥0
LSB
DATA
MSB
ADDRESS
STROBE
tw
tSTART
SR01417
Figure 11. Serial Bus Timing Diagram
2001 Aug 21
12
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
POWER–ON
PROGRAM D WORD
– SET DEFAULT
PROGRAM C WORD
– SELECT SA, SM
– SET CHARGE PUMP GAIN
– SET AUX DIVIDER
PROGRAM B WORD
– SELECT FDAC
– SET POWER-UP OPTION
– SET LOCK DETECT
– SET REF DIVIDER
PROGRAM A WORD
– SELECT MAIN DIVIDER
– SET FRACTIONAL-N
– SET FMOD
READY TO OPERATE
PROGRAM A WORD
Y
CHANGE
MAIN
FREQUENCY
N
CHANGE
FDAC
Y
N
PROGRAM C WORD
Y
CHANGE
AUX
FREQUENCY
N
PROGRAM B WORD
Y
POWER
DOWN
N
PROGRAM B WORD
Y
POWER
UP
N
POWER
OFF
SR02360
Figure 12. Typical programming sequence
2001 Aug 21
13
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
Data format
Table 2. Format of programmed data
Last In
MSB
p23
p22
Serial Programming Format
p21
p20
../..
First In LSB
../..
p1
p0
Table 3. A word, length 24 bits
Last In
MSB
Address
0
LSB
First In
fmod
Fractional-N
fmod
NF2
NF1
NF0
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
SK1
SK2
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
Default
Main Divider ratio
Spare
A word address
Fixed to 00.
Fractional Modulus select
fmod = 0 is modulo 8; fmod = 1 is modulo 5.
Fractional-N Increment
Fractional-N Increment values 000 to 111 (0 to 7). NF is a 3-bit word.
N-Divider
N0..N15, Main divider values 512 to 65535 allowed for divider ratio.
Spare
SK1, SK2 must be set to 0.
Table 4. B word, length 24 bits
Address
0
Reference Divider
1
Default
Lock
PD
FDAC (Fractional Compensation DAC)
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
L1
L0
Main
Aux
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
0
0
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
0
B word address
Fixed to 01
REF-Divider
R0..R9, Reference divider values 4 to 1023 allowed for divider ratio. R <9:0>.
Lock detect output
L1 L0
0 0 Combined main, aux. lock detect signal present at the LOCK pin (push/pull).
0 1 Combined main, aux, lock detect signal present at the LOCK pin (open drain).
1 0 Main lock detect signal present at the LOCK pin (push/pull).
1 1 Auxiliary loop lock detect signal present at the LOCK pin (push/pull).
When auxiliary loop and main loop are in power down mode, the lock indicator is low.
Power down (PD)
PON pin is tied to GND
Main = 1: power-on to Main PLL. Main = 0: power-down to Main PLL.
Aux = 1: power-on to Aux PLL. Aux = 0: power-down to Aux PLL.
PON pin is tied to VDD
Main = 0: power-on to Main PLL. Main = 1: power-down to Main PLL.
Aux = 0: power-on to Aux PLL. Aux = 1: power-down to Aux PLL.
Fractional Compensation
FC7..0 Fractional Compensation charge pump current DAC, values 0 to 255.
Table 5. C word, length 24 bits
Address
1
Auxiliary Divider
0
Default
CP
SM
SA
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CP1
CP0
SM2
SM1
SM0
SA2
SA1
SA0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
0
0
0
0
0
0
C word address
Fixed to 10
A-Divider
A0..A13, Auxiliary divider values 128 to 16383 allowed for divider ratio.
Charge pump current Ratio
CP1, CP0: Charge pump current ratio, see Table 1.
Main comparison select
SM comparison divider select for main phase detector.
Aux comparison select
SA Comparison divider select for auxiliary phase detector.
Table 6. D word, length 24 bits
Address
1
1
Synthesizer Test Bits
0
Default
–
–
–
–
Tdis-spu
Tspu
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D word address
Fixed to 110.
Tdis-spu = 1
Speed-up mode disabled. NOTE: All other test bits must be set to 0 for normal operation.
Tspu = 1
Speed-up mode always on. NOTE: All other test bits must be set to 0 for normal operation.
2001 Aug 21
14
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS
SR02332
SR02331
Figure 14. PHI Charge Pump Output vs. Temperature
(CP = 01_12x; VDD = 3.0 V; ISET = 164 mA)
–6000
ISET = 204 µA
–8000
0.00
3.00
2.75
2.50
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02334
SR02333
Figure 16. PHI Charge Pump Output vs. Temperature
(CP = 00_36x; VDD = 3.0 V; ISET = 164 mA)
–200
ISET = 164 µA
–400
–600
–400
ISET = 204 µA
–600
–800
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
–800
COMPLIANCE VOLTAGE
COMPLIANCE VOLTAGE (V)
SR02335
SR02336
Figure 17. PHP Charge Pump Output vs. ISET
(CP = 10_3x; VDD = 3.0 V; Temp = 25_C)
2001 Aug 21
+85 °C
3.00
0
–40 °C
+25 °C
2.50
ISET = 81 µA
–200
200
2.25
0
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎ
Î
ÎÎ
Î
Î
Î
ÎÎ ÎÎ
Î
Î
Î
ÎÎ
ÎÎÎÎÎÎÎÎÎÎ
2.00
400
1.75
ISET = 81 µA
200
1.50
600
1.25
ISET = 164 µA
1.00
800
Icp (uA)
Icp (uA)
400
ISET = 204 µA
0.75
600
0.50
800
0.25
Figure 15. PHI Charge Pump Output vs. ISET
(CP = 00_36x; Temp = 25 _C)
2.75
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
–8000
3.00
ISET = 164 µA
2.75
–4000
–4000
+85 °C
2.50
–2000
ISET = 81 µA
2.25
0
–40 °C
+25 °C
2.00
0
2000
1.75
Icp (uA)
Icp (uA)
ISET = 81 µA
2000
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
Î
Î
ÎÎ Î
Î
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
1.50
4000
4000
1.25
6000
ISET = 164 µA
1.00
6000
0.75
ISET = 204 µA
0.50
8000
8000
0.25
Figure 13. PHI Charge Pump Output vs. ISET
(CP = 01_12x; Temp = 25 _C)
–6000
3.00
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE(V)
–2000
2.75
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
2.50
–3000
–3000
2.25
–2000
ISET = 204 µA
2.00
–2000
+85 °C
–1000
ISET = 164 µA
1.75
ISET = 81 µA
–40 °C
+25 °C
0
1.50
0
1.25
1000
1.00
ISET = 81 µA
0.75
1000
0.50
2000
0.25
ISET = 164 µA
Icp (uA)
2000
Icp (uA)
ISET = 204 µA
–1000
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
3000
3000
Figure 18. PHP Charge Pump Output vs. Temperature
(CP = 10_3x; VDD = 3.0 V; ISET = 164 mA)
15
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
250
150
200
150
ISET = 81 µA
100
100
50
50
Icp (uA)
0
–50
ISET = 81 µA
–100
0
–40 °C
+25 °C
–50
+85 °C
–100
ISET = 164 µA
–150
–200
COMPLIANCE VOLTAGE (V)
Figure 20. PHP Charge Pump Output vs. Temperature
(CP = 11_1x; VDD = 3.0 V; ISET = 164 mA)
1500
1500
ISET = 204 µA
500
Icp (uA)
ISET = 81 µA
0
ISET = 81 µA
+85 °C
–500
ISET = 164 µA
–1000
–40 °C
+25 °C
0
–1000
ISET = 204 µA
–1500
3.00
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02339
SR02340
Figure 21. PHP–SU Charge Pump Output vs. ISET
(CP = 01_5x; VDD = 3.0 V; Temp = 25 _C)
Figure 22. PHP–SU Charge Pump Output vs. Temperature
(CP = 01_5x; VDD = 3.0 V; ISET = 164 mA)
4000
4000
3000
ISET = 204 µA
3000
2000
ISET = 164 µA
2000
1000
ISET = 81 µA
1000
Icp (uA)
0
0
–1000
ISET = 81 µA
–2000
ISET = 164 µA
–2000
–3000
ISET = 204 µA
–3000
–1000
–4000
ÎÎ
Î
ÎÎ
Î
Î
Î
Î
Î
Î
ÎÎ
Î
Î
Î
Î
ÎÎ
ÎÎ ÎÎ
Î
Î
ÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
–40 °C
+25 °C
+85 °C
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
SR02341
SR02342
Figure 23. PHP–SU Charge Pump Output vs. ISET
(CP = 00_15x; VDD = 3.0 V; Temp = 25 _C)
2001 Aug 21
0.50
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
–4000
0.25
Icp (uA)
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
–1500
0.25
Icp (uA)
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ
1000
ISET = 164 µA
–500
3.00
SR02338
Figure 19. PHP Charge Pump Output vs. ISET
(CP = 11_1x; VDD = 3.0 V; Temp = 25 _C)
500
2.75
COMPLIANCE VOLTAGE (V)
SR02337
1000
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
–250
0.75
0.50
0.00
0.25
ISET = 204 µA
–250
0.75
–200
0.50
–150
0.25
Icp (uA)
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
Î
ÎÎ
Î
Î
ÎÎ
Î
ÎÎ
ÎÎÎ
ÎÎ
Î
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ
Î
ÎÎ Î
Î
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎ
250
ISET = 204 µA
ISET = 164 µA
200
Figure 24. PHP–SU Charge Pump Output vs. Temperature
(CP = 00_15x; VDD = 3.0 V; ISET = 164 mA)
16
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
150
–100
Î
Î
Î
Î
Î
Î
Î
ÎÎ
Î
Î
Î
Î
Î
ÎÎ
Î
ÎÎ ÎÎ
Î
Î
Î
ÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ISET = 204 µA
100
100
ISET = 164 µA
50
50
Icp (uA)
0
ISET = 81 µA
–50
COMPLIANCE VOLTAGE (V)
SR02344
Figure 25. PHA Charge Pump Output vs. ISET
(CP = 11_0.5x; Temp = 25 _C)
Figure 26. PHA Charge Pump Output vs. Temperature
(CP = 11_0.5x; VDD = 3.0 V; ISET = 164 mA)
400
Î
Î
Î
ÎÎ
Î
Î
Î
Î
Î
Î
Î
Î
Î
ÎÎ
Î
Î
Î
ÎÎ ÎÎ
Î
Î
Î
ÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎ
400
ISET = 204 µA
300
300
200
ISET = 164 µA
200
100
ISET = 81 µA
100
–40 °C
+25 °C
0
+85 °C
Icp (uA)
0
–100
ISET = 81 µA
–200
ISET = 164 µA
–300
–100
–200
–300
ISET = 204 µA
Figure 28. PHA Charge Pump Output vs. Temperature
(CP = 10_1.5x; VDD = 3.0 V; ISET = 164 mA)
MINIMUM SIGNAL INPUT LEVEL (dBm)
2.6V
3.0V
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
3.6V
INPUT FREQUENCY (MHz)
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
–51
–40 °C
+25 °C
+85 °C
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
Figure 27. PHA Charge Pump Output vs. ISET
(CP = 10_1.5x; VDD = 3.0 V; Temp = 25 _C)
INPUT FREQUENCY (MHz)
SR02347
Figure 29. Main Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25 _C; ISET = 164 µA; NF = 0; MOD = 8; N = 853)
2001 Aug 21
3.00
SR02345
SR02346
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
–51
2.75
COMPLIANCE VOLTAGE (V)
COMPLIANCE VOLTAGE (V)
0
–3
–6
–9
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.00
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.50
–400
–400
0.25
Icp (uA)
3.00
COMPLIANCE VOLTAGE (V)
SR02343
MINIMUM SIGNAL INPUT LEVEL (dBm)
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
–150
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
–150
0.25
–100
ISET = 204 µA
0.00
+85 °C
–50
ISET = 164 µA
–100
–40 °C
+25 °C
0
0.00
Icp (uA)
ISET = 81 µA
SR02348
Figure 30. Main Divider Input Sensitivity vs.
Frequency and Temperature
(ISET = 164 µA; NF = 0; MOD = 8; N = 853; VDD = 3.0 V)
17
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0
–3
MIMINUM SIGNAL INPUT LEVEL (dBm)
0
–3
–9
–12
2.6V
3.0V
3.6V
–15
–18
–21
–24
–27
–30
–33
–36
–39
–6
–40 °C
+25 °C
+85 °C
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
0
–6
3.0V
–9
3.6V
–12
–15
–18
–21
–24
–27
–30
0
5
10
15
20
25 30
35
40 45
50
55
60 65
70
TOTAL CURRENT (mA)
8.50
8.00
7.50
7.00
–40 °C
+25 °C
+85 °C
6.50
6.00
3.2
3.4
SUPPLY VOLTAGE (V)
3.6
3.8
SR02353
Figure 35. Total Supply Current vs. Temperature
(ISET = 164 µA)
2001 Aug 21
900
950
+85 °C
–12
–15
–18
–21
–24
–27
–30
5
10
15
20
25
30
35
40
45
50
55
60
65
Figure 34. Reference Divider Input Sensitivity vs.
Frequency and Temperature
(ISET = 164 µA; Divider Ratio = 682; VDD = 3.0 V)
9.00
3.0
+25 °C
–9
70
SR02352
Figure 33. Reference Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25 _C; ISET = 164 µA; Divider Ratio = 682)
2.8
–40 °C
–6
FREQUENCY (MHz)
SR02351
2.6
0
–3
0
FREQUENCY (MHz)
2.4
SR02350
Figure 32. Auxiliary Divider Input Sensitivity vs.
Frequency and Temperature
(ISET = 164 µA; Divider Ratio = 213; VDD = 3.0 V)
MINIMUM SIGNAL INPUT LEVEL (dBm)
MINIMUM SIGNAL INPUT LEVEL (dBm)
Figure 31. Auxiliary Divider Input Sensitivity vs.
Frequency and Supply Voltage
(Temp = 25 _C; ISET = 164 µA; Divider Ratio = 213)
2.6V
700
750
800
850
FREQUENCY (MHz)
SR02349
–3
500
550
600
650
0
50
FREQUENCY (MHz)
300
350
400
450
–42
750
800
850
900
950
250
300
350
400
450
500
550
600
650
700
0
50
100
150
200
–42
100
150
200
250
MINIMUM SIGNAL INPUT LEVEL (dBm)
–6
18
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
2001 Aug 21
19
SA8027
SOT360-1
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
HBCC24: plastic, heatsink bottom chip carrier; 24 terminals; body 4 x 4 x 0.65 mm
2001 Aug 21
20
SA8027
SOT564-1
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
NOTES
2001 Aug 21
21
SA8027
Philips Semiconductors
Product data
2.5 GHz low voltage, low power
RF fractional-N/IF integer frequency synthesizer
SA8027
Data sheet status
Data sheet status [1]
Product
status [2]
Definitions
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Koninklijke Philips Electronics N.V. 2001
All rights reserved. Printed in U.S.A.
Contact information
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 09-01
For sales offices addresses send e-mail to:
[email protected].
Document order number:
2001 Aug 21
22
9397 750 08745