CXD2044Q Digital Comb Filter (NTSC/PAL/PAL-M/PAL-N) For the availability of this product, please contact the sales office. Description The CXD2044Q is an adaptive intra-field comb filter compatible with NTSC, PAL, PAL-M and PAL-N systems, and can provide high-precision Y/C separation with a single chip. Features • Intra-field Y/C separation by adaptive processing • 8-bit A/D converter (1-channel) • 8-bit D/A converter (2-channel) • Four 1H delay lines • Clock 4fsc Recommended Operating Conditions 5.0 ± 0.25 • Supply voltage DVDD AAVD 5.0 ± 0.25 ADVD 5.0 ± 0.25 YVDD 5.0 ± 0.25 CVDD 5.0 ± 0.25 Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage DVDD VSS – 0.5 to +7.0 V AAVD VSS – 0.5 to +7.0 V ADVD VSS – 0.5 to +7.0 V YVDD VSS – 0.5 to +7.0 V CVDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Storage temperature Tstg –55 to +150 °C • Analog input ADIN • Operating temperature Topr A/D NTSC: 1H PAL: 2H 1.8 –20 to +75 V V V V V Vp-p °C Applications Y/C separation for color TVs and VCRs Structure Silicon gate CMOS IC Block Diagram Analog Vin 80 pin QFP (Plastic) NTSC: 1H PAL: 2H DL Digital Vin D/A 8 8 A-Yout D-Yout Adaptive filter operation D/A Logic operation 8 A-Cout D-Cout Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95418-ST CXD2044Q CVRF CIRF CVss Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 DVss DVDD TEST CONT XYOE C8 C7 C6 C5 C4 C3 C2 C1 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 TEST 65 40 CVG TEST 66 39 ACO XCOE 67 38 XACO APCN 68 37 CVDD RATI 69 36 VB NTPL 70 35 YVss YOT 71 DVss 34 YIRF 72 33 YVRF DVDD 73 32 YVG DTR 74 31 AYO TEST 75 30 XAYO PMN 76 29 YVDD TEST 77 28 ADVD TEST 78 27 RT BPF 79 26 AAVD TEST 80 AAVS RB ADCO GR VI1 CRV VI2 ICP VI3 ADVS VI4 XCPON VI5 CLPI 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ADCK 8 MCK 7 CLKO 6 DVDD 5 DVss 4 INSL 3 OCLK 2 VI6 VI8 1 VI7 25 ADIN Pin Description Pin No. Symbol I/O Description 1 VI8 I Digital input (MSB). Connect to DVDD or DVss when not in use. 2 VI7 I Digital input. Connect to DVDD or DVss when not in use. 3 VI6 I Digital input. Connect to DVDD or DVss when not in use. 4 VI5 I Digital input. Connect to DVDD or DVss when not in use. 5 VI4 I Digital input. Connect to DVDD or DVss when not in use. 6 VI3 I Digital input. Connect to DVDD or DVss when not in use. 7 VI2 I Digital input. Connect to DVDD or DVss when not in use. 8 VI1 I Digital input (LSB). Connect to DVDD or DVss when not in use. 9 ADCO I A/D converter output through mode. High: Video signals taken into the A/D converter (input pin: ADIN) are output without change from the Y output pins as 8-bit digital data with a 3.5 clock delay. Low: Standard mode 10 INSL I Input switching. Switches the input data fed to the comb filter. High: Digital input Low: Analog input 11 OCLK I Clock amplifier input. Input 0.8Vp-p or more, eliminating the DC components with a capacitor. –2– CXD2044Q Pin No. Symbol I/O 12 DVSS — Digital ground. 13 DVDD — Digital power supply. (5V) 14 CLKO O Clock amplifier output. 15 MCK I Master clock input. Input the 4fsc clock locked to the color burst. Normally, connect the clock amplifier output (CLKO: Pin 14). 16 ADCK I Clock input for the A/D converter. Input the same clock as the master clock (MCK: Pin 15). Normally, connect the clock amplifier output (CLKO: Pin 14). 17 CLPI I Clamp pulse input for the A/D converter. Clamps the signal voltage during the low period of the clamp pulse signal. When the clamp function is off, connect to the digital power supply (DVDD). 18 XCPON I Clamp setting for the A/D converter. High: Clamp function is set to off, and the normal A/D converter function is only enabled. Low: Clamp function is enabled. 19 ADVS 20 ICP I Clamp control voltage integral pin. Connect a capacitor of approximately 0.01µF. When not using clamp, connect to the analog ground (AAVS). 21 CRV I Clamp reference voltage input. Operates to make the analog input voltage equal to the clamp reference voltage during the clamp period. When not using clamp, connect to the analog ground (AAVS). 22 RB O Reference voltage (bottom): 0.5V (typ.) 23 GR — Guard ring. Connect to the analog ground (AAVS). 24 AAVS — Analog ground for the A/D converter. 25 ADIN I 26 AAVD — Analog power supply for the A/D converter. (5V) 27 RT O Reference voltage (top): 2.6V (typ.) 28 ADVD — Digital power supply for the A/D converter. (5V) 29 YVDD — Analog power supply for the Y D/A converter. (5V) 30 XAYO O AYO inverted current output. Connect to the analog ground (YVss). 31 AYO O Analog luminance signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. 32 YVG O Connect a capacitor of approximately 0.1µF. 33 YVRF I Sets the full-scale value of the analog luminance output signal. 34 YIRF O Connect a resistor of “16R” (16 times the output resistor “R” of the AYO pin). 35 YVss — Analog ground for the Y D/A converter. 36 VB O Connect a capacitor of approximately 0.1µF. 37 CVDD — Analog power supply for the C D/A converter. (5V) 38 XACO O ACO inverted current output. Connect to the analog ground (CVss). — Description Digital ground for the A/D converter. Comb filter analog input (A/D converter input). –3– CXD2044Q Pin No. Symbol I/O Description 39 ACO O Analog chroma signal output. Output can be obtained by connecting a resistor between this pin and the analog ground. 40 CVG O Connect a capacitor of approximately 0.1µF. 41 CVRF I Sets the full-scale value of the analog chroma output signal. 42 CIRF O Connect a resistor of “16R” (16 times the output resistor “R” of the ACO pin). 43 CVss — Analog ground for the C D/A converter. 44 Y8 O Digital luminance signal output (MSB). 45 Y7 O Digital luminance signal output. 46 Y6 O Digital luminance signal output. 47 Y5 O Digital luminance signal output. 48 Y4 O Digital luminance signal output. 49 Y3 O Digital luminance signal output. 50 Y2 O Digital luminance signal output. 51 Y1 O Digital luminance signal output (LSB). 52 DVss — Digital ground. 53 DVDD — Digital power supply. (5V) 54 TEST I Test. Normally open or fix to “Low”. 55 CONT I Normally open or fix to “High”. 56 XYOE I Digital luminance signal output control. High: High impedance Low: Standard output However, during PAL-M/N mode (Pins 70 and 76 are both “High”), the digital chroma signal output is also controlled simultaneously. See Table 1. 57 C8 O Digital chroma signal output (MSB). 58 C7 O Digital chroma signal output. 59 C6 O Digital chroma signal output. 60 C5 O Digital chroma signal output. 61 C4 O Digital chroma signal output. 62 C3 O Digital chroma signal output. 63 C2 O Digital chroma signal output. 64 C1 O Digital chroma signal output (LSB). 65 TEST I Test. Normally open or fix to “Low”. 66 TEST I Test. Normally open or fix to “Low”. 67 XCOE I Digital chroma signal output control. See Table 1. High: High impedance Low: Standard output I Aperture compensation circuit setting. High: Compensates for the aperture-induced frequency response characteristics degradation. Even in through mode (YOT: H), aperture compensation is performed for the Y output. Low: Standard mode 68 APCN –4– CXD2044Q Pin No. Symbol I/O Description 69 RATI I Ratio setting. High: PAL/PAL-M/PAL-N: When DTR: H, compulsively fixed to “Low” internally. Low: NTSC 70 NTPL I NTSC/PAL/PAL-M/PAL-N mode setting. See Table 1. High: PAL/PAL-M/PAL-N Low: NTSC Y output through mode. High: Outputs the input composite video signal from the Y output. At this time, there is 1H + 15 clock delay from the digital input for NTSC, and 2H + 15 clock delay from the digital input for PAL/PAL-M/PAL-N. For C output, the Y/C separated chroma signal is output. Low: Y/C separation mode 71 YOT I 72 DVss — Digital ground. 73 DVDD — Digital power supply. (5V) 74 DTR I PAL/PAL-M/PAL-N: High: Dot interference reduction mode Low: Before dot interference reduction NTSC: Fix to “Low”. 75 TEST I Test. Normally fix to “Low”. 76 PMN I NTSC/PAL/PAL-M/PAL-N mode selection. See Table 1. 77 TEST I Test. Normally fix to “Low”. 78 TEST I Test. Normally fix to “Low”. 79 BPF I Y/C separation processing mode setting. High: Fixed to BPF separation mode Low: Adaptive processing mode 80 TEST I Test. Normally fix to “Low”. Table 1. NTSC/PAL/PAL-M/PAL-N mode selection (Numbers in parentheses indicate the Pin No.) Mode NTPL (70) PMN (76) XCOE (67)∗ NTSC 0 0 0 PAL 1 0 0 PAL-M 1 1 0 PAL-N 1 1 1 ∗ Digital Y output enable and digital C output enable are simultaneously controlled by XYOE (Pin 56) during PAL-M/PAL-N mode. –5– CXD2044Q Electrical Characteristics (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) DC Characteristics Item Symbol Measurement conditions Min. Typ. Max. Unit Applicable pins — 4.75 5.0 5.25 V ∗1 VDD AAVD Supply voltage ADVD YVDD CVDD Operating temperature Topr — –20 +75 °C Input/output voltage VI, VO — Vss VDD V ∗2 V ∗3 ns ∗1 Input voltage Input rise/fall time VIH VIL tr, tf VOH Output voltage VOL Logical Vth Input voltage 0.7VDD CMOS level input 0.3VDD 0 — IOH = –2mA 500 ∗4 VDD–0.8 IOH = –4mA V IOL = 4mA 0.4 VDD/2 VIH V 0.7VDD — 0.3VDD VIL 0.8 VIN fmax = 50MHz sine wave Feedback resistance value RFB VIN = Vss or VDD 250k IIL, IIH VIN = VSS or VDD –10 IIH VIH = VDD 40 100 240 IIL VIL = VSS –40 –100 –240 3.0 9.0 18.0 Clock amplifier output delay ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 ∗9 — — All pins All pins other than ∗6 All input pins other than ∗6 All output pins other than ∗5 CLKO (Pin 14) OCLK (Pin 11) All pins other than ∗8 and ∗9 Pins 54, 65, 66 and 75 to 80 Pin 55 –6– V ∗6 Vp-p Input amplitude Input leak current ∗4 ∗5 IOL = 8mA LVth ∗5 1M 2.5M Ω ∗7 10 µA ∗8 ∗9 ns ∗5 CXD2044Q AC Characteristics Input Interface Timing Input Data Tsu Th 0.7VDD MCK Input Characteristics Input pin Pin No. VI8 to VI1 1 to 8 (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Min. Tsu Th 20.00 10.00 Unit ns Remarks Rising edge of MCK is used as a reference. Output Interface Timing 0.7VDD MCK Tpd Output Data Output Characteristics Output pin Pin No. Y8 to Y1 44 to 51 C8 to C1 57 to 64 (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Tpd (output load capacitance 20 [pF]) Max. 25.0 Min. 5.00 Max. 25.00 Min. 5.00 –7– Unit Remarks ns Rising edge of MCK is used as a reference. ns Rising edge of MCK is used as a reference. CXD2044Q Clock Frequency (VDD = 4.75 to 5.25V, VSS = 0V, Ta = –20 to +75°C) Input pin OCLK, MCK, ADCK Pin No. Symbol Min. 11, 15, 16 f — Typ. 4fsc∗1 Max. Unit — MHz ∗1 fsc = 3.58MHz (NTSC), 4.43MHz (PAL) (Ta = 25°C, f = 1MHz, VIN = VOUT = 0V) I/O Pin Capacitance Item Symbol Min. Typ. Max. Input pin capacitance CIN — — 9 Output pin capacitance COUT — — 11 Unit pF (VDD = 5V, Ta = 25°C, f = 10MHz) Internal 8-bit ADC Characteristics Item Symbol Conditions Min. Typ. Max. Unit Resolution n — 8 — bit Max. conversion speed fmax 18 — — MSPS Analog input bandwidth BW — 18 — MHz VRB 0.48 0.52 0.56 V VRT–VRB 1.96 2.08 2.22 V Self bias –3dB Output data delay tpd — — 45 ns Differential linearity error ED –1.0 — +1.0 LSB Integral linearity error EL –3.0 — +3.0 LSB Clamp offset voltage EOC VREF = VRB –20 0 +20 mV VREF = VRT –30 –10 +10 mV (VDD = 5V, VRF = 2V, RIRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz) Internal 8-bit DAC Characteristics Item Symbol Conditions Min. Typ. Max. Unit Resolution n — 8 — bit Max. conversion speed fmax 18 — — MSPS Differential linearity error ED –0.8 — +0.8 LSB Integral linearity error EL –2.0 — +2.0 LSB Output full-scale voltage VFS 1.805 1.90 1.995 V Output full-scale current IFS — 9.5 15 mA Output offset voltage VOS — — 1.0 mV Glitch energy GE — 30 — pV-s ∗2 ∗2 R = 75Ω, 1Vp-p output –8– CXD2044Q Application Circuit for the A/D Converter Block (1) When inputting the clamp pulse directly 0.01µ ADC input 27 RT Clamp pulse CLPI 17 75 25 ADIN XCLP 18 22 RB ADCK 16 10p 10µ 0.01µ ADC clock 21 CRV 20k 20 ICP 0.01µ 23 GR 26 AAVD 0.1µ ADVD 28 24 AAVS ADVS 19 0.1µ (2) When not using the internal clamp circuit 0.01µ ADC input CLPI 17 27 RT 75 25 ADIN XCLP 18 22 RB ADCK 16 10p 0.01µ ADC clock 21 CRV 20 ICP 23 GR 26 AAVD 0.1µ ADVD 28 24 AAVS ADVS 19 –9– 0.1µ CXD2044Q Application Circuit for the D/A Converter Block AYO 31 Y OUTPUT 200 (R) 0.1µ 29 YVDD XAYO 30 0.1µ 35 YVG 32 YVSS YVRF 33 15 CLOCK MCK 1K YIRF 34 3.3k (R') DVDD VB 36 0.1µ DVSS C OUTPUT ACO 39 200 (R) XACO 38 0.1µ 0.1µ 37 CVDD CVG 40 43 CVSS CVRF 41 1K CIRF 42 3.3k (R') • Method of selecting the output resistor The CXD2044Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage VFS = 0.5 to 2.0 [V], output full-scale current IFS = 0 to 15 [mA]. Calculate the output resistance value using the relationship VFS = IFS × R. In addition, connect a resistor of 16 times the output resistor to the reference current pin (YIRF, CIRF). In case this results in a non-existent value, use a resistance value as close to the calculated value as possible. Note that, at this time, VFS = VRF × 16R/R' (VRF: Pin voltage of YVRF and CVRF). Here, R is the resistor connected to AYO/ACO, and R' is the resistor connected to YIRF/CIRF. Power consumption can be reduced by using higher resistance values for the R, but the glitch energy and data settling time increase contrastingly. Set the optimum values according to the system applications. • VDD, Vss Separate the analog and digital systems around the device to reduce the effects of noise. YVDD and CVDD are by-passed to YVss and CVss, respectively, as close to each other as possible through ceramic capacitors of approximately 0.1µF. – 10 – Clock input 0.1µ DVss CONT TEST XYOE C8 C6 C3 C4 C2 3.3k DVss DVDD INSL OCLK VI1 ADCO VI6 VI5 80 TEST 79 BPF 78 TEST 77 TEST 76 PMN 75 TEST 3 4 8 1000p 7 6 5 9 C1 to 8: High Impedance C1 to 8: Standard output PAL-N PAL-M Digital ground Digital ground 0.01µ Digital power supply (5V) 0.1µ 20k 1k 10p 75 0.1µ 3.3k 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 10µ 0.01µ 200 1k 200 : Digital ground : Digital power supply (5V) : Analog ground : Analog power supply (5V) VIDEO IN LPF LPF Y OUT C OUT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 0.01µ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PMN (pin76) Digital power supply (5V) 2 1 ADIN 25 AAVD 26 RT 27 ADVD 28 YVDD 29 XAYO 30 AYO 31 MCK 74 DTR CLKO YVG 32 CLPI YVRF 33 ADCK 73 DVDD ADVS YIRF 34 XCPON 72 DVss CRV CVG 40 YVss 35 DVDD 70 NTPL ICP 71 YOT XCOE (pin67) Clamp pulse input (∗1) Normal BPF Normal NTSC Through C1 VI7 VI8 PAL Y2 VB 36 Y1 69 RATI C5 VI3 OFF Y4 CVDD 37 Y3 XACO 38 Y6 68 APCN Y5 67 XCOE Y8 ACO 39 C7 VI4 – 11 – VI2 Aperture ON Y7 66 TEST RB 65 TEST CVss 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 0.1µ CVRF AAVS (∗1) Y1 to 8: Standard output Y1 to 8: High impedance CIRF GR Application Circuit CXD2044Q CXD2044Q Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g – 12 – 0.8 ± 0.2 80