MC10EP57
4:1 Differential Multiplexer
The MC10EP57 is a fully differential 4:1 multiplexer. By leaving
the SEL1 line open (pulled LOW via the input pulldown resistors) the
device can also be used as a differential 2:1 multiplexer with SEL0
input selecting between D0 and D1. The fully differential architecture
of the EP57 makes it ideal for use in low skew applications such as
clock distribution.
The SEL1 is the most significant select line. The binary number
applied to the select inputs will select the same numbered data input
(i.e., 00 selects D0).
Multiple VBB outputs are provided for single-ended or AC coupled
interfaces. In these scenarios, the VBB output should be connected to
the data bar inputs and bypassed via a 0.01µF capacitor to ground.
Note that the VBB output can source/sink up to 0.5mA of current
without upsetting the voltage level. All VCC and VEE pins must be
externally connected to power supply to guarantee proper operation
•
•
•
•
•
•
•
•
•
•
•
•
•
•
350ps Typical Propagation Delays
Typical Frequency 3.0GHz
20–Lead TSSOP Package
PECL mode: 3.0V to 5.5V VCC with VEE = 0V
ECL mode: 0V VCC with VEE = –3.0V to –5.5V
Internal Input Resistors: Pulldown on D, D
Q Output will default LOW with inputs open or at VEE
ESD Protection: >2KV HBM, >100V MM
VBB Outputs
New Differential Input Common Mode Range
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.
For Additional Information, See Application Note AND8003/D
Useful as Either 4:1 or 2:1 Multiplexer
Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
Transistor Count = 584 devices
VCC
20
SEL1 SEL0
19
18
VCC
Q
Q
17
16
15
VCC VBB1 VBB2
14
13
12
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20
1
TSSOP–20
DT SUFFIX
CASE 948E
MARKING DIAGRAM
A
L
Y
W
MC10
EP57
ALYW
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
PIN DESCRIPTION
PIN
FUNCTION
D0–3, D0–3
ECL Diff. Data Inputs
SEL0, 1
ECL Mux Select Inputs
VBB1, VBB2
ECL Reference Output Voltage
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative, 0 Supply
VEE
FUNCTION TABLE
11
4:1
SEL1
SEL0
DATA OUT
L
L
H
H
L
H
L
H
D0, D0
D1, D1
D2, D2
D3, D3
ORDERING INFORMATION
Device
Package
Shipping
1
2
3
4
5
6
7
8
9
10
MC10EP57DT
TSSOP
75 Units/Rail
VCC
D0
D0
D1
D1
D2
D2
D3
D3
VEE
MC10EP57DTR2
TSSOP
2500 Tape & Reel
Figure 1. 20–Lead TSSOP (Top View) and Logic Diagram
Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 2
1
Publication Order Number:
MC10EP57/D
MC10EP57
MAXIMUM RATINGS*
Value
Unit
VEE
Symbol
Power Supply (VCC = 0V)
Parameter
–6.0 to 0
VDC
VCC
Power Supply (VEE = 0V)
6.0 to 0
VDC
VI
Input Voltage (VCC = 0V, VI not more negative than VEE)
–6.0 to 0
VDC
VI
Input Voltage (VEE = 0V, VI not more positive than VCC)
6.0 to 0
VDC
Iout
Output Current
50
100
mA
IBB
VBB Sink/Source Current{
± 0.5
mA
TA
Operating Temperature Range
–40 to +85
°C
Tstg
Storage Temperature
θJA
Thermal Resistance (Junction–to–Ambient)
θJC
Thermal Resistance (Junction–to–Case)
Tsol
Solder Temperature (<2 to 3 Seconds: 245°C desired)
Continuous
Surge
–65 to +150
°C
140
100
°C/W
23 to 41 ±5%
°C/W
265
°C
Still Air
500lfpm
* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = –5.5V to –3.0V) (Note 4.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 1.)
40
52
65
40
52
65
40
52
65
mA
VOH
Output HIGH Voltage
(Note 2.)
–1135
–1060
–885
–1070
–945
–820
–1010
–885
–760
mV
VOL
Output LOW Voltage
(Note 2.)
–1995
–1810
–1685
–1995
–1745
–1620
–1995
–1685
–1560
mV
VIH
Input HIGH Voltage
Single Ended
–1210
–885
–1145
–820
–1085
–760
mV
VIL
Input LOW Voltage
Single Ended
–1935
–1610
–1870
–1545
–1810
–1485
mV
VBB
Output Voltage Reference
–1550
–1350
–1500
–1300
–1450
–1250
mV
0.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 3.)
IIH
Input HIGH Current
IIL
Input LOW Current
–1450
VEE+2.0
0.0
–1400
VEE+2.0
150
0.0
–1350
VEE+2.0
150
µA
SEL, D
D
0.5
–150
0.5
–150
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating.
2. All loading with 50 ohms to VCC–2.0 volts.
3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
4. Input and output parameters vary 1:1 with VCC.
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MC10EP57
DC CHARACTERISTICS, LVPECL (VCC = 3.3V ± 0.3V, VEE = 0V) (Note 8.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 5.)
40
52
65
40
52
65
40
52
65
mA
VOH
Output HIGH Voltage
(Note 6.)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage
(Note 6.)
1305
1490
1615
1305
1555
1680
1305
1615
1740
mV
VIH
Input HIGH Voltage
Single Ended
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage
Single Ended
1365
1690
1430
1755
1490
1815
mV
VBB
Output Voltage Reference
1750
1950
1800
2000
1850
2050
mV
3.3
2.0
3.3
2.0
3.3
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 7.)
IIH
Input HIGH Current
IIL
Input LOW Current
1850
2.0
1900
150
1950
150
µA
SEL, D
D
0.5
–150
0.5
–150
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
5. VCC = 3.3V, VEE = 0V, all other pins floating.
6. All loading with 50 ohms to VCC–2.0 volts.
7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
8. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, PECL (VCC = 5.0V ± 0.5V, VEE = 0V) (Note 12.)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
(Note 9.)
40
52
65
40
52
65
40
52
65
mA
VOH
Output HIGH Voltage
(Note 10.)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage
(Note 10.)
3005
3190
3315
3005
3255
3380
3005
3315
3440
mV
VIH
Input HIGH Voltage
Single Ended
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage
Single Ended
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3450
3650
3500
3700
3550
3750
mV
5.0
2.0
5.0
2.0
5.0
V
150
µA
VIHCMR Input HIGH Voltage Common Mode
Range (Note 11.)
IIH
Input HIGH Current
IIL
Input LOW Current
3550
2.0
150
3600
150
3650
µA
SEL, D
D
0.5
–150
0.5
–150
0.5
–150
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
9. VCC = 5.0V, VEE = 0V, all other pins floating.
10. All loading with 50 ohms to VCC–2.0 volts.
11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
12. Input and output parameters vary 1:1 with VCC.
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MC10EP57
AC CHARACTERISTICS (VCC = 0V; VEE = –3.0V to –5.5V) or (VCC = 3.0V to 5.5V; VEE = 0V)
–40°C
Symbol
Characteristic
Min
fmax
Maximum Toggle
Frequency (Note 13.)
tPLH,
tPHL
Propagation Delay to
Output Differential
D–>Q, Q
COM_SEL, SEL–>Q, Q
tSKEW
Within–Device Skew (Note 14.)
Duty Cycle Skew (Note 15.)
tJITTER
Cycle–to–Cycle Jitter
VPP
Input Voltage Swing (Diff.)
tr, tf
Output Rise/Fall Times
(20% – 80%)
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
3.0
GHz
ps
250
300
350
400
450
500
275
320
375
420
100
475
520
320
320
420
450
100
TBD
Q, Q
Unit
520
575
100
TBD
TBD
ps
ps
150
800
1200
150
800
1200
150
800
1200
mV
70
120
170
70
140
200
70
150
220
ps
13. Fmax guaranteed for functionality only.
14. Within–Device Skew is defined as identical transitions on similar paths through a device.
15. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP57
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X
0.15 (0.006) T U
K REF
0.10 (0.004)
S
M
T U
S
V
S
K
K1
2X
L/2
20
11
B
L
J J1
–U–
PIN 1
IDENT
ÍÍÍ
ÍÍÍ
ÍÍÍ
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
M
A
–V–
N
F
DETAIL E
–W–
C
D
0.100 (0.004)
–T– SEATING
G
H
DETAIL E
PLANE
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5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC10EP57
Notes
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MC10EP57
Notes
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MC10EP57
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MC10EP57/D