PLL52C63-01 Pen tium/SDRAM Clock Gen er ator with In te grated Buff ers PIN INFORMATION FEATURES n Generates all clock frequencies for Pentium (II), AMD and Cyrix system requiring multiple CPU clocks. n Supports up to16 Synchronous CPU clocks (4 CPU and 12 SDRAM) and 7 Synchronous PCI BUS clocks. n Two 14.318Mhz reference clocks and one 2.5V IOAPIC n One 24Mhz floppy clock and one 48Mhz USB clock. n Power management control pins to stop CPU, SDRAM or PCI BUS clocks. n Supports 2-wire I2C serial bus interface. n 50% duty cycle with low jitter n Mixed voltage support from 3.0 to 5V or (VDDq2=2.5V) n Available in 300mil 48 pin SSOP. FREQUENCY SELECTION (MHz) F2 F1 F0 PCLK/SDRAM BCLK 0 0 0 50 25 0 0 1 100 50 0 1 0 83.3 41.6 0 1 1 68.5 34.2 1 0 0 55 27.5 1 0 1 75 37.5 MODE PIN15 PIN46 1 1 0 60 30 1 (OUT PUT) BCLK5 REF1 1 1 1 66.6 33.3 0 (IN PUT) PCISTP CPUSTP Note: F2,F1,F0 and MODE are se lecta ble only dur ing power- on. They are HIGH by de fault and LOW when 10K Ω Pull down is at tached. I/O MODE CONFIGURATION BLOCK DIAGRAM 45437 Warm Springs Blvd., Fre mont, Cali for nia 94539, TEL 510- 492- 0990 FAX 510- 492- 0991 9704.Rev.1C Page 1