1550 MHz to 2150 MHz Rx Mixer with Integrated Fractional-N PLL and VCO ADRF6602 FEATURES GENERAL DESCRIPTION Rx mixer with integrated fractional-N PLL RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz Input P1dB: 14.5 dBm Input IP3: 30 dBm IIP3 optimization via external pin SSB noise figure IP3SET pin open: 13.5 dB IP3SET pin at 3.3 V: 14 dB Voltage conversion gain: 6 dB Matched 200 Ω IF output impedance IF 3 dB bandwidth: 500 MHz Programmable via 3-wire SPI interface 40-lead, 6 mm × 6 mm LFCSP The ADRF6602 is a high dynamic range active mixer with integrated phase-locked loop (PLL) and voltage-controlled oscillator (VCO). The PLL/synthesizer uses a fractional-N PLL to generate an fLO input to the mixer. The reference input can be divided or multiplied and then applied to the PLL phase frequency detector (PFD). The PLL can support input reference frequencies from 12 MHz to 160 MHz. The PFD output controls a charge pump whose output drives an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2× fLO is applied to an LO divider, as well as to a programmable PLL divider. The programmable PLL divider is controlled by a Σ-Δ modulator (SDM). The modulus of the SDM can be programmed from 1 to 2047. APPLICATIONS The active mixer converts the single-ended 50 Ω RF input to a 200 Ω differential IF output. The IF output can operate up to 500 MHz. Cellular base stations The ADRF6602 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM VCC1 VCC2 VCC_LO VCC_MIX VCC_V2I VCC_LO 1 10 17 22 27 34 NC NC 32 33 ADRF6602 INTERNAL LO RANGE 1550MHz TO 2150MHz LODRV_EN 36 LON 37 BUFFER LOP 38 BUFFER PLL_EN 16 FRACTION MODULUS REG CLK 13 SPI INTERFACE LE 14 2:1 MUX INTEGER REG REF_IN 6 ÷2 ÷4 N COUNTER 21 TO 123 MUX TEMP SENSOR 7 2.5V LDO 9 DECL2P5 VCO LDO 40 DECLVCO VCO CORE PRESCALER ÷2 29 IP3SET CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA – PHASE + FREQUENCY DETECTOR MUXOUT 8 4 DECL3P3 26 RF IN THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 2 11 15 20 21 23 24 25 28 30 31 35 5 RSET GND 3 39 18 19 CP VTUNE IFP IFN 08545-001 DATA 12 DIV BY 4, 2, 1 3.3V LDO Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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ADRF6602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 13 Register 5—PLL Enable and LO Path Control (Default: 0x0000E5) .................................................................................... 14 Register 6—VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 14 RF Specifications .......................................................................... 3 Register 7—Mixer Bias Enable and External VCO Enable (Default: 0x000007).................................................................... 14 Synthesizer/PLL Specifications ................................................... 4 Theory of Operation ...................................................................... 15 Logic Input and Power Specifications ....................................... 5 Programming the ADRF6602................................................... 15 Timing Characteristics ................................................................ 5 Initialization Sequence .............................................................. 15 Absolute Maximum Ratings............................................................ 6 LO Selection Logic ..................................................................... 16 ESD Caution .................................................................................. 6 Applications Information .............................................................. 17 Pin Configuration and Function Descriptions ............................. 7 Basic Connections for Operation ............................................. 17 Typical Performance Characteristics ............................................. 9 Evaluation Board ............................................................................ 18 Register Structure ........................................................................... 11 Evaluation Board Control Software ......................................... 18 Register 0—Integer Divide Control (Default: 0x0001C0)..... 11 Schematics and Artwork ........................................................... 20 Register 1—Modulus Divide Control (Default: 0x003001) .. 11 Evaluation Board Configuration Options ............................... 22 Register 2—Fractional Divide Control (Default: 0x001802) .................................................................................... 12 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23 Register 3—Σ-Δ Modulator Dither Control (Default: 0x10000B) .................................................................................... 12 REVISION HISTORY 1/10—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADRF6602 SPECIFICATIONS RF SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 1. Parameter INTERNAL LO FREQUENCY RANGE RF INPUT FREQUENCY RANGE RF INPUT AT 1410 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 1760 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage RF INPUT AT 2010 MHz Input Return Loss Input P1dB Second-Order Intercept (IIP2) Third-Order Intercept (IIP3) Single-Side Band Noise Figure LO to IF Leakage IF OUTPUT Voltage Conversion Gain IF Bandwidth Output Common-Mode Voltage Gain Flatness Gain Variation Output Swing Output Return Loss LO INPUT/OUTPUT (LOP, LON) Frequency Range Output Level (LO as Output) Input Level (LO as Input) Input Impedance Test Conditions/Comments ±3 dB RF input range Min 1550 1000 Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Relative to 50 Ω (can be improved with external match) −5 dBm each tone (10 MHz spacing between tones) −5 dBm each tone (10 MHz spacing between tones) IP3SET = 3.3 V IP3SET = open At 1× LO frequency, 50 Ω termination at the RF port Differential 200 Ω load Small-signal 3 dB bandwidth External pull-up balun or inductors required Over frequency range, any 5 MHz/50 MHz Over full temperature range Differential 200 Ω load Relative to 200 Ω Externally applied 1× LO input, internal PLL disabled Typ Rev. 0 | Page 3 of 24 Unit MHz MHz −12 15 56.5 31.5 14 13.5 −47 dB dBm dBm dBm dB dB dBm −12 15 55 30.0 15 13.3 −47 dB dBm dBm dBm dB dB dBm −12 14.5 57 28.5 16 14.7 −46 dB dBm dBm dBm dB dB dBm 6 500 5 0.2/1.0 1.0 2 −12 dB MHz V dB dB V p-p dB 250 1× LO into a 50 Ω load, LO output buffer enabled Max 2150 3100 6000 −7 ±6 50 MHz dBm dBm Ω ADRF6602 SYNTHESIZER/PLL SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 153.6 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 2. Parameter SYNTHESIZER SPECIFICATIONS Frequency Range Figure of Merit Reference Spurs PHASE NOISE Integrated Phase Noise PFD Frequency REFERENCE CHARACTERISTICS REF_IN Input Frequency REF_IN Input Capacitance MUXOUT Output Level MUXOUT Duty Cycle CHARGE PUMP Pump Current Output Compliance Range Test Conditions/Comments Synthesizer specifications referenced to 1× LO Internally generated LO PREF_IN = 0 dBm fREF = 153.6 MHz fREF/4 fREF/2 fREF > fREF fLO = 1550 MHz to 2150 MHz, fPFD = 38.4 MHz 1 kHz to 10 kHz offset 100 kHz offset 500 kHz offset 1 MHz offset 5 MHz offset 10 MHz offset 20 MHz offset 1 kHz to 40 MHz integration bandwidth Min Typ Max Unit 2150 −222 MHz dBc/Hz −105 −105 −80 −85 dBc dBc dBc dBc −90 −103 −122 −130 −142 −148 −150 0.3 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms MHz 1550 20 40 REF_IN, MUXOUT pins 12 160 4 VOL (lock detect output selected) VOH (lock detect output selected) 0.25 2.7 50 Programmable to 250 μA, 500 μA, 750 μA, 1 mA 500 1 Rev. 0 | Page 4 of 24 2.8 MHz pF V V % μA V ADRF6602 LOGIC INPUT AND POWER SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25°C; fREF = 38.4 MHz; fPFD = 38.4 MHz; high-side LO injection; fIF = 140 MHz; IIP3 optimized using capacitor DAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 3. Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN POWER SUPPLIES Voltage Range Supply Current Test Conditions/Comments CLK, DATA, LE Min Typ 1.4 0 Max Unit 3.3 0.7 V V μA pF 5.25 V mA mA 0.1 5 VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins 4.75 PLL only External LO mode (internal PLL disabled, IP3SET pin = 3.3 V) Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V) Power-down mode 5 97 165 262 mA 30 mA TIMING CHARACTERISTICS VCC2 = 5 V ± 5%. Table 4. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Description LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Timing Diagram t4 t5 CLK t2 DATA DB23 (MSB) t3 DB22 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) t1 DB0 (LSB) (CONTROL BIT C1) t7 08545-002 t6 LE Figure 2. Timing Diagram Rev. 0 | Page 5 of 24 ADRF6602 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE IFP, IFN RFIN θJA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating −0.5 V to +5.5 V −0.3 V to +3.6 V −0.3 V to VCC + 0.3 V 18 dBm 35°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 6 of 24 ADRF6602 40 39 38 37 36 35 34 33 32 31 DECLVCO VTUNE LOP LON LODRV_EN GND VCC_LO NC NC GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADRF6602 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 GND IP3SET GND VCC_V2I RFIN GND GND GND VCC_MIX GND NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. 08545-003 GND DATA CLK LE GND PLL_EN VCC_LO IFP IFN GND 11 12 13 14 15 16 17 18 19 20 VCC1 1 DECL3P3 2 CP 3 GND 4 RSET 5 REF_IN 6 GND 7 MUXOUT 8 DECL2P5 9 VCC2 10 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic VCC1 2 3 4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35 5 DECL3P3 CP GND RSET Description Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Decoupling Node for 3.3 V LDO. Connect a 0.1 μF capacitor between this pin and ground. Charge Pump Output Pin. Connect to VTUNE through loop filter. Ground. Connect these pins to a low impedance ground plane. Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1 mA using Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 to 0 (internal reference current). In this mode, no external RSET is required. If Bit DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally adjusted according to the following equation: ⎛ 217.4 × I CP R SET = ⎜⎜ ⎝ I NOMINAL 6 8 REF_IN MUXOUT 9 10 DECL2P5 VCC2 12 13 DATA CLK 14 LE 16 PLL_EN 17, 34 VCC_LO 18, 19 22 IFP, IFN VCC_MIX 26 RFIN ⎞ ⎟ − 37.8 Ω ⎟ ⎠ Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect signal. The output is selected by programming the appropriate register. Decoupling Node for 2.5 V LDO. Connect a 0.1 μF capacitor between this pin and ground. Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits. Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Load Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the eight registers. The relevant latch is selected by the three control bits of the 24-bit word. PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be used to switch modes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Mixer IF Outputs. These outputs should be pulled to VCC with RF chokes. Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. RF Input (Single-Ended, 50 Ω). Rev. 0 | Page 7 of 24 ADRF6602 Pin No. 27 Mnemonic VCC_V2I 29 32, 33 36 IP3SET NC LODRV_EN 37, 38 LON, LOP 39 VTUNE 40 EP DECLVCO EPAD Description Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the pin. Connect a resistor from this pin to a +5 V supply to adjust IIP3. Normally leave open. No Connection. LO Driver Enable. Together with Pin 16 (PLL_EN), this digital input pin determines whether the LOP and LON pins operate as inputs or outputs. LOP and LON become inputs if the PLL_EN pin is low or if the PLL_EN pin is set high with the PLEN bit (DB6 in Register 5) set to 0. LOP and LON become outputs if either the LODRV_EN pin or the LDRV bit (DB3 in Register 5) is set to 1 while the PLL_EN pin is set high. External LO drive frequency must be 1× LO. This pin should not be left floating. Local Oscillator Input/Output. The internally generated 1× LO is available on these pins. When internal LO generation is disabled, an external 1× LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.5 V to 2.5 V. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Rev. 0 | Page 8 of 24 ADRF6602 TYPICAL PERFORMANCE CHARACTERISTICS CDAC = 0x0, IP3SET = 3.3 V, internally generated LO, RFIN = −10 dBm, fIF = 140 MHz, unless otherwise noted. 45 5 4 40 3 35 +85°C –40°C +25°C 1 INPUT IP3 (dBm) GAIN (dB) 2 +85°C 0 –1 30 –40°C +25°C 25 20 –2 15 –3 1650 1750 1850 1950 2050 2150 LO FREQUENCY (MHz) 5 1550 08545-014 –5 1550 1650 1750 1850 1950 2050 2150 LO FREQUENCY (MHz) Figure 4. Gain vs. LO Frequency 08545-017 10 –4 Figure 7. IIP3 vs. LO Frequency, RFIN = −5 dBm 90 20 18 +25°C 80 70 INPUT P1dB (dBm) INPUT IP2 (dBm) 16 +85°C 60 +25°C –40°C 50 +85°C 14 –40°C 12 10 8 6 4 40 1650 1750 1850 1950 2050 2150 LO FREQUENCY (MHz) 0 1550 08545-015 30 1550 1850 1950 2050 2150 Figure 8. IP1dB vs. LO Frequency 0 19 –5 LO FEEDTHROUGH AMPLITUDE (dBm) 20 18 17 16 15 +85°C +25°C 13 –40°C 12 11 –10 –15 –20 –25 –30 –35 –40 –45 –40°C +85°C –50 –55 1650 1750 1850 1950 2050 LO FREQUENCY (MHz) Figure 6. Noise Figure vs. LO Frequency 2150 –60 1550 1650 1750 1850 1950 LO FREQUENCY (MHz) 2050 2150 08545-019 +25°C 10 1550 08545-016 NOISE FIGURE (dB) 1750 LO FREQUENCY (MHz) Figure 5. IIP2 vs. LO Frequency, RFIN = −5 dBm 14 1650 08545-018 2 Figure 9. LO Feedthrough to IF vs. LO Frequency, LO Output Turned Off Rev. 0 | Page 9 of 24 ADRF6602 Phase noise measurements made at LO output, unless otherwise noted. 1.0 0.9 –100 100kHz OFFSET 0.7 –110 0.6 10kHz OFFSET 0.5 –120 1MHz OFFSET 0.4 –130 INTERGRATED PHASE NOISE 0.3 –140 0.2 10MHz OFFSET –150 –90 LO = 2134.4MHz PHASE NOISE (dBc/Hz) 0.8 INTEGRATED PHASE NOISE (°rms) 1kHz OFFSET 1650 1750 1850 1950 2050 0 2150 LO FREQUENCY (MHz) Figure 10. PLL Spot Phase Noise at Various Offsets and Integrated Phase Noise vs. LO Frequency –75 1× PFD OFFSET –85 2× PFD OFFSET –90 –95 –105 –110 1550 4× PFD OFFSET 1650 1750 1850 1950 2050 LO FREQUENCY (MHz) 2150 08545-021 SPURS LEVEL (dBc) –80 0.25× AND 0.5× PFD OFFSET –110 –120 LO = 1558.4MHz –130 –140 –160 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) Figure 12. Phase Noise vs. Offset Frequency and LO Frequency (LO Frequency Varies from 1550 MHz to 2150 MHz) –70 –100 –100 –150 0.1 08545-020 SPOT PHASE NOISE (dBc/Hz) –90 –160 1550 –80 Figure 11. PLL Reference Spurs vs. LO Frequency Rev. 0 | Page 10 of 24 08545-022 –80 ADRF6602 REGISTER STRUCTURE This section provides the register maps for the ADRF6602. The three LSBs determine the register that is programmed. REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) DIVIDE MODE RESERVED INTEGER DIVIDE RATIO CONTROL BITS DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) DM DIVIDE MODE 0 FRACTIONAL (DEFAULT) 1 INTEGER ID6 ID5 ID4 ID3 ID2 ID1 ID0 INTEGER DIVIDE RATIO 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 1 1 1 1 0 1 0 122 (INTEGER MODE ONLY) 1 1 1 1 0 1 1 123 (INTEGER MODE ONLY) 08545-004 DB23 Figure 13. Register 0—Integer Divide Control Register Map REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) 0 0 MODULUS VALUE CONTROL BITS DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1 1 1 2047 Figure 14. Register 1—Modulus Divide Control Register Map Rev. 0 | Page 11 of 24 08545-005 RESERVED DB23 DB22 ADRF6602 REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED CONTROL BITS FRACTIONAL VALUE DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0) FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 08545-006 DB23 <MDR FRACTIONAL VALUE MUST BE LESS THAN MODULUS Figure 15. Register 2—Fractional Divide Control Register Map REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) DITHER DITHER RESTART VALUE ENABLE DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DEN DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DITH1 0 0 DITH0 0 1 DITHER MAGNITUDE 15 (DEFAULT) 7 1 0 3 1 1 1 (RECOMMENDED) DEN 0 1 CONTROL BITS DB7 DB6 DB5 DV4 DV3 DV2 DB4 DB3 DB2 DB1 DB0 DV1 DV0 C3(0) C2(1) C1(1) DITHER ENABLE DISABLE (RECOMMENDED) ENABLE (DEFAULT) DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DITHER RESTART VALUE 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 1 ... ... 1 0x00001 (DEFAULT) ... ... 0x1FFFF 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 0 ... ... 1 Figure 16. Register 3—Σ-Δ Modulator Dither Control Register Map Rev. 0 | Page 12 of 24 08545-007 DB23 0 DITHER MAGNITUDE DB22 DB21 DITH1 DITH0 ADRF6602 REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4) REF OUPUT MUX SELECT DB23 DB22 CP CURRENT REF SOURCE INPUT REF PATH DB21 DB20 DB19 RMS2 RMS1 RMS0 RS1 RS0 PFD PHASE OFFSET MULTIPLIER PFD POL CP CURRENT CP SRC DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 CP CONTROL PFD EDGE DB8 DB18 DB17 DB6 DB5 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPCT1 CPCT0 PE1 DB7 PE0 PFD ANTI BACKLASH DELAY DB4 DB3 CONTROL BITS DB2 DB1 DB0 PAB1 PAB0 C3(1) C2(0) C1(0) PAB0 PAB1 PFD ANTI BACKLASH DELAY 0 0 1 1 PE1 0 1 0 1 0 1 0ns (DEFAULT) 0.5ns 0.75ns 0.9ns PE0 REFERENCE PATH EDGE SENSITIVITY 0 1 FALLING EDGE RISING EDGE (DEFAULT) DIVIDER PATH EDGE SENSITIVITY FALLING EDGE RISING EDGE (DEFAULT) CPC1 CPC0 CHARGE PUMP CONTROL 0 0 1 1 0 1 0 1 BOTH ON PUMP DOWN PUMP UP TRISTATE (DEFAULT) CPS CHARGE PUMP CONTROL SOURCE 0 1 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) CONTROL FROM PFD (DEFAULT) CPP1 CPP0 CHARGE PUMP CURRENT 0 0 1 1 CPM 0 1 0 1 0 1 250µA 500µA (DEFAULT) 750µA 1000µA CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 0 0 1 1 0 × 22.5°/ICPMULT 1 × 22.5°/ICPMULT 4 × 22.5°/ICPMULT (RECOMMENDED) 10 × 22.5°/ICPMULT (DEFAULT) 16 × 22.5°/ICPMULT 31 × 22.5°/ICPMULT 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 CPBD PFD PHASE OFFSET POLARITY 0 1 NEGATIVE POSITIVE (DEFAULT) CHARGE PUMP CURRENT REFERENCE SOURCE INTERNAL (DEFAULT) EXTERNAL RS0 RS1 INPUT REFERENCE PATH SOURCE 0 0 1 1 0 1 0 1 2× REFIN REFIN (DEFAULT) 0.5× REFIN 0.25× REFIN RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LOCK DETECT (DEFAULT) VPTAT REFIN (BUFFERED) 0.5× REFIN (BUFFERED) 2× REFIN (BUFFERED) TRISTATE 0.25× REFIN (BUFFERED) DGND 08545-008 0 0 0 0 1 1 1 1 Figure 17. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map Rev. 0 | Page 13 of 24 ADRF6602 REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5) CAP DAC RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 0 0 0 0 0 0 0 0 0 0 CD3 PLL EN LO DIV1 LO EXT LO DRV DB7 DB6 DB5 DB4 DB3 0 PLEN LDV1 LXL CD2 CD1 CD0 CONTROL BITS DB2 DB1 DB0 LDRV C3(1) C2(0) C1(1) CD3 CD2 CD1 CD0 CAPACITOR DAC CONTROL FOR IIP3 OPTIMIZATION LDRV LO OUTPUT DRIVER ENABLE 0 1 0 1 0 1 0 1 MIN MAX 0 1 DRIVER OFF (DEFAULT) DRIVER ON LXL EXTERNAL LO DRIVE ENABLE (PIN 37, PIN 38) 0 1 INTERNAL LO OUTPUT (DEFAULT) EXTERNAL LO INPUT LDV1 DIVIDE-BY-2 IN LO CHAIN ENABLE 0 1 DIVIDE BY 1 DIVIDE BY 2 (DEFAULT) PLEN PLL ENABLE 0 1 DISABLE ENABLE (DEFAULT) 08545-009 0 RES Figure 18. Register 5—PLL Enable and LO Path Control Register Map REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: 0x1E2106) CHARGE 3.3V VCO LDO VCO VCO PUMP LDO ENABLE ENABLE ENABLE ENABLE SWITCH DB23 DB22 DB21 0 0 0 DB20 CPEN DB19 L3EN DB18 LVEN VCO AMPLITUDE DISABLE ENABLE (DEFAULT) L3EN 3.3V LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) LVEN VCO LDO ENABLE 0 1 DISABLE ENABLE (DEFAULT) VCO BAND SELECT FROM SPI CONTROL BITS DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 C3(1) C2(1) C1(0) CPEN CHARGE PUMP ENABLE 0 1 VCO BW SW CTRL VC[5:0] VCO AMPLITUDE VBS[5:0] VCO BAND SELECT FROM SPI 0x00 …. 0x18 …. 0x2B …. 0x3F 0 …. 24 (DEFAULT) …. 43 (RECOMMENDED) …. 63 0x00 0x01 …. 0x3F DEFAULT 0x20 VCO SW VCO SWITCH CONTROL FROM SPI 0 1 REGULAR (DEFAULT) BAND CAL VCO EN VCO ENABLE 0 1 DISABLE ENABLE (DEFAULT) VBSRC VCO BW CAL AND SW SOURCE CONTROL 0 1 BAND CAL (DEFAULT) SPI 08545-010 RESERVED Figure 19. Register 6—VCO Control and VCO Enable Register Map REGISTER 7—MIXER BIAS ENABLE AND EXTERNAL VCO ENABLE (DEFAULT: 0x000007) RES MIXER XVCO B_EN RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 0 XVCO MBE 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTROL BITS DB7 DB6 DB5 0 0 0 DB4 DB3 DB2 DB1 DB0 0 0 C3(1) C2(1) C1(1) MBE MIXER BIAS ENABLE DISABLE 0 ENABLE (DEFAULT) 1 EXTERNAL VCO INTERNAL VCO (DEFAULT) EXTERNAL VCO 08545-011 XVCO 0 1 Figure 20. Register 7—Mixer Bias Enable and External VCO Enable Register Map Rev. 0 | Page 14 of 24 ADRF6602 THEORY OF OPERATION The ADRF6602 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer optimization functions, as well as allowing for an externally applied LO or VCO. The mixer core within the ADRF6602 is the next generation of an industry leading family of mixers from Analog Devices, Inc. The RF input is converted to a current and then mixed down to IF using high performance NPN transistors. The mixer output currents are transformed to a differential output. The high performance active mixer core results in an exceptional IIP3 and IP1dB, with a very low output noise floor for excellent dynamic range. Over the specified frequency range, the ADRF6602 typically provides IF input P1dB of 14.5 dBm and IIP3 of 30 dBm. Improved performance at specific frequencies can be achieved with the use of the internal capacitor DAC (CDAC), which is programmable via the SPI port, and through the use of a resistor to a +5 V supply from the IP3SET pin (Pin 29). Adjustment of the capacitor DAC allows increments in phase shift at internal nodes in the ADRF6602, thus allowing cancellation of thirdorder distortion with no change in supply current. Connecting a resistor to a +5 V supply from the IP3SET pin increases the internal mixer core current, thereby improving overall IIP2 and IIP3, as well as IP1dB. Using the IP3SET pin for this purpose increases the overall supply current. The fractional divide function of the PLL allows the frequency multiplication value from REF_IN to LO output to be a fractional value rather than be restricted to an integer value as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD), where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all programmable via the SPI port. In other fractional-N PLL designs, fractional multiplication is achieved by periodically changing the fractional value in a deterministic way. The disadvantage of this approach is often spurious components close to the fundamental signal. In the ADRF6602, a Σ-Δ modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function. PROGRAMMING THE ADRF6602 The ADRF6602 is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 7. Table 7. ADRF6602 Register Functions Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Function Integer divide control for the PLL Modulus divide control for the PLL Fractional divide control for the PLL Σ-Δ modulator dither control PLL charge pump, PFD, reference path control PLL enable and LO path control VCO control and VCO enable Mixer bias enable and external VCO enable Note that internal calibration for the PLL must be run when the ADRF6602 is initialized at a given frequency. This calibration is run automatically whenever Register 0, Register 1, or Register 2 is programmed. Because the other registers affect PLL performance, Register 0, Register 1, and Register 2 should always be programmed last and in this order: Register 0, Register 1, Register 2. To program the frequency of the ADRF6602, the user typically programs only Register 0, Register 1, and Register 2. However, if registers other than these are programmed first, a short delay should be inserted before programming Register 0. This delay ensures that the VCO band calibration has sufficient time to complete before the final band calibration for Register 0 is initiated. Software is available on the product page of the Analog Devices website (www.analog.com) that allows easy programming from a PC running Windows XP or Vista. INITIALIZATION SEQUENCE To ensure proper power-up of the ADRF6602, it is important to reset the PLL circuitry after the VCC supply rail settles to 5 V ± 0.25 V. Resetting the PLL ensures that the internal bias cells are properly configured, even under poor supply start-up conditions. To ensure that the PLL is reset after power-up, follow this procedure: 1. 2. 3. Disable the PLL by setting the PLEN bit to 0 (Register 5, Bit DB6). Disable the VCO LDO internal node by setting the LVEN bit to 0 (Register 6, Bit DB18). After a delay of >100 ms, set the PLEN and LVEN bits to 1. After this procedure, the other registers can be programmed, in order, from Register 7 to Register 3, and then from Register 0 to Register 2, as described in the Programming the ADRF6602 section. Rev. 0 | Page 15 of 24 ADRF6602 LO SELECTION LOGIC The downconverting mixer in the ADRF6602 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the internal PLL, the LO signal can be accessed directly at these same pins. This function can be used for debugging purposes, or the internally generated LO can be used as the LO for a separate mixer. The operation of the LO generation and whether LOP and LON are inputs or outputs are determined by the logic levels applied at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3 (LDRV) and Bit DB6 (PLEN) in Register 5. The combination of externally applied logic and internal bits required for particular LO functions is given in Table 8. Table 8. LO Selection Logic Pin 16 (PLL_EN) 0 0 1 1 1 1 1 Pins1 Pin 36 (LODRV_EN) X X X 0 X 1 Register 5 Bits1 Bit DB6 (PLEN) Bit DB3 (LDRV) 0 X 1 X 0 X 1 0 1 1 1 X X = don’t care. Rev. 0 | Page 16 of 24 Output Buffer Disabled Disabled Disabled Disabled Enabled Enabled Outputs LO External External External Internal Internal Internal ADRF6602 APPLICATIONS INFORMATION shown in Figure 21. The reference signal, or a divided-down version of the reference signal, can be brought back off chip at the multiplexer output pin (MUXOUT). A lock detect signal and a voltage proportional to the ambient temperature can also be selected on the multiplexer output pin. BASIC CONNECTIONS FOR OPERATION Figure 21 shows the schematic for the ADRF6602 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 μF capacitors located as close as possible to the device. In addition, the internal decoupling nodes (DECL3P3, DECL2P5, and DECLVCO) should be decoupled with the capacitor values shown in Figure 21. The loop filter is connected between the CP and VTUNE pins. When connected in this way, the internal VCO is operational. For information about the loop filter components, see the Evaluation Board Configuration Options section. The RF input is internally ac-coupled and needs no external bias. The IF outputs are open collector, and a bias inductor is required from these outputs to VCC. Operation with an external VCO is also possible. In this case, the loop filter components should be referred to ground. The output of the loop filter is connected to the input voltage pin of the external VCO. The output of the VCO is brought back into the device on the LOP and LON pins, using a balun if necessary. The reference frequency for the PLL should be from 12 MHz to 160 MHz and should be applied to the REF_IN pin, which should be ac-coupled and terminated with a 50 Ω resistor as 1 2 3 4 5 6 VCC S2 LO IN/OUT R41 0Ω (0402) LODRV_EN LON 4 3 5 1 C20 0.1µF (0402) C19 0.1µF (0402) C32 OPEN (0402) R45 OPEN (0402) R6 0Ω (0402) C8 100pF (0402) R27 0Ω (0402) C26 100pF (0402) R26 0Ω (0402) C24 100pF (0402) R25 0Ω (0402) C22 100pF (0402) R24 0Ω (0402) C21 100pF (0402) R17 0Ω (0402) C18 100pF (0402) C30 OPEN (0402) R42 OPEN (0402) VCC_LO 22 VCC2 17 VCC1 10 1 16 R73 49.9Ω (0402) 37 14 DIVIDER ÷2 BUFFER BUFFER DECL2P5 FRACTION REG MODULUS DIV BY 4, 2, 1 2:1 MUX INTEGER REG 26 THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 6 N COUNTER 21 TO 123 TEMP SENSOR 8 4 7 11 15 20 21 23 24 25 28 30 31 35 RSET R2 R37 OPEN 0Ω (0402) (0402) CP TEST POINT (ORANGE) R38 0Ω (0402) 29 5 R10 1.6kΩ (0603) C15 5.6nF (1206) 3 39 CP R11 OPEN (0402) C43 10µF (0603) C2 OPEN (0402) 40 18 VTUNE DECLVCO R1 0Ω (0402) C11 0.1µF (0402) C41 OPEN (0603) IP3SET C40 OPEN (0603) IFN VCC +5V VTUNE R63 OPEN (0402) RFIN C27 0.1µF (0402) 19 IFP R62 0Ω (0402) C13 27pF (0603) C12 R8 100pF 0Ω (0402) (0402) R27 0Ω (0402) R9 18kΩ R65 0Ω (0402) (0402) C14 270pF (0603) C42 10µF (0603) R22 0Ω (0402) CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA – PHASE + FREQUENCY DETECTOR C17 0.1µF (0402) RFIN VCO CORE PRESCALER ÷2 MUX C16 R18 100pF 0Ω (0402) (0402) DECL3P3 2 ADRF6602 ÷2 MUXOUT R16 0Ω (0402) 12 9 ÷4 REFOUT 13 SPI INTERFACE C5 1nF LOP 38 (0402) C13 1nF (0402) REF_IN REF_IN VCC_MIX 27 LE VCC_V2I DATA C23 0.1µF (0402) CLK C25 0.1µF (0402) 36 T8 TC1-1-13+ C6 1nF (0402) R44 OPEN (0402) C27 0.1µF (0402) PLL_EN VCC_LO C31 OPEN (0402) C7 0.1µF (0402) 34 R40 0Ω (0402) P1 9-PIN DSUB 9 R47 10kΩ (0402) VCC RED +5V VCC1 RED R39 OPEN (0402) S1 OPEN 8 R36 0Ω R30 (0402) 0Ω (0402) R48 0Ω (0402) R35 0Ω (0402) R19 0Ω R20 (0402) 0Ω (0402) R43 10kΩ (0402) 7 1 4 2 R27 0Ω 3 (0402) 5 RFOUT R43 0Ω (0402) C29 0.1µF (0402) R12 0Ω (0402) C1 100pF (0402) Figure 21. Basic Connections for Operation of the ADRF6602 Rev. 0 | Page 17 of 24 08545-024 A peak-to-peak differential swing on RFIN of 1 V (0.353 V rms for a sine wave input) results in an IF output power of 3.8 dBm. ADRF6602 EVALUATION BOARD Figure 24 shows the schematic of the RoHS-compliant evaluation board for the ADRF6602. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if the design can accept the slightly higher trace loss of this material. The evaluation board is designed to operate using the internal VCO of the device (the default configuration) or with an external VCO. To use an external VCO, R62 and R12 should be removed. Place 0 Ω resistors in R63 and R11. The input of the external VCO should be connected to the VTUNE SMA connector, and the external VCO output should be connected to the LO IN/OUT SMA connector. In addition to these hardware changes, internal register settings must also be changed to enable operation with an external VCO (see the Register 6— VCO Control and VCO Enable (Default: 0x1E2106) section). Additional configuration options for the evaluation board are described in Table 9. EVALUATION BOARD CONTROL SOFTWARE Software to program the ADRF6602 is available for download from www.analog.com. To install the software, download and extract the zip file. Then run the following installation file: ADRF6x0x_3p0p0_XP_install.exe To connect the evaluation board to a USB port, a USB adapter board (Part No. EVAL-ADF4XXXZ-USB) must be purchased from www.analog.com. This board connects to the PC using a standard USB cable with USB mini-connector at one end. An additional 25-pin male to 9-pin female adapter is required to mate the ADF4XXXZ-USB board to the 9-pin D-Sub connector on the ADRF6602 evaluation board. 08545-025 The evaluation board can be connected to the PC using a PC parallel port or a USB port. These options are selectable from the opening menu of the software interface (see Figure 22). The evaluation board is shipped with a 25-pin parallel port cable for connection to the PC parallel port. Figure 22. Control Software Opening Menu Figure 23 shows the main menu of the control software with the default settings displayed. Rev. 0 | Page 18 of 24 08545-026 ADRF6602 Figure 23. Main Screen of the ADRF6602 Evaluation Board Software Rev. 0 | Page 19 of 24 3P3V_LDO AG ND REFIN OSC_3P3V AG N D AG ND AG ND AG ND R70 49.9 1 1000PF C31 10PF 22000 PF C3 C4 0 R15 0.1UF OSC_3P3V C11 AG N D 100PF C12 AG N D AG N D 0 100PF R8 C10 0 VCC_LO 0.1UF 10UF 1 R29 R7 0 0 10UF VCC_BB AG N D C28 1000PF C14 AGN D DNI R49 0 R16 VCO_LDO R11 2P5V_LDO REFOUT R37 0 C9 3P3V1 1 C41 VCC VCC4 CP DNI 1 AG ND 0.1UF C2 0 R1 VCC AG ND C42 10UF 1 AG ND AG ND C18 100PF AG ND C19 0.1UF AG ND 0 100PF 0.1UF R17 0 R18 C16 AG N D C17 VCC2 1 2P5V AG N D AG ND 100PF C1 0 1K P1-1 10UF C43 VCO_LDO R65 C13 470PF AG ND 1 AG N D GND1 R9 0.022UF C15 VCC_SENSE R12 R32 R38 0 R2 9 8 7 6 5 4 3 2 1 P1 R63 100K P1-6 40 P1-6 R36 R57 R30 0 0 0 DIG_GND 0 R19 1 37 100PF DNI 1 Z1 AG N D 16 AG N D R53 10K 15 35 2 AG ND 100PF DNI C34 AG ND 36 VCC 34 AG ND 17 1 VCC5 1 VCC R54 10K 33 AG N D R56 10K P3-T7 3 1 18 32 30 21 22 23 AG ND AGN D C20 0.1UF 1 VCC_LO1 C21 0 R24 VCC_LO R25 AG N D VCC_BB1 AG ND C25 0.1UF 0 R26 1 VCC_RF VCC_BB C24 AG ND 0.1UF C27 100PF TBD R27 R58 DNI VCC VCC AG N D TBD L2 TBD AG N D C23 0.1UF L1 0 C22 100PF 1 DNI C36 DNI C35 VCC_BB 0 R48 0 R47 0 R60 TBD IP3SET OUTPUT_EN R28 AG ND 1 IP3SET VCC_LO AG N D LO 24 AG N D IP3SET AG ND 0 R69 25 26 27 28 29 E-PAD PAD GND VCC_MIX GND GND GND RFIN VCC_V2I GND IP3SET GND AG ND AG ND 0.1UF 100PF 1 VCC_LO C7 0 R6 AGN D P1-T7 AG N D C8 NC 4 2 5 P4-T7 P4-T7 100PF AG ND 20 T8 4A 5A 4 3 2A 3A 6A 5 2 6 1A OUTPUT_EN 19 31 LO_EXTERN P3-T7 P3-T7 P4-T7 3 LE 14 DATA 13 1 VCC1 S2 R52 1K DNI 38 C33 12 R51 1K DNI AG N D 39 1NF R55 10K C5 C6 1NF 11 100PF DNI C32 VCC2 9 DECL2P5 8 MUXOUT 7 GND 6 REF_IN 5 R SET 4 GND 3 CP 2 DECL3P3 1 VCC1 10 P1-1 R50 1K DNI CLK DNI 1 AMP745781 -4 C40 TBD AG ND VTUNE 1 GND2 0 0 VCC_RF 1 DNI AG ND SNS R10 R71 R72 R62 SNS1 0 806 TBD 3 1 1 P1-T7 IFP GND LE AG N D IFN VCC PLL_EN R33 NC 0 NC 0 R31 Y1 R14 DECLVCO GND VTUNE DATA VCC_LO VCC_LO T7 AG N D AG N D IFN IFP VCC_RF AGN D RFIN 0 R67 0 DNI R68 VCO_LDO VCC AGND VCC_SENSE AGND 3P3V_LDO 2P5V_LDO LO_EXTERN 0 1 R43 1 LOP R35 LON 0 GND GND S1 LODRV_EN GND T3 4 1 VCC CLK 1 AG N D OUT DNI R44 AG ND 0.1UF C29 2 2 GND R20 Rev. 0 | Page 20 of 24 0 R34 Figure 24. Evaluation Board Schematic 0 6 3 P1-T7 TC4-1W VCC R59 0 J1 1 J1 2 J1 3 J1 4 J1 5 J1 6 J1 7 J1 8 J1 9 J1 10 AG ND ADRF6602 SCHEMATICS AND ARTWORK 08545-023 R66 0 08545-012 08545-013 ADRF6602 Figure 25. Evaluation Board Layout (Bottom) Figure 26. Evaluation Board Layout (Top) Rev. 0 | Page 21 of 24 ADRF6602 EVALUATION BOARD CONFIGURATION OPTIONS Table 9. Component S1, R55, R56, R33 Description LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins function as inputs or outputs (see the LO Selection Logic section for more information). LO IN/OUT SMA Connector REFIN SMA Connector REFOUT SMA Connector LO input/output. An external 1× LO or 2× LO can be applied to this single-ended input connector. Reference input. The input reference frequency for the PLL is applied to this connector. Input impedance is 50 Ω. Multiplexer output. The REFOUT connector connects directly to the MUXOUT pin. The on-board multiplexer can be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, REFIN/4. Temperature sensor output voltage. Lock detect indicator. Charge pump test point. The unfiltered charge pump signal can be probed at this test point. Note that the CP pin should not be probed during critical measurements such as phase noise. Loop filter. Loop filter components. CP Test Point R37, C14, R9, R10, C15, C13, R65, C40 R11, R12 R62, R63, VTUNE SMA Connector R2 RFIN SMA Connector T3 Loop filter return. When the internal VCO is used, the loop filter components should be returned to Pin 40 (DECLVCO) by installing a 0 Ω resistor in R12. When an external VCO is used, the loop filter components can be returned to ground by installing a 0 Ω resistor in R11. Internal vs. external VCO. When the internal VCO is enabled, the loop filter components are connected directly to the VTUNE pin (Pin 39) by installing a 0 Ω resistor in R62. To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. RSET pin. This pin is unused and should be left open. RF input. The RF input signal should be applied to the RFIN SMA connector. The RF input of the ADRF6602 is ac-coupled, so no bias is necessary. IF output. The differential IF output signals from the ADRF6602 (IFP and IFN) are converted to a single-ended signal by T3. Rev. 0 | Page 22 of 24 Default Condition/ Option Settings S1 = R55 = open (not installed) R56 = R33 = 0 Ω LODRV_EN = 0 V LO input Lock detect R12 = 0 Ω (0402) R11 = open (0402) R62 = 0 Ω (0402) R63 = open (0402) R2 = open (0402) R3 = R23 = open (0402) ADRF6602 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 1 4.25 4.10 SQ 3.95 EXPOSED PAD (BOT TOM VIEW) 21 20 11 10 0.25 MIN 4.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 40 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 072108-A PIN 1 INDICATOR 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 Figure 27. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF6602ACPZ-R7 ADRF6602-EVALZ 1 Temperature Range −40°C to +85°C Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 23 of 24 Package Option CP-40-1 ADRF6602 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08545-0-1/10(0) Rev. 0 | Page 24 of 24