19-0222; Rev 0; 5/05 KIT ATION EVALU E L B A AVAIL Complete 450MHz Quadrature Transmitter Features The MAX2370 integrated quadrature transmitter is designed for 450MHz applications. The device takes a differential I/Q baseband input and converts it up to intermediate frequency (IF) through a quadrature modulator and IF variable-gain amplifier (VGA). The signal is then routed to an external IF filter and upconverted to RF through an image-reject mixer and RF VGA. The signal is further amplified with an on-chip power amplifier (PA) driver. An IF synthesizer, an RF synthesizer, a local oscillator buffer, and an SPI™/QSPI™/MICROWIRE™compatible, 3-wire programmable bus complete the basic functional blocks of this IC. ♦ 450MHz Operating Frequency The MAX2370 is available in a 48-pin TQFN package with exposed paddle and is specified for the extended temperature range (-40°C to +85°C). ♦ Directly Drives External Power Amplifier ♦ +8dBm Output Power -64dBc Typical ACPR at ±885kHz Offset -66dBc Typical ACPR at ±1.125MHz Offset ♦ 100dB Power-Control Range ♦ Dual Synthesizer for RF and IF Local Oscillators ♦ SPI/QSPI/MICROWIRE-Compatible 3-Wire Interface Bus ♦ Single-Sideband Upconverter Ordering Information Applications 450MHz CDMA/WCDMA Phones OFDM, cdma2000®, WCDMA, NMT Wireless Data Links PART PKG CODE TEMP RANGE PIN-PACKAGE MAX2370ETM -40°C to +85°C 48 Thin QFN-EP* (7mm x 7mm) MAX2370ETM+ -40°C to +85°C 48 Thin QFN-EP* T4877+3 (7mm x 7mm) T4877-3 *EP = Exposed paddle. +Denotes lead-free package. RFOUT N.C. 1 LOCK VCCDRV IDLE VCC 3 TXGATE IFIN+ IFINN.C. N.C. 7 VCC IFCP VCCIFCP 37 38 39 40 LO N.C. RFPLL VCCRFCP RFCP 44 41 GND 45 46 42 N.C. GND 47 36 RF PLL 2 IF PLL 35 34 Σ 4 33 0° 90° 5 6 +45 MAX2370 32 31 EP -45 30 29 8 28 9 10 11 Σ SPI INTERFACE 27 0° /2 90° 26 25 N.C. N.C. N.C. TANK+ TANKIFLO VCC SHDN II+ 24 23 22 REF N.C. VCC Q+ Q- 21 19 20 GC VCC 18 16 17 N.C. IFOUTIFOUT+ 14 15 13 12 DI CS N.C. RBIAS 43 GND 48 TOP VIEW CLK SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. cdma2000 is a registered trademark of Telecommunications Industry Association. Pin Configuration/ Functional Diagram ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2370 General Description MAX2370 Complete 450MHz Quadrature Transmitter ABSOLUTE MAXIMUM RATINGS VCC, RFOUT, VCCIFCP, VCCRFCP, VCCDRV to GND.................................................-0.3V to +3.6V DI, SCLK, CS, GC, SHDN, TXGATE, IDLE, LOCK to GND.........................................-0.3V to (VCC + 0.3V) AC Input Pins (IFIN_, Q_, I_, TANK_, REF, RFPLL, LO) to GND.....................................................1V Peak Digital Input Current (SHDN, TXGATE, IDLE, SCLK, DI, CS) ...............................................................±10mA Continuous Power Dissipation (TA = +70°C) 48-Pin Thin QFN (derate 38.5mW/°C above +70°C).....3077mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C CAUTION! ESD SENSITIVE DEVICE Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.3V, SHDN = IDLE = TXGATE = high, VGC = 2.5V, RBIAS = 10kΩ, registers set according to Table 1, fREF = 19.2MHz, no AC signals applied, TA = -40°C to +85°C. Typical values are at VCC = +3.0V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage Range Operating Supply Current Sleep-Mode Supply Current CONDITIONS VCC MIN TYP 2.7 UNITS 3.3 V VGC = 0.6V 53 79 VGC = 1.95V 57 87 PRFOUT = +5.5dBm, IFG[2:0] = 011 118 PRFOUT = +8dBm, IFG[2:0] = 011 134 Addition for IFLO buffer 3.4 7.7 IDLE = low 6 10 TXGATE = low 5 7 0.5 20 SHDN = 0V Logic-High Voltage mA 0.7 x VCC 0.3 x VCC Logic Input Current -5 GC Input Current VGC = 0.5V to 2.5V GC Input Current During Shutdown SHDN = low, VGC = 2.5V Lock Indicator High Voltage (Locked) 47kΩ pullup load Lock Indicator Low Voltage (Unlocked) 47kΩ pullup load µA V Logic-Low Voltage 2 MAX V +5 µA 3.3 5 µA 7 11 µA VCC 0.4V _______________________________________________________________________________________ V 0.5 V Complete 450MHz Quadrature Transmitter (MAX2370 EV kit, VCC = +2.7V to +3.3V, SHDN = IDLE = TXGATE = high, VGC = 2.5V, RBIAS = 10kΩ, 50Ω system, TA = -40°C to +85°C. Typical values are at VCC_ = SHDN = IDLE = TXGATE = CS = 3.0V, fREF = 19.2MHz, LO input power = -15dBm, fLO = 575MHz, f RFOUT = 455MHz, f IF = 120MHz, registers set according to Table 1, input voltage at I and Q = 130mV RMS differential, cascade specifications assume 400Ω IF filter with 5dB insertion loss, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS MODULATOR IF Frequency Range Typically meets 30dB sideband suppression over this frequency range I/Q Common-Mode Input Voltage (Notes 2, 3) I/Q Input Current VCM = 1.4V 95 to 195 1.35 +25°C < TA < +85°C Gain-Control Range VGC = 0.5V to 2.5V Gain Variation Over Temperature Relative to +25°C, TA = -40°C to +85°C Carrier Suppression Sideband Suppression VGC = 2.5V VGC = 2.5V IF Output Noise at Rx Band VGC set to give -12dBm IF output power, noise measured at 10MHz offset (Note 4) IF Adjacent Channel Power Ratio IS-95 Reverse Modulation VGC set to give -12dBm IF output power, IFG[2:0] = 011 70 TA = -40°C MHz VCC 1.25 V 6 µA 87 dB 85 30 30 -2.4, +3.4 dB 40 40 dB dB -138 fOFFSET = ±885kHz in 30kHz BW fOFFSET = ±1.125MHz in 30kHz BW -66 -69 fOFFSET = ±1.98MHz in 30kHz BW -84 fOFFSET = ±4MHz in 30kHz BW -89 -135 dBm/Hz dBc UPCONVERTER AND PREDRIVER RFOUT Frequency Range See the Typical Operating Characteristics for typical gain vs. frequency LO Frequency Range Typically meets 30dB image suppression over this range LO and RFPLL Input Power Conversion Gain MPL Gain Change 410 to 500 530 to 695 -15 MPL = 0, gain relative to MPL = 1 RF Gain-Control Range RF Image Suppression Rx Band Noise Power VGC = 0.5V to 2.5V +25°C < TA < +85°C -7 23 PRFOUT = +8dBm, noise measured at +10MHz offset (Note 4) -130 Adjacent Channel Power Ratio IS-95 Reverse Modulation (Note 4) POUT = +5.5dBm, IFG[2:0] = 011 5.5 dBm dB dB 44 46 -20 POUT = +8dBm, IFG[2:0] = 011 MHz 0 -3.4 30 TA = -40°C At maximum output power CASCADED MODULATOR, UPCONVERTER, AND PREDRIVER RFOUT Output Power Meets ACPR specifications (Note 4) MHz dB dBc -128.5 10 dBm/Hz dBm fOFFSET = ±885kHz in 30kHz BW -64 -57 fOFFSET = ±1.125MHz in 30kHz BW -66 -61 fOFFSET = ±1.98MHz in 30kHz BW fOFFSET = ±4MHz in 30kHz BW -82 -86 -78 -78 fOFFSET = ±885kHz in 30kHz BW -64 -58 fOFFSET = ±1.125MHz in 30kHz BW -67 -62 fOFFSET = ±1.98MHz in 30kHz BW fOFFSET = ±4MHz in 30kHz BW -81 -86 -78 -85 dBc _______________________________________________________________________________________ 3 MAX2370 AC ELECTRICAL CHARACTERISTICS MAX2370 Complete 450MHz Quadrature Transmitter AC ELECTRICAL CHARACTERISTICS (continued) (MAX2370 EV kit, VCC = +2.7V to +3.3V, SHDN = IDLE = TXGATE = high, VGC = 2.5V, RBIAS = 10kΩ, 50Ω system, TA = -40°C to +85°C. Typical values are at VCC_ = SHDN = IDLE = TXGATE = CS = 3.0V, fREF = 19.2MHz, LO input power = -15dBm, fLO = 575MHz, f RFOUT = 455MHz, f IF = 120MHz, registers set according to Table 1, input voltage at I and Q = 130mV RMS differential, cascade specifications assume 400Ω IF filter with 5dB insertion loss, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Output Power Variation Over Temperature CONDITIONS MIN Relative to +25°C, TA = -40°C to +85°C TYP MAX 0, -2 UNITS dB IF PLL Reference Frequency 5 30 MHz Reference Frequency Signal Level 0.1 0.6 VP-P IF Main-Divide Ratio IF Reference-Divide Ratio 256 2 16,383 2047 VCO Operating Range 190 to 390 MHz ICP = 00 96 139 174 ICP = 01 ICP = 10 135 190 192 278 240 348 ICP = 11 267 390 488 Turbolock Boost Current ICP = 11, ICP_MAX = 1 533 774 968 µA Charge-Pump Source/Sink Current Matching All values of ICP, over compliance range 6 % Charge-Pump Source/Sink Current IF Charge-Pump Compliance RF PLL RF PLL Frequency Range VCCIFCP 0.5V 0.5 RF PLL operated at 2x LO frequency MHz MHz 5 30 RF Main-Divide Ratio 4096 262,143 Charge-Pump Source/Sink Current Turbolock Boost Current Charge-Pump Source/Sink Current Matching RCP = 00 2 220 325 8191 406 RCP = 01 441 650 813 RCP = 10 499 738 923 RCP = 11 (Note 5) 717 1152 1063 1694 1329 2118 µA 6 % All values of RCP, over compliance range RF Charge-Pump Compliance Phase-Detector Noise Floor Note 1: Note 2: Note 3: Note 4: Note 5: 4 V 1300 Reference Frequency RF Reference-Divide Ratio µA VCCRFCP 0.5V 0.5 RCP = 11, RCP_TURBO1 = RCP_TURBO2 = 0, 50kHz comparison frequency µA -162 V dBc/Hz Guaranteed by production test at TA = +25°C to +85°C, design and characterization at TA = -40°C. ACPR is met over the specified VCM range. VCM must be supplied by the I/Q baseband source with ±8µA current capability. Guaranteed by design and characterization to 6σ. When enabled with RCP_TURBO1 and RCP_TURBO2 (see Tables 3 and 4), the total charge-pump current is specified. For all values of RCP, the total turbolock current is 1.63 times the corresponding nonturbo current value. _______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter MAX2370 Typical Operating Characteristics (MAX2370 EV kit, VCC_ = SHDN = IDLE = TXGATE = CS = 3.0V, fREF = 19.2MHz, LO input power = -15dBm, fLO = 575MHz, fRFOUT = 455MHz, fIF = 120MHz, RBIAS = 10kΩ, VGC = 2.5V, registers set according to Table 1, input voltage at I and Q = 130mVRMS differential, TA = +25°C, unless otherwise noted.) CURRENT 110 -60 90 -80 70 -100 50 POWER -30 -40 ACPR ±1.125MHz ACPR ±1.98MHz ACPR ±885kHz -50 -60 -70 -80 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 2.1 2.2 2.3 VGC (V) 2.4 2.5 2.6 0 -60 -70 -80 IMAGE SUPPRESSION 15 -30 10 -40 LO SUPPRESSION -50 0 -60 -2 -10 -40 0.5 -50 0.4 -90 1 2 3 5 4 IFG[2:0] (DECIMAL) 6 7 FREQUENCY (MHz) MAX2370 toc08 IF OUTPUT SPECTRUM 0.9 -10 -20 -20 0.8 -20 -30 -30 0.7 -30 -40 PHASE 0.6 -40 0.5 -50 0.4 -60 -70 S11 PHASE (°) S11 PHASE (°) S11 MAGNITUDE -10 -50 0.4 -60 0.3 -70 0.3 0.2 -80 0.2 -80 -90 -90 0.1 -90 -100 -100 -110 MAGNITUDE 0 500 520 540 560 580 600 620 640 660 680 700 FREQUENCY (MHz) POUT = -12dBm -50 0.5 FREQUENCY (MHz) -100 400 410 420 430 440 450 460 470 480 490 500 0 -100 -70 0 0.7 1300 -60 PHASE -16 0.8 1250 -30 0.6 -80 -10 1200 -20 MAGNITUDE 0.7 0.1 0.9 0 -10 -14 1.0 PHASE 0 0.2 0 -40 2.7 MAX2370 toc06 0.3 -12 0 MAGNITUDE 2.6 0.8 LO PORT S11 MAX2370 toc07 2.5 0.9 -8 RFPLL PORT S11 1.0 2.4 RFOUT PORT S22 -6 RF FREQUENCY (MHz) 1150 2.3 1.0 -4 400 410 420 430 440 450 460 470 480 490 500 1100 2.2 -60 -70 -80 FREQUENCY CENTER: 120MHz, SPAN: 5MHz, RBW: 30kHz _______________________________________________________________________________________ 5 S22 PHASE (°) RF GAIN (dB) -20 SUPPRESSION (dBc) 20 ACPR ±1.98MHz ACPR ±885kHz -50 2.1 S22 MAGNITUDE -10 1050 ACPR ±1.125MHz -40 NORMALIZED IF OUTPUT POWER vs. IFG[2:0] 0 NORMALIZED IF OUTPUT POWER (dB) 25 S11 MAGNITUDE -30 VGC (V) GAIN 0.1 POWER -20 2.7 MAX2370 toc05 MAX2370 toc04 30 0.6 0 -10 VGC (V) RF GAIN, IMAGE SUPPRESSION, AND LO SUPPRESSION vs. FREQUENCY 5 10 -90 -90 POWER (dBm) -40 -20 20 MAX2370 toc9 130 -10 RF OUTPUT POWER AND RF ACPR (dBm/dBc) -20 MAX2370 toc02 150 POWER SUPPLY CURRENT (mA) RF OUTPUT POWER (dBm) 0 RF OUTPUT POWER AND RF ACPR vs. GAIN-CONTROL VOLTAGE 0 170 IF OUTPUT POWER AND IF ACPR (dBm, dBc) MAX2370 toc01 20 IF OUTPUT POWER AND IF ACPR vs. GAIN-CONTROL VOLTAGE MAX2370 toc03 RF OUTPUT POWER AND SUPPLY CURRENT vs. GAIN-CONTROL VOLTAGE Typical Operating Characteristics (continued) (MAX2370 EV kit, VCC_ = SHDN = IDLE = TXGATE = CS = 3.0V, fREF = 19.2MHz, LO input power = -15dBm, fLO = 575MHz, fRFOUT = 455MHz, fIF = 120MHz, RBIAS = 10kΩ, VGC = 2.5V, registers set according to Table 1, input voltage at I and Q = 130mVRMS differential, TA = +25°C, unless otherwise noted.) MAX2370 toc10 POUT = +8dBm 0 -10 -10 MAX2370 toc11 IF LOCAL OSCILLATOR SPECTRUM RF OUTPUT SPECTRUM 10 PREF = -10dBm -20 -30 IF LO POWER (dBm) -20 POWER (dBm) MAX2370 Complete 450MHz Quadrature Transmitter -30 -40 -50 -60 -40 -50 -60 -70 -80 -70 -90 -80 -90 FREQUENCY CENTER: 455MHz, SPAN: 5MHz, RBW: 30kHz -100 239.8 239.9 240.0 240.1 240.2 240.3 FREQUENCY (MHz) Pin Description PIN NAME FUNCTION 1 RFOUT Transmitter RF Output. This open-collector output requires a pullup inductor to the supply voltage, which can be part of the output matching network. 2, 10, 11, 16, 17, 32–35, 43, 47 N.C. 3 LOCK 4 VCCDRV Power Supply for the RF Driver Stage. Bypass to PC board ground with a capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 5 IDLE Digital Input. Drive to logic-high for normal operation. Logic-low on IDLE shuts down everything except the RF PLL. A small RC lowpass filter can be used to filter digital noise. 6 VCC Power Supply for the Upconverter Stage. Bypass to PC board ground with a capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 7 TXGATE Digital Input. Drive to logic-high for normal operation. Logic-low on TXGATE shuts down everything except the RF PLL, IF PLL, IF VCO. A small RC lowpass can be used to filter digital noise. 8, 9 12 6 IFIN+, IFIN- RBIAS No Connection. Leave these pins open-circuit. Some of these pins are internally connected. Open-Drain Output Indicating LOCK Status of the IF and/or the RF PLLs. Requires an external pullup resistor. Control using configuration register bits LD_MODE[1:0]. Differential IF Inputs to the RF Upconverter. IFIN+ and IFIN- are internally biased to typically VCC 1.5V. The input impedance for this port is nominally 400Ω differential. AC-couple the output of the differential IF filter to this port. Keep the differential lines as short as possible to minimize the effects of stray pickup. Bias Resistor Connection. Internally biased to typically 1.18V. An external resistor must be connected from RBIAS to ground to set the bias current for the upconverters and PA driver stages. The nominal resistor value is 10kΩ. This value can be altered to optimize the linearity of the driver stage. _______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter PIN NAME 13, 14, 15 CLK, DI, CS 18, 19 20 FUNCTION CMOS Inputs from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE Compatible). A small RC lowpass filter on each of these pins can be used to reduce noise on these lines. Differential IF Outputs. This port is active when IF_SEL is LOW and supports both FM and CDMA modes. IFOUT+ and IFOUT- must be inductively pulled up to VCC and differentially loaded with typically 560Ω. A 400Ω differential IF bandpass filter is connected between this port and IFIN+/-. IFOUT-, IFOUT+ The pullup inductors can be part of the filter structure. The differential output impedance of this port is nominally 400Ω, including the 560Ω external differential resistor. Keep the transmission lines from these pins as short as possible to minimize the unintentional pickup of spurious signals and noise. RF and IF Gain-Control Analog Input. Accepts input voltages from 0.5V (minimum gain) to 2.5V (maximum gain). When not driven, GC is internally biased to typically 1.5V. RC lowpass filter the GC voltage applied to this pin to remove DAC noise or PDM clock spurs. 21 VCC Power Supply for the IF VGA. Bypass to PC board ground with a 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 22 VCC Power Supply for the I/Q Modulator. Bypass to PC board ground with a 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 23, 24 Q+, Q- Differential Q-Channel Baseband Inputs to the Modulator. Q+ and Q- connect directly to the bases of a differential pair and require a typical 1.35V to (VCC - 1.5V) external common-mode bias voltage. 25, 26 I+, I- Differential I-Channel Baseband Inputs to the Modulator. I+ and I- connect directly to the bases of a differential pair and require a typical 1.35V to (VCC - 1.5V) external common-mode bias voltage. 27 SHDN 28 VCC Power Supply for the VCO Section. Bypass to PC board ground with a 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 29 IFLO IF LO Output. Provides access to the IF VCO output and can be used to drive an external PLL. It can be disabled by logic-low on the BUF_EN control bit. IFLO is internally biased to typically 1.5V. 30, 31 TANK-, TANK+ Differential Tank Connections for the IF VCO. TANK+ and TANK- are internally biased to approximately 1.6V and must be AC-coupled to the external tank (can be DC-coupled if tank does not sink or source current). 36 REF Reference Frequency Input. REF is internally biased to approximately 1.0V and must be ACcoupled to the reference source. This is a high-impedance port and must be externally terminated in the desired impedance. 37 VCCIFCP Power Supply for the IF Charge Pump. This supply can be different from the system VCC. Bypass to PC board ground with a minimum 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. 38 IFCP High-Impedance IF Charge-Pump Output. Connect to the tune input of the IF VCO through the IF PLL loop filter. Keep the connection from IFCP to the tune input as short as possible to prevent spurious pickup. 39 VCC Power Supply for Digital Circuitry. Bypass to PC board ground with a minimum 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. Digital Input. Drive LOW to shut down the entire IC, drive high for normal operation. A small RC lowpass filter can be used to filter digital noise. _______________________________________________________________________________________ 7 MAX2370 Pin Description (continued) Complete 450MHz Quadrature Transmitter MAX2370 Pin Description (continued) PIN NAME 40 RFCP 41 VCCRFCP 42 RFPLL 44 LO 45, 46, 48, EP GND FUNCTION High-Impedance RF Charge-Pump Output. Connect to the tune input of the RF VCO through the RF PLL loop filter. Keep the connection from RFCP to the tune input as short as possible to prevent spurious pickup. Power Supply for the RF Charge Pump. This supply can be different from the system VCC. Bypass to PC board ground with a minimum 0.1µF capacitor placed as close to the pin as possible. Do not share capacitor ground vias with other ground connections. RF PLL Input. This port drives the RF PLL. RFPLL is internally biased to typically VCC - 0.8V. RF LO Input. LO is internally biased to typically VCC - 0.8V. Ground Connection. Solder the exposed paddle (EP) evenly to the board’s ground plane for proper operation. Detailed Description The MAX2370 complete quadrature transmitter accepts differential I/Q baseband inputs with external commonmode bias. A modulator upconverts the baseband inputs to a 95MHz to 195MHz IF frequency. A gain-control voltage pin (GC) controls the gain of both the IF and RF VGAs simultaneously to achieve the best current consumption and linearity performance. The IF signal is brought off-chip for filtering, then fed to a single sideband upconverter followed by the RF VGA and PA driver. The RF upconverter requires an external VCO for operation. The IF PLL, RF PLL, and operating mode can be programmed by an SPI/QSPI/ MICROWIRE-compatible 3-wire interface. The following sections describe each block in the Functional Diagram. I/Q Modulator Differential in-phase (I) and quadrature-phase (Q) inputs are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). The I and Q inputs need a typical DC bias of VCC / 2 and a current-drive capability of 8µA. However, common-mode voltages in the 1.35V to (VCC - 1.25V) range are also acceptable. The I and Q input capacitances are typically 0.6pF to ground on each pin. The IF VCO output is fed into a divide-by-two quadrature generator block to derive quadrature LO components to drive the I/Q modulator. The output of the modulator is fed into the IF VGA. IF VCO The IF VCO oscillates at twice the desired IF frequency. The oscillation frequency is determined by external tank components (see the IF Tank Design section). Typical spurious performance for the IF VCO is shown in the Typical Operating Characteristics. 8 IFLO Output Buffer IFLO provides a buffered LO output when BUF_EN is 1. The IFLO output frequency is equal to the IF VCO frequency, and the typical output power is -12dBm. This output is intended for applications where the receive IF is the same frequency as the transmit IF. IF/RF PLL The IF/RF PLL uses a charge-pump output to drive external loop filters. The loop filter is typically a passive second-order lead-lag filter. Outside the filter’s bandwidth, phase noise is determined by the tank components. The two components that contribute most significantly to phase noise are the inductor and varactor. Use high-Q inductors and varactors to maximize equivalent parallel resistance. The IF_TURBO_CHARGE, RCP_TURBO1, and RCP_TURBO2 bits can be set to enable turbo mode. Turbo mode provides maximum charge-pump current during frequency acquisition. Turbo mode is disabled after frequency acquisition is achieved. When turbo mode is disabled, charge-pump current returns to the programmed levels as set by the ICP and RCP bits in the CONFIG register (Table 3). IF VGA The IF VGA allows the IF output level to be controlled by a voltage applied to the GC pin. The 0.5V to 2.5V voltage range on GC provides a gain-control range of > 70dB, with 2.5V providing maximum gain. The differential IF output ports are optimized for the 95MHz to 195MHz frequency range. Do not allow VGC to exceed VCC - 0.2V as this may cause oscillations at cold temperatures. Single-Sideband Mixer and RF VGA The RF transmit mixer uses a single-sideband architecture to eliminate an off-chip RF filter. The RF VGA follows the single-sideband mixer and is controlled by the same GC voltage as the IF VGA to provide optimum _______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter output power at the expense of 3.4dB less maximum obtainable output power. PA Driver Power Management Bias control is distributed among several functional sections and can be controlled to accommodate many different power-down modes as shown in Table 8. The serial interface remains active during shutdown. Setting bit SHDN_BIT = 0 or pin SHDN = GND powers down the device. In either case, PLL programming and register information is retained. The MAX2370 includes a PA driver that is optimized for the 410MHz to 500MHz RF frequency range. The PA driver is an open-collector output and requires a pullup inductor to VCC. The pullup inductor can act as a shunt element in a shunt-series matching network. Programmable Registers The MAX2370 includes eight programmable registers consisting of four divide registers, a configuration register, an operational control register, a current control register, and a test register. Each register consists of 24 bits. The 4 least significant bits (LSBs) are the register’s address. The 20 most significant bits (MSBs) are used for register data. All registers contain some “don’t care” bits. These can be either a 0 or 1 and do not affect operation (Figure 1). Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Typical register settings for the eight registers are shown in Table 1. The dividers and control registers are programmed from the SPI/QSPI/MICROWIRE-compatible serial port. The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference frequency divide ratio. The RF VCO frequency can be determined by the following: RF VCO frequency = fREF x (RFM / RFR) The IFM and IFR registers are similar: IF VCO frequency = fREF x (IFM / IFR) where fREF is the external reference frequency. The operational control register (OPCTRL) controls the state of the MAX2370. See Table 2 for a description of each bit’s function. The configuration register (CONFIG) sets the configuration for the RF and IF PLL and the baseband I/Q input levels. See Table 3 for a description of each bit’s function. The current-control register (ICCCTRL) modifies the bias current to accommodate different operating modes. In the high-power mode, MPL = 1 sets the bias current and conversion gain to deliver an output power of at least +5.5dBm from the PA drivers. In the low-noise mode, MPL = 0 reduces output noise by 2.5dB for any given Applications Information 3-Wire Serial Interface Figure 3 shows the 3-wire interface timing diagram. The 3-wire bus is SPI/QSPI/MICROWIRE compatible. Electromagnetic Compliance Considerations To produce a low-spur and EMC-compliant transmitter, minimize circular current-loop area to reduce H-field radiation. To minimize circular current-loop area, bypass all VCC pins as close to the device as possible and use the distributed capacitance of a ground plane. To minimize voltage drops, make VCC traces short and wide. Program only the necessary bits in any register to minimize cycling of the serial interface’s clock. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing high-frequency spectral content. RC filtering also provides transient protection by shunting high frequencies to ground, while the series resistance attenuates the transients for error-free operation. The same applies to the logic input pins (SHDN, TXGATE, IDLE). Place high-frequency bypass capacitors close to the pins with a dedicated via for each capacitor to ground. The 48-pin thin QFN-EP package provides minimal ground inductance by using an exposed paddle under the part. Provide at least five low-inductance vias under the exposed paddle to ground. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as a slot radiator and reduce its shield effectiveness. Keep RF LO traces as short as possible to reduce LO radiation and susceptibility to interference. IF Tank Design The IF tank is fully differential. The external tank components for 120MHz IF operation are shown in the Typical Application Circuit. See Maxim Application Note IF Tank Design for the MAX2360 at www.maxim-ic.com for more information on designing tanks for alternate IFs. _______________________________________________________________________________________ 9 MAX2370 current consumption and linearity performance. The power-control range of the RF VGA is typically 44dB. MAX2370 Complete 450MHz Quadrature Transmitter Internal to the IC, the charge pump has a leakage of less than 10nA. This is equivalent to a 300MΩ shunt resistor. The charge-pump output must see an extremely high DC resistance of greater than 300MΩ. This minimizes charge-pump spurs at the comparison frequency. Make sure there is no solder flux under the varactor or loop filter and use low-leakage capacitors. Layout Considerations The MAX2370 EV kit can be used as a starting point for layout. For best performance, take into consideration power-supply issues as well as RF, LO, and IF layout. Power-Supply Layout To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC pin of the MAX2370. At the end of each trace is a bypass capacitor with impedance to ground less than 1Ω at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Also, connect the exposed paddle to the PC board GND with multiple vias to provide the lowest inductance ground connection possible. 10 Matching Network Layout The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and any other planes) below the matching network components can be used. Keep traces short on the high-impedance ports (e.g., IF inputs and outputs) to minimize shunt capacitance. Tank Layout Keep the traces coming out of the tank short to reduce series inductance and shunt capacitance. Keep the inductor pads and coupling capacitor pads small to minimize stray shunt capacitance. Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter 24-BIT REGISTER MAX2370 MSB LSB DATA 20 BITS ADDRESS 4 BITS B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 RFM-DIVIDE REGISTER RFR-DIVIDE REGISTER IFM-DIVIDE REGISTER IFR-DIVIDE REGISTER CONTROL REGISTER CONFIGURATION REGISTER CURRENT-CONTROL REGISTER RFM-DIVIDE RATIO (18) ADDRESS X X B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X X X X X B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 RFR-DIVIDE RATIO (13) X B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X 0 X X X X X X X B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 1 1 0 0 1 0 1 ADDRESS 0 TEST BITS (9) TEST REGISTER 1 ADDRESS CURRENT CONTROL BITS (16) X 0 ADDRESS 0 CONFIGURATION BITS (16) X 0 ADDRESS OPERATION CONTROL BITS (16) X 0 ADDRESS 0 IFR-DIVIDE RATIO (11) X 0 ADDRESS 0 IFM-DIVIDE RATIO (14) X 0 1 1 0 ADDRESS 0 1 1 1 X = DON’T CARE Figure 1. Register Configuration ______________________________________________________________________________________ 11 MAX2370 Complete 450MHz Quadrature Transmitter Table 1. Register Settings for Typical Operation REGISTER NAME TYPICAL SETTINGS REGISTER ADDRESS RFM[17:0] 23000DEC 0000b RF M-Divider Count RFR[12:0] 384DEC 0001b RF R-Divider Count IFM[13:0] 4800DEC 0010b IF M-Divider Count IFR[10:0] 384DEC 0011b IF R-Divider Count OPCTRL[15:0] 090Fhex 0100b Operational Control Settings CONFIG[15:0] D03Fhex 0101b Configuration and Setup Control ICCCTRL[15:0] 0C38hex 0110b Current Multiplication Factor, Throttle-Back Control, Modulator Bypass, Compensation for Gain Variation Over Temperature, Maximum PowerLevel Setting TEST[8:0] 100hex 0111b Test Mode Control 12 FUNCTION ______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter BIT NAME BIT LOCATION (0 = LSB) TYPICAL SETTINGS RESERVED 15 0 Reserved. Set to 0 for normal operation. RCP_TURBO1 14 0 Works with RCP_TURBO2 (in the configuration register) to set the turbo charge-pump mode (see Table 7). 0 0 = Normal operation. 1 = Sets IF charge-pump current to turbo level and keeps it there even after lock is established. This mode provides the highest charge-pump current, but effectively no turbo mode since current is already at maximum. FUNCTION ICP_MAX 13 RESERVED 12, 11 01 Reserved. Set to 01 for normal operation. RESERVED 10, 9 00 Reserved. Set to 00 for normal operation. IFG 8, 7, 6 100 3-bit gain balancing control. Increases IF gain by approximately 2dB per LSB. Provides a means for adjusting balance between RF and IF gain for optimized linearity. RESERVED 5 0 Reserved. Set to 0 for normal operation. 0 LO buffer enable. 0 = LO buffer off. 1 = LO buffer on. BUF_EN 4 MOD_TYPE 3 1 Selects type of modulation. 0 = Selects direct VCO modulation (IF VCO is directly modulated and the I/Q modulator is bypassed). 1 = Selects quadrature modulation. STBY 2 1 Standby control. 0 = Shuts down everything except the registers and serial interface. 1 = Normal operation. TXSTBY 1 1 Transmitter standby control. 0 = Shuts down the modulator and upconverter leaving PLLs locked and registers active. This bit’s functionality is equivalent to that of the TX_GATE pin. 1 = Normal operation. SHDN_BIT 0 1 Shutdown control. 0 = Shuts down everything except the serial interface. 1 = Normal operation. ______________________________________________________________________________________ 13 MAX2370 Table 2. Operation Control Register (OPCTRL, Address: 0100b) MAX2370 Complete 450MHz Quadrature Transmitter Table 3. Configuration Register (CONFIG, Address: 0101b) BIT NAME BIT LOCATION (0 = LSB) TYPICAL SETTINGS IF_PLL_SHDN 15 1 IF PLL shutdown control. 0 = Shuts down IF PLL. This mode is used with an external IF PLL. 1 = Normal operation. RF_PLL_SHDN 14 1 RF PLL shutdown control. 0 = Shuts down RF PLL. This mode is used with an external RF PLL. 1 = Normal operation. RESERVED 13 0 Reserved. Set to 0 for normal operation. IQ_LEVEL 12 1 Selects the nominal I/Q input levels. 0 = Selects 300mVP-P input mode. 1 = Selects 600mVP-P input mode. RESERVED 11, 10 00 Reserved. Set to 00 for normal operation. 00 Sets the IF charge-pump current. 00 = 139µA. 01 = 192µA. 10 = 278µA. 11 = 390µA. Sets the RF charge-pump current. 00 = 325µA. 01 = 650µA. 10 = 738µA. 11 = 1063µA. ICP 9, 8 FUNCTION RCP 7, 6 00 RESERVED 5, 4 11 Reserved. Set to 11 for normal operation. IF_TURBO_CHARGE 3 1 IF turbo-charge control. 0 = Disables extra charge-pump current during acquisition. 1 = Activates turbo-charge feature providing extra current during acquisition. RCP_TURBO2 2 1 Works with RCP_TURBO1 (in the operation control register) to set the turbo charge-pump mode (see Table 7). 11 Determines output mode for LOCK pin as defined below: 00 = Test mode. 01 = IF PLL lock detector. 10 = RF PLL lock detector. 11 = Logical AND of IF PLL and RF PLL lock detectors. LD_MODE 1, 0 Table 4. Current-Control Register (ICCCTRL, Address: 0110b) 14 BIT NAME BIT LOCATION (0 = LSB) TYPICAL SETTINGS RESERVED 15, 14, 13, 12 0000 MPL 11 1 FUNCTION Reserved. Set to 0000 for normal operation. Sets the maximum RF output power level. 0 = Sets to low-noise mode. 1 = Sets to normal power mode. RESERVED 10, 9, 8, 7 1000 Reserved. Set to 1000 for normal operation. THROTTLE_BACK 6, 5, 4 011 Controls the throttleback rate (see Table 6). I_MULT 3, 2, 1, 0 1000 Sets the current scale factor for the PA driver (see Table 5). ______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter BITS NOMINAL CURRENT SCALE FACTOR 0011 0.69 0100 0.75 0101 0.81 0110 0.88 0111 0.94 1000 (default) 1.00 1001 1.13 1010 1.25 1011 1.38 1100 1.50 BIT NAME I_MULT Table 6. Typical Throttleback Rate Set By THROTTLE_BACK Bits BIT NAME THROTTLE_BACK BITS NOMINAL RATE (dBmA/dB) 000 1.3 001 1.2 010 1.1 011 1.0 100 0.9 101 0.8 110 0.7 111 0.6 Table 7. RF Turbo Charge-Pump Current Setting RCP_TURBO1 RCP_TURBO2 0 0 No turbo current. Charge-pump current is set by RCP bits. FUNCTION 0 1 Turbo current turns on every time RF PLL is reprogrammed. Turbo current is automatically turned off after RF PLL is locked. 1 0 Turbo current is always on. 1 1 Turbo current is turned on every time RF PLL is out of lock. IDLE Pin IF VCO IF PLL Ultra-low shutdown current RF PLL SHDN Pin COMMENTS MODULATOR POWER-DOWN MODE UPCONVERTER Table 8. Power-Down Modes OFF OFF OFF OFF OFF Rx only mode OFF OFF — OFF OFF TXGATE Pin For punctured Tx mode OFF OFF — — — RF_PLL_SHDN Bit For external RF PLL use — — OFF — — — — — — OFF OFF OFF — — — IF_PLL_SHDN Bit TXSTBY Bit For external IF PLL use Tx is OFF, but IF and RF LOs stay locked ______________________________________________________________________________________ 15 MAX2370 Table 5. Typical Current Scale Factors Set By I_MULT Bits MAX2370 Complete 450MHz Quadrature Transmitter MAX2335 RX RECEIVER 3300pF 0.047µF /2 RF VCO 12kΩ 100pF 100pF VCC VCC 0.1µF VCC 0.1µF 100pF VCC 47nH 0.022µF 1000pF 100pF 20kΩ 6 IFCP VCCIFCP 37 38 39 40 RFCP VCC 41 42 43 44 45 28 Σ SPI INTERFACE 27 0° /2 90° 26 25 DI 560Ω 2pF TO 6.8pF 5.1kΩ 4.7pF 47nH 33pF IFLO VCC IFLO SHDN I- SHDN I+ 5.1kΩ DAC VCC 0.1µF I 24 23 33pF Q+ Q- 22 21 VCC 20 0.1µF VGC GC VCC 19 18 17 16 CS CLK N.C. N.C. IFOUTIFOUT+ CLK 15 12 1000pF 100nH N.C. TANK+ TANK- 29 VCC 400Ω 120MHz BPF N.C. 32 9 11 100pF 33 30 10 10kΩ N.C. N.C. 31 EP -45 CS 100pF MAX2370 19.2MHz TCXO REF 34 8 13 TXGATE N.C. N.C. RBIAS +45 7 14 100pF 0° 90° 5 IFIN+ IFIN- VCC 0.033µF 35 Σ 4 TXGATE IDLE IF PLL 3 IDLE VCC 100pF RF PLL 2 VCCDRV VCC 0.1µF 36 1 N.C. LOCK LOCK 46 N.C. GND GND LO GND RFOUT DI 51kΩ 47 48 VCC N.C. RFPLL VCCRFCP PA DUPLEXER DAC Q VCC 0.1µF 2.7pF 100nH 9.1pF 9.1pF Figure 2. MAX2370 Typical Application Circuit 16 ______________________________________________________________________________________ Complete 450MHz Quadrature Transmitter B19 (MSB) B18 B0 A3 A1 A0 (LSB) CLK tCWL tCS tCH tCWH MAX2370 DI tCS > 50ns tCH > 10ns tCWH > 50ns tES > 50ns tCWL > 50ns tEW > 50ns tES CS tEW Figure 3. 3-Wire Interface Timing Diagram ______________________________________________________________________________________ 17 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 32, 44, 48L QFN.EPS MAX2370 Complete 450MHz Quadrature Transmitter D2 D CL D/2 b D2/2 k E/2 E2/2 CL (NE-1) X e E E2 k L DETAIL A e (ND-1) X e DETAIL B e CL L L1 CL L L e e DALLAS A1 A2 SEMICONDUCTOR A PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm APPROVAL DOCUMENT CONTROL NO. 21-0144 18 ______________________________________________________________________________________ REV. D 1 2 Complete 450MHz Quadrature Transmitter DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm APPROVAL DOCUMENT CONTROL NO. 21-0144 REV. D 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX2370 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)