MAXIM MAX512CSD

19-0252; Rev 2; 5/96
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
____________________________Features
♦ Operate from a Single +5V (MAX512) or
+3V (MAX513) Supply, or from Bipolar Supplies
♦ Low Power Consumption
1mA Operating Current
<1µA Shutdown Current
♦ Unipolar or Bipolar Outputs
♦ 5MHz, 3-Wire Serial Interface
♦ SPI, QSPI, and Microwire Compatible
♦ Two Buffered, Bipolar-Output DACs (DACs A/B)
♦ Independently Programmable Shutdown Mode
♦ Space-Saving 14-Pin SO/DIP Packages
♦ Pin and Software Reset
______________Ordering Information
PART
14 Plastic DIP
MAX512CSD
MAX512C/D
0°C to +70°C
0°C to +70°C
14 SO
Dice*
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
________________Functional Diagram
DIN
1
14 LOUT
CS
2
13 I.C.
SCLK 3
MAX512
MAX513
12 REFAB
RESET 4
11 REFC
V DD
5
10 OUTC
GND
6
9
OUTB
V SS 7
8
OUTA
DIP/SO
CS
2
REFAB REFC
12
11
SCLK
3
16-BIT SHIFT REGISTER
DATA (8)
TOP VIEW
DIN
1
DAC
LATCH
A
DAC A
DAC
LATCH
B
DAC B
DAC
LATCH
C
DAC C
CONTROL (8)
__________________Pin Configuration
PIN-PACKAGE
0°C to +70°C
________________________Applications
Digital Gain and Offset Adjustment
Programmable Attenuators
Programmable Current Sources
Programmable Voltage Sources
RF Digitally Adjustable Bias Circuits
VCO Tuning
TEMP. RANGE
MAX512CPD
OUTA
8
OUTB
9
OUTC
10
MAX512
MAX513
LOUT
14
LATCH
4
RESET
5
VDD
7
VSS
6
GND
Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola Inc.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX512/MAX513
_______________General Description
The MAX512/MAX513 contain three 8-bit, voltage-output
digital-to-analog converters (DAC A, DAC B, and DAC C).
Output buffer amplifiers for DACs A and B provide voltage
outputs while reducing external component count. The
output buffer for DAC A can source or sink 5mA to within
0.5V of VDD or VSS. The buffer for DAC B can source or
sink 0.5mA to within 0.5V of V DD or V SS . DAC C is
unbuffered, providing a third voltage output with increased
accuracy. The MAX512 operates with a single
+5V ±10% supply, and the MAX513 operates with a
+2.7V to +3.6V supply. Both devices can also operate
with split supplies.
The 3-wire serial interface has a maximum operating frequency of 5MHz and is compatible with SPI™, QSPI™,
and Microwire™. The serial input shift register is 16 bits
long and consists of 8 bits of DAC input data and 8 bits
for DAC selection and shutdown. DAC registers can be
loaded
–—– independently or in parallel at the positive edge
of CS. A latched logic output is also available for auxiliary control.
Ultra-low power consumption and small packages
(14-pin DIP/SO) make the MAX512/MAX513 ideal for
portable and battery-powered applications. Supply current is only 1mA, dropping to less than 1µA in shutdown.
Any of the three DACs can be independently shut down.
In shutdown mode, the DAC's R-2R ladder network is
disconnected from the reference input, minimizing system power consumption.
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................ -0.3V, +6V
VSS to GND................................................................. -6V, +0.3V
VDD to VSS ................................................................ -0.3V, +12V
Digital Inputs and Outputs to GND............... -0.3V, (VDD + 0.3V)
REFAB ................................................ (VSS - 0.3V), (VDD + 0.3V)
OUTA, OUTB (Note 1) ....................................................VSS, VDD
OUTC.............................................................-0.3V, (VDD + 0.3V)
REFC..............................................................-0.3V, (VDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.00mW/°C above +70°C) ............800mW
SO (derate 8.33mW/°C above +70°C) ...........................667mW
CERDIP (derate 9.09mW/°C above +70°C) ...................727mW
Operating Temperature Ranges
MAX51_C_ _ .........................................................0°C to +70°C
MAX51_E_ _.......................................................-40°C to +85°C
MAX51_MJD ....................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1: The outputs may be shorted to VDD, VSS, or GND if the package power dissipation is not exceeded. Typical short-circuit current to GND is 50mA.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V DD = +4.5V to +5.5V for MAX512, V DD = +2.7V to +3.6V for MAX513, V SS = GND = 0V, REFAB = REFC = V DD ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±1
LSB
STATIC PERFORMANCE
Resolution
N
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Total Unadjusted Error
TUE
Zero-Code Temperature
Coefficient
Power-Supply Rejection Ratio
8
DAC A/B (Note 2)
±1.5
DAC C
±1
(Note 2)
±1
DAC A/B
100
DAC C
PSRR
Bits
Guaranteed monotonic
LSB
µV/°C
5
MAX512, 4.5V ≤ VDD ≤ 5.5V,
REFAB = REFC = 4.096V
0.01
MAX513, 2.7V ≤ VDD ≤ 3.6V,
REFAB = REFC = 2.4V
0.015
LSB
LSB
%/%
REFERENCE INPUTS
Reference Input Voltage Range
REFAB
VSS
VDD
REFC
GND
VDD
Reference Input Capacitance
Reference Input Resistance
Reference Input Resistance
(shutdown mode)
2
25
RREF
REFAB (Note 3)
8
REFC (Note 3)
12
REFAB, REFC
V
pF
kΩ
2
_______________________________________________________________________________________
MΩ
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
(V DD = +4.5V to +5.5V for MAX512, V DD = +2.7V to +3.6V for MAX513, V SS = GND = 0V, REFAB = REFC = V DD ,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REF_
V
DAC OUTPUTS
Output Voltage Range
0
Capacitive Load
Output Resistance
DAC A
0.10
DAC B
0.01
DAC C
0
µF
DAC A
0.050
DAC B
0.500
DAC C
24
kΩ
DIGITAL INPUTS
Input High Voltage
VIH
Input Low Voltage
VIL
(0.7)(VDD)
Input Current
IIN
VIN = 0V or VDD
Input Capacitance
CIN
(Notes 4, 5)
Output High Voltage
VOH
ISOURCE ≤ 1.6mA
Output Low Voltage
VOL
ISINK ≤ 1.6mA
SR
CL = 0.1µF (DAC A), CL = 0.01µF (DAC B)
V
(0.3)(VDD)
0.1
V
±10
µA
10
pF
DIGITAL OUTPUT
VDD - 0.4
V
0.4
V
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
To ±1⁄2LSB
Voltage-Output Settling Time
Digital Feedthrough and Crosstalk
0.1
CL = 0.1µF (DAC A)
70
CL = 0.01µF (DAC B)
70
CL = 0.1nF (DAC C)
35
All 0s to all 1s
V/µs
µs
10
nV-s
POWER SUPPLIES
MAX512
4.5
5.5
MAX513
2.7
3.6
MAX512
-5.5
-4.5
MAX513
-3.6
-2.7
Positive Supply Voltage Range
VDD
Negative Supply Voltage Range
(Note 6)
VSS
Positive Supply Current
IDD
All inputs = 0V
Negative Supply Current
ISS
All inputs = 0V, VSS = -5.5V
Shutdown Supply Current
MAX512 (VDD = 5.5V)
1.3
2.8
MAX513 (VDD = 3.6V)
0.9
2.5
V
V
mA
-1.3
mA
0.1
µA
Note 2: Digital code from 24 through 232 are due to swing limitations of output amplifiers on DAC A and DAC B. See Typical
Operating Characteristics.
Note 3: Reference input resistance is code dependent. The lowest input resistance occurs at code 55hex. Refer to the reference
input section in the Detailed Description.
Note 4: Guaranteed by design. Not production tested.
Note 5: Input capacitance is code dependent. The highest capacitance occurs at code 00hex.
Note 6: For single-supply mode, tie VSS to GND.
_______________________________________________________________________________________
3
MAX512/MAX513
ELECTRICAL CHARACTERISTICS (continued)
TIMING CHARACTERISTICS (Note 4)
(VDD = +4.5V to +5.5V for MAX512, VDD = +2.7V to +3.6V for MAX513, VSS = GND = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
SERIAL INTERFACE TIMING
–—–
CS Fall to SCLK Rise Setup Time
–—–
SCLK Rise to CS Rise Setup Time
CONDITIONS
MIN
TYP
UNITS
MAX
tCSS
150
ns
tCSH
150
ns
DIN to SCLK Rise Setup Time
tDS
50
ns
DIN to SCLK Rise Hold Time
tDH
50
ns
SCLK Pulse Width High
tCH
100
ns
SCLK Pulse Width Low
tCL
100
Output Delay LOUT
–—–
CS Pulse Width High
tOD
ns
CL = 100pF
150
tCSPWH
ns
200
ns
Note 4: Guaranteed by design. Not production tested.
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
1.5
1
VDD = 3V, VSS = GND = 0V
REFAB = VDD
CODE = ALL 1s
0.5
0
0.0001 0.001 0.01
0.1
10
DAC B
4.4
4.2
4.0
1
VDD = 5V, VSS = GND = 0V
REFAB = VDD
CODE = ALL 1s
3.8
0.0001 0.001 0.01
100
OUTPUT SOURCE CURRENT (mA)
8
1
10
0
DAC A LOADED WITH 5mA
DAC B NO LOAD
0
DAC C NO LOAD
-2
0
32
64
96 128 160 192 224 255
DIGITAL CODE
4
1.5
1.4
10
-20
REFAB = REFC = VDD
ALL LOGIC INPUTS GROUNDED
1.3
DAC B LOADED WITH 0.5mA
DAC B LOADED WITH 0.5mA
DAC A NO LOAD
1
MAX512 TOC-03
100
POSITIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
IDD (mA)
DAC A LOADED WITH 5mA
0.1
OUTPUT SINK CURRENT (mA)
-15
2
300
200
0
0.0001 0.001 0.01
100
TUE (LSB)
6
4
DAC B
400
100
-5
-10
DAC A
600
500
TOTAL UNADJUSTED ERROR
vs. DIGITAL CODE (Single Supply)
MAX512 TOC-04
10
VDD = +3V, VSS = -3V
REFAB = VSS, REFC = VDD
CODE = ALL 1s
0.1
VDD = 3V, VSS = GND = 0V
800 REFAB = VDD
CODE = ALL 1s
700
OUTPUT SOURCE CURRENT (mA)
TOTAL UNADJUSTED ERROR
vs. DIGITAL CODE (Dual Supplies)
12
MAX512 TOC-02
4.8
4.6
900
OUTPUT VOLTAGE (mV)
DAC B
2
OUTPUT VOLTAGE vs.
OUTPUT SINK CURRENT
MAX512 TOC-05
OUTPUT VOLTAGE (V)
2.5
DAC A
5.0
OUTPUT VOLTAGE (V)
DAC A
3
5.2
MAX512 TOC-01
3.5
OUTPUT VOLTAGE vs.
OUTPUT SOURCE CURRENT (VDD = 5V)
MAX512 TOC-06
OUTPUT VOLTAGE vs.
OUTPUT SOURCE CURRENT (VDD = 3V)
TUE (LSB)
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage Output DACs
with Serial Interface
1.1
1.0
0.9
0.8
-25
0.7
-30
VDD = 3V, VSS = GND = 0V
REFAB = 3V
-35
0
32
64
96
128
160 192 224 255
DIGITAL CODE
0.6
0.5
2.5
3.0
3.5
4.0
VDD (V)
_______________________________________________________________________________________
4.5
5.0
5.5
Low-Cost, Triple, 8-Bit Voltage Output DACs
with Serial Interface
REFC GROUNDED FOR REF_ < 0
CODE = ALL 1s
ISS, VDD = 3V, VSS = -3V
-0.5
-1.0
1.340
-3
-2
-1
1
0
3
2
3.0
2.5
2.0
1.5
1.0
0.5
20 40 60 80 100 120 140
-60 -40 -20 0
20 40 60 80 100 120 140
REFAB = REFC (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
REFERENCE FEEDTHROUGH
vs. FREQUENCY
REFERENCE LARGE-SIGNAL
FREQUENCY RESPONSE
REFERENCE SMALL-SIGNAL
FREQUENCY RESPONSE
-40
DAC C
-60
-80
DAC A, B
0
-5
-10
-15
-20
-100
-120
0.1
1
10
FREQUENCY (kHz)
100
1000
MAX512 TOC-11
5
MAX512 TOC-10
VDD = 3V, VSS = GND = 0V
REF_ FROM 0V TO 2.9V
NO LOAD
CODE = ALL 0s
0.01
3.5
VDD = +5V, VSS = GND = 0V
REFAB = REFC = VDD
ALL LOGIC INPUTS = +5V
0
-60 -40 -20 0
4
0
RELATIVE OUTPUT (dB)
FEEDTHROUGH (dB)
VDD = +5V, VSS = GND = 0V
REFAB = REFC = VDD
ALL LOGIC INPUTS = +5V
ALL DACs SET TO ALL 1s
1.345
ISS, VDD = 5V, VSS = -5V
-5 -4
-20
MAX512 TOC-08
1.350
-1.5
0
1.355
4.0
-25
0.001
0.01
0.1
1
DAC B
-40
-80
10
FREQUENCY (kHz)
100
1000
DAC A
DAC C
-20
-60
VDD = 3V, VSS = GND = 0V
REFAB, REFC
SINE WAVE 0V TO VDD
MAX512 TOC-12
IDD, VDD = 3V, VSS = -3V
RELATIVE OUTPUT (dB)
0
1.360
IDD (mA)
ISUPPLY (mA)
0.5
1.365
4.5
SHUTDOWN SUPPLY CURRENT (µA)
IDD, VDD = 5V, VSS = -5V
1.0
1.370
MAX512 TOC-07
1.5
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX512 TOC-09
POSITIVE SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
VDD = 3V, VSS = GND = 0V
REFAB, REFC
SINE WAVE ±40mV
0.1k
1k
10k
100k
1M
10M
FREQUENCY (Hz)
_______________________________________________________________________________________
5
MAX512/MAX513
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage Output DACs
with Serial Interface
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
LINE-TRANSIENT RESPONSE (OUTC)
LINE-TRANSIENT RESPONSE (OUTA)
3.14V
3.14V
A
A
2.86V
2.86V
B
B
20µs/div
20µs/div
REFC = 2.56V, NO LOAD, CODE = ALL 1s
REFAB = 2.56V, NO LOAD, CODE = ALL 1s
A : VDD, 100mV/div
B : OUTA, 500µV/div
A : VDD, 100mV/div
B : OUTC, 2mV/div
CLOCK FEEDTHROUGH (OUTA)
CLOCK FEEDTHROUGH (OUTC)
A
A
B
B
1µs/div
1µs/div
6
VSS = 0V, CS = HIGH
VSS = 0V, CS = HIGH
A: SCLK, 333kHz, 0V TO 2.9V, 2V/div
B: OUTA, 2mV/div
A: SCLK, 333kHz, 0V TO 2.9V, 2V/div
B: OUTC, 2mV/div
_______________________________________________________________________________________
Low-Cost, Triple, 8-Bit Voltage Output DACs
with Serial Interface
POSITIVE SETTLING TIME (DAC A)
POSITIVE SETTLING TIME (DAC B)
A
A
B
B
20µs/div
20µs/div
VDD = 3V, VSS = 0V, REFAB = VDD, RL = 1k Ω, CL = 0.1µF
ALL BITS OFF TO ALL BITS ON
VDD = 3V, VSS = 0V, REFAB = VDD, RL = 10k Ω, CL = 0.01µF
ALL BITS OFF TO ALL BITS ON
A: CS, 2V/div
B: OUTA, 20mV/div
A: CS, 2V/div
B: OUTB, 20mV/div
POSITIVE SETTLING TIME (DAC C)
POSITIVE SETTLING TIME WITH DUAL SUPPLIES
A
A
B
B
10µs/div
10µs/div
VDD = 3V, VSS = 0V, REFC = VDD, RL = ∞, CL = 122pF
ALL BITS OFF TO ALL BITS ON
VDD = 5V, VSS = -5V, REFAB = 2.56V, RL = 1k Ω, CL = 0.1µF
ALL BITS OFF TO ALL BITS ON
A: CS, 2V/div
B: OUTC, 20mV/div
A: CS, 5V/div
B: OUTA, 10mV/div
_______________________________________________________________________________________
7
MAX512/MAX513
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
_____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
TIME EXITING SHUTDOWN MODE
OUTPUT VOLTAGE NOISE DC TO 1MHz
A
OUTA,
200µV/div
B
20µs/div
2ms/div
VDD = 3V, VSS = 0V, REFAB = VDD, RL = 1k Ω, CL = 0.1µF
DAC LOADED WITH ALL 1s
DIGITAL CODE = 80, REFAB = VDD, NO LOAD
A: CS, 2V/div
B: OUTA, 1V/div
______________________________________________________________Pin Description
8
PIN
NAME
FUNCTION
1
DIN
Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.
2
–—–
CS
Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands
–—–
are executed at the rising edge of C S.
3
SCLK
4
–————–
RESET
Serial Clock Input. Data is clocked in on the rising edge of SCLK.
Asynchronous reset input (active low). Clears all registers to their default state (FFhex for DAC A and
DAC B registers); all other registers are reset to 0 (including the input shift register).
5
VDD
Positive Power Supply (2.7V to 5.5V). Bypass with 0.22µF to GND.
6
GND
Ground
7
VSS
Negative Power Supply 0V or (-1.5V to -5.5V). Tie to GND for single supply operation. If a negative supply
is applied, bypass with 0.22µF to GND.
8
OUTA
DAC A Output Voltage (Buffered). Resets to full scale. Connect 0.1µF capacitor or greater to GND.
9
OUTB
DAC B Output Voltage (Buffered). Resets to full scale. Connect 0.01µF capacitor or greater to GND.
10
OUTC
DAC C Output Voltage (Unbuffered). Resets to zero.
11
REFC
DAC C Reference Voltage
12
REFAB
13
I.C.
14
LOUT
DAC A/B Reference Voltage
Internally connected. Do not make connections to this pin.
Logic Output (latched)
_______________________________________________________________________________________
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
MAX512/MAX513
_______________Detailed Description
Analog Section
The MAX512/MAX513 contain three 8-bit, voltage-output, digital-to-analog converters (DACs). The DACs are
“inverted” R-2R ladder networks using complementary
switches that convert 8-bit digital inputs into equivalent
analog output voltages in proportion to the applied reference voltages.
The MAX512/MAX513 have two reference inputs: one is
shared by DAC A and DAC B and the other is used by
DAC C. These inputs allow different full-scale output
voltages and different output voltage polarities for the
DAC pair A/B and DAC C.
The MAX512/MAX513 include output buffer amplifiers
for DACs A and B and input logic for simple microprocessor (µP) and CMOS interfaces.
The MAX512/MAX513 operate in either single-supply or
dual-supply mode, as determined by VSS. If VSS is within approximately -0.5V of GND, single-supply mode is
assumed. If VSS is below -1.5V, the devices are in dualsupply mode.
Reference Inputs and DAC Output Range
The voltage at REF_ sets the full-scale output of the
DACs. The input impedance of the REF_ inputs is code
dependent. The lowest value, approximately 12kΩ for
REFC (8kΩ for REFAB), occurs when the input code is
01010101 (55hex). The maximum value of infinity
occurs when the input code is zero.
In shutdown mode, the selected DAC output is set to
zero while the value stored in the DAC register remains
unchanged. This removes the load from the reference
input to save power. Bringing the MAX512/MAX513 out
of shutdown mode restores the DAC output voltage.
Because the input resistance at REF_ is code dependent, the DAC’s reference sources should have an output impedance of no more than 5Ω. The input capacitance at the REF_ pins is also code dependent and
typically does not exceed 25pF.
The reference voltage on REFAB can range anywhere
between the supply rails. In dual-supply mode, a positive reference input voltage on REFAB should be less
than (VDD - 1.5V) to avoid saturating the buffer amplifiers. The reference voltage includes the negative supply rail. See the Output Buffer Amplifier section for more
information. The REFC input accepts positive voltages
up to VDD and should not be forced below ground.
The absolute difference between any reference voltage
and GND should not exceed 6V.
R
2R
2R
R
2R
R
2R
OUT
2R
REF
GND
SHOWN FOR ALL 1s ON DAC; DAC C IS NOT BUFFERED
Figure 1. DAC Simplified Circuit Diagram
Output Buffer Amplifiers (DAC A / DAC B)
DAC A and DAC B voltage outputs are internally
buffered. The buffer amplifiers have a rail-to-rail
(VSS to VDD) output voltage range.
In single-supply mode, the DAC outputs A and B are
internally divided by two and the buffer is set to a gain
of two, eliminating the need for a buffer input voltage
range to the positive supply rail.
In dual-supply mode, the DAC outputs are not attenuated and the buffer is set to unity gain.
Although only necessary for negative output voltages,
the dual-supply mode may be used even if the desired
DAC output voltage is positive. Possible errors associated with the divide-by-two attenuator and gain-of-two
buffers in single-supply mode are eliminated in dualsupply mode. In this case, do not use reference voltages higher than (VDD - 1.5V).
DAC A’s output amplifier can source and sink up to 5mA
of current (0.5mA for DAC B buffer). See the Total
Unadjusted Error vs. Digital Code graph in the Typical
Operating Characteristics for dual and single supplies.
The amplifier is unity-gain stable with a capacitive load of
0.05µF (0.01µF for DAC B buffer) or greater. The slew
rate is limited by the load capacitor and is typically
0.1V/µs with a 0.1µF load (0.01µF for DAC B buffer).
Unbuffered Output (DAC C)
The output of DAC C is unbuffered and has a typical output impedance of 24kΩ. It can be used to drive a highimpedance load, such as an op amp or comparator, and
has 35µs typical settling time to 1/2LSB with a single 3V
supply. Use DAC C if a quick dynamic response is
required.
_______________________________________________________________________________________
9
Reset
–————–
–—
———–
The RESET input is active low. When asserted (RESET
= 0), DACs A and B are set to full scale (FFhex) and
active, while DAC C is set to zero code (00hex) and
active. The 16-bit serial register is cleared to 0000hex.
LOUT is reset to zero.
Table 1. Input Shift Register
DATA BITS
Shutdown Mode
When programmed to shutdown mode, the outputs of
DAC A and B go into a high-impedance state. Virtually
no current flows into or out of the buffer amplifiers in
that state. The output of DAC C goes to 0V when shut
down. In shutdown mode, the REF_ inputs are high
impedance (2MΩ typ) to conserve current drain from
the system reference; therefore, the system reference
does not have to be powered down. The logic output
LOUT remains active in shutdown.
Coming out of shutdown, the DAC outputs return to the
values kept in the registers. The recovery time is equivalent to the DAC settling time.
CONTROL BITS
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
Serial Interface
–—–
An active-low chip select (CS) enables the shift register
to receive data from the serial data input. Data is
clocked into the shift register on every rising edge of
the serial clock signal (SCLK). The clock frequency can
be as high as 5MHz.
Data is sent MSB first and can be transmitted in one
16-bit word.
–—–The write cycle can be interrupted at any
time when CS is kept active (low) to allow, for example,
two 8-bit-wide transfers. After clocking all 16 bits into
B0*
DAC Data Bit 0 (LSB)
B1
DAC Data Bit 1
B2
DAC Data Bit 2
B3
DAC Data Bit 3
B4
DAC Data Bit 4
B5
DAC Data Bit 5
B6
DAC Data Bit 6
B7
DAC Data Bit 7 (MSB)
LA
Load Reg DAC A, Active High
LB
Load Reg DAC B, Active High
LC
Load Reg DAC C, Active High
SA
Shut Down DAC A, Active High
SB
Shut Down DAC B, Active High
SC
Shut Down DAC C, Active High
Q1
Logic Output
Q2**
Uncommitted Bit
**Clocked in last.
**Clocked in first.
–—–
the input shift register, the rising edge of CS updates
the DAC outputs, the shutdown status, and the status of
the logic output. Because of their single buffered structure, DACs cannot be simultaneously updated to different digital values.
CS
INSTRUCTION
EXECUTED
SCLK
OPTIONAL
SDIN
Q2
Q1
SC
SB
SA
LC
LB
LA
(CONTROL BYTE)
D7
D6
D5
D4
D3
D2
D1
D0
(DATA BYTE)
Figure 2. MAX512/MAX513 3-Wire Serial-Interface Timing Diagram
10
______________________________________________________________________________________
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
MAX512/MAX513
Table 2. Serial-Interface Programming Commands
CONTROL
DATA
FUNCTION
MSB
LSB
Q2
Q1
SC
SB
SA
LC
LB
LA
B7
B6
B5
B4
B3
B2
B1
B0
*
*
*
*
*
0
0
0
X
X
X
X
X
X
X
X
*
*
*
*
*
1
0
0
8-Bit DAC Data
Load Register to DAC C
*
*
*
*
*
0
1
0
8-Bit DAC Data
Load Register to DAC B
*
*
*
*
*
0
0
1
8-Bit DAC Data
Load Register to DAC A
*
*
*
*
*
1
1
1
8-Bit DAC Data
*
*
0
0
0
*
*
*
X
X
X
X
X
X
X
X
All DACs Active
*
*
1
0
0
*
*
*
X
X
X
X
X
X
X
X
Shut Down DAC C
*
*
0
1
0
*
*
*
X
X
X
X
X
X
X
X
Shut Down DAC B
*
*
0
0
1
*
*
*
X
X
X
X
X
X
X
X
Shut Down DAC A
*
*
1
1
1
*
*
*
X
X
X
X
X
X
X
X
Shut Down All DACs
X
0
*
*
*
*
*
*
X
X
X
X
X
X
X
X
Reset LOUT
X
1
*
*
*
*
*
*
X
X
X
X
X
X
X
X
Set LOUT
No Operation to DAC Registers
Load All DAC Registers
Don’t care.
Not shown for clarity. The functions of loading and shutting down the DACs and programming the logic can be combined in a single command.
X
*
Serial-Input Data Format and Control Codes
Table 2 lists the serial-input data format. The 16-bit
input word consists of an 8-bit control byte and an 8-bit
data byte. The 8-bit control byte is not decoded internally. Every control bit performs one function. Data is
clocked in starting with Q2 (uncommitted bit), followed
by the remaining control bits and the data byte. The
LSB of the data byte (B0) is the last bit clocked into the
shift register (Figure 2).
Example of a 16-bit input word:
Loaded
in First
Loaded
in Last
Q2 Q1 SC SB SA LC LB LA B7 B6 B5 B4 B3 B2 B1 B0
X
0
1
0
0
0
1
1
1
0
0
0
0
0
0
0
The example above performs the following functions:
• 80hex (128 decimal) loaded into DAC registers
A and B.
• Content of the DAC C register remains unchanged.
• DAC A and DAC B are active.
• DAC C is shut down.
• LOUT is reset to 0.
Digital Inputs
The digital inputs are compatible with CMOS logic.
Supply current increases slightly when toggling the
logic inputs through the transition zone between
(0.3)(VDD) and (0.7)(VDD).
Digital Output
The latched digital output (LOUT) has a 1.6mA source
capability while maintaining a (VDD - 0.4V) output level.
With a 1.6mA sink current, the output voltage is guaranteed to be no more than 0.4V. The output can be used
for digital auxiliary control. Please note that the digital
output remains fully active during shutdown mode.
Microprocessor Interfacing
The MAX512/MAX513 serial interface is compatible with
Microwire, SPI, and QSPI. For SPI and QSPI, clear the
CPOL and CPHA bits (CPOL = 0 and CPHA = 0).
CPOL = 0 sets the inactive state of clock to zero and
CPHA = 0 changes data at the falling edge of SCLK.
This setting allows both SPI and QSPI to run at full clock
speeds (0.5MHz and 4MHz, respectively). If a serial port
is not available on your µP, three bits of a parallel port
can be used to emulate a serial port by bit manipulation.
Minimize digital feedthrough at the voltage outputs by
operating the serial clock only when necessary.
______________________________________________________________________________________
11
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
CS
tCSPWH
tCSS
tCSH
tCH
SCLK
tCL
tDS
tDH
DIN
tOD
LOUT
Figure 3. MAX512/MAX513 Detailed Serial-Interface Timing Diagram
_____________
Applications Information
Power-Supply and Reference
Operating Ranges
The MAX512 is fully specified to operate with
VDD = 5V ±10% and VSS = GND = 0V. The MAX513 is
specified for single-supply operation with VDD ranging from
2.7V to 3.6V, covering all commonly used supply voltages
in 3V systems. The MAX512/MAX513 can also be used
with a negative supply ranging from -1.5V to -5.5V. Using a
negative supply typically improves zero-code error and
settling time (as shown in the Typical Operating
Characteristics graphs).
The two separate reference inputs for the DAC pair A/B
and the unbuffered output C allow different full-scale output voltages and, if a negative supply is used, also allow
different polarity. In dual-supply mode, REFAB can vary
from VSS to (VDD - 1.5V). In single-supply mode, the
specified range for REFAB is 0V to VDD. REFC can range
from GND to VDD. Do not force REFC below ground.
Power-supply sequencing is not critical. If a negative supply is used, make sure VSS is never more than 0.3V above
ground. Do not apply signals to the digital inputs until the
device is powered-up. If this is not possible, add currentlimiting resistors to the digital inputs.
12
Power-Supply Bypassing and
Ground Management
In single-supply operation (VSS = GND), GND and VSS
should be connected to the highest quality ground
available. Bypass VDD with a 0.1µF to 0.22µF capacitor
to GND. For dual-supply operation, bypass VSS with a
0.1µF to 0.22µF capacitor to GND. Reference inputs
can be used without bypassing. For optimum line/loadtransient response and noise performance, bypass the
reference inputs with 0.1µF to 4.7µF to GND. Careful
PC board layout minimizes crosstalk among DAC outputs, reference inputs, and digital inputs. Separate analog lines with ground traces between them. Make sure
that high-frequency digital lines are not routed in parallel to analog lines.
Unipolar Output
With unipolar output, the output voltage and the reference voltage are the same polarity. The MAX512/
MAX513 can be used with a single supply if the reference voltages are positive. With a negative supply,
the REFAB voltage can vary from V SS to
approximately (VDD - 1.5V), allowing two-quadrant multiplication.
______________________________________________________________________________________
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
DAC CONTENTS
ANALOG
OUTPUT
B7 B6 B5 B4 B3 B2 B1 B0
MAX512/MAX513
Table 3. Unipolar Code Table
Table 4. Bipolar Code Table
DAC CONTENTS
ANALOG
OUTPUT
B7 B6 B5 B4 B3 B2 B1 B0
1
1
1
1
1
1
1
1
 255 
+REF_ × 

 256 
1
1
1
1
1
1
1
1
 127 
+REF_ × 

 128 
1
0
0
0
0
0
0
1
 129 
+REF_ × 

 256 
1
0
0
0
0
0
0
1
 1 
+REF_ × 

 128 
0
0
0
0
0
0
0
0V
0
0
0
0
0
0
0
 128 
REF_
+REF_ × 
 = +
2
 256 
1
1
0
1
1
1
1
1
1
1
 1 
−REF_ × 

 128 
1
 127 
+REF_ × 

 256 
0
0
0
0
0
0
0
1
 127 
−REF_ × 

 128 
0
0
0
0
0
0
0
0
 128 
−REF_ × 
 = − REF_
 128 
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
 1 
+REF_ × 

 256 
0V
Note :
Note :
1LSB = REF_ × 2
−8
 1 
1LSB = REF_ × 2 −(8 - 1) = REF_ × 

 128 
 1 
= REF_ × 

 256 
 D

− 1
ANALOG OUTPUT = REF_ × 
 128

 D 
ANALOG OUTPUT = REF_ × 

 256 
Bipolar Output
RF Applications
Using Figure 4’s circuit, the MAX512/MAX13 can be configured for bipolar outputs. Table 4 lists the bipolar codes
and corresponding output voltages. There are two ways to
achieve rail-to-rail outputs: 1) Operate the
MAX512/MAX513 with a single supply and positive reference voltages or 2) Use dual supplies with a positive or
negative voltage at REFAB and a positive voltage at REFC.
In either case, the op amps need dual supplies. When
using the dual-supply mode, possible errors associated
with the divide-by-two attenuator and gain-of-two buffer are
eliminated (see the Output Buffer Amplifier section). For
maximum output swing of all outputs in dual-supply mode,
connect REFAB to VSS and REFC to VDD. In single-supply
mode, connect REFAB, REFC, and VDD together.
With dual supplies, DACs A and B can perform fourquadrant multiplication. Please note that in dual-supply
mode, the REFAB input ranges from VSS to (V DD 1.5V). Because REFC accepts only positive inputs,
DAC C performs two-quadrant multiplication.
Figure 4 shows Maxim’s ICL7612A with rail-to-rail input
common-mode range and rail-to-rail output voltage
swing—ideal for a high output voltage swing from low
supply voltages.
Both the MAX512 and MAX513 can bias GaAs FETs,
where the gate of the FETs must be negatively biased
to ensure that there is no drain current. In a typical
application, power to the RF amplifiers should not be
turned on until the bias voltages provided by DAC A
and DAC B are fully established; likewise, the supply
should be turned off before the bias voltage is switched
off. Figure 5 shows how DAC B supplies the negative
bias VGG1 for the driver stage and DAC A provides the
negative bias VGG2 for the output stage [1].
The DAC A and DAC B outputs are also ideal for controlling VCOs in mobile radios or cellular phones. Other
applications include varactor and PIN diode circuits.
The unbuffered DAC C provides a span within GND
and VDD and is individually set at REF C. DAC C typically adjusts offset and gain in the system.
1 [John Wachsmann. “A High-Efficiency GaAs MMIC Power Amplifier for
1.9GHz PCS Applications,” Proceedings of the First Annual Wireless
Symposium, pp. 375, Penton Publishing, Jan. 1993.]
______________________________________________________________________________________
13
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
REFAB
VDD
REFC
DIN
1
R*
CS
2
12
SCLK
3
DAC
LATCH
A
16-BIT SHIFT REGISTER
CONTROL (8)
DATA (8)
R*
11
8
OUTA
DAC A
DAC
LATCH
B
DAC B
DAC
LATCH
C
DAC C
0.05µF
0.1µF
VSS
R*
9
OUTB
0.1µF
VDD
0.1µF
10
OUTC
0.1µF
14
LATCH
5
VSS
7
VDD
VSS
0.22µF
VOUT
ICL7612A**
MAX512
MAX513
VDD
VOUT
ICL7612A**
R*
RESET
4
0.1µF
LOUT
VSS
GND
6
0.22µF
* R IN 10kΩ RANGE
** CONNECT PIN 8 TO GND
Figure 4. Bipolar Output Circuit
VDD1
REFAB = -4.2V
VDD2
RFIN
MAX512
MAX513
RFOUT
VGG1
VGG2
OUTB
DAC B
0.01µF
OUTA
DAC A
0.05µF
Figure 5. RF Bias Circuit
14
______________________________________________________________________________________
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
PART
TEMP. RANGE
___________________Chip Topography
PIN-PACKAGE
MAX512EPD
-40°C to +85°C
14 Plastic DIP
MAX512ESD
MAX512MJD
MAX513CPD
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
14 SO
14 CERDIP
14 Plastic DIP
MAX513CSD
MAX513C/D
MAX513EPD
MAX513ESD
MAX513MJD
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
14 SO
Dice*
14 Plastic DIP
14 SO
14 CERDIP
OUTC OUTB
OUTA V SS GND
V DD
REFC
REFAB
0.122"
(3.099mm)
* Contact factory for dice specifications.
RESET
SCLK
LOUT
DIN
CS
0.081"
(2.057mm)
TRANSISTOR COUNT: 1910
SUBSTRATE CONNECTED TO VDD
______________________________________________________________________________________
15
MAX512/MAX513
_Ordering Information (continued)
MAX512/MAX513
Low-Cost, Triple, 8-Bit Voltage-Output DACs
with Serial Interface
________________________________________________________Package Information
DIM
D1
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e
eA
eB
L
α
E
E1
D
A3
A A2
L A1
INCHES
MAX
MIN
0.200
–
–
0.015
0.150
0.125
0.080
0.055
0.022
0.016
0.065
0.050
0.012
0.008
0.765
0.735
0.080
0.050
0.325
0.300
0.280
0.240
0.100 BSC
0.300 BSC
0.400
–
0.150
0.115
15˚
0˚
MILLIMETERS
MIN
MAX
–
5.08
0.38
–
3.18
3.81
1.40
2.03
0.41
0.56
1.27
1.65
0.20
0.30
18.67
19.43
1.27
2.03
7.62
8.26
6.10
7.11
2.54 BSC
7.62 BSC
–
10.16
2.92
3.81
0˚
15˚
21-330A
α
14-PIN PLASTIC
DUAL-IN-LINE
PACKAGE
C
e
B1
eA
B
eB
DIM
E
A
A1
B
C
D
E
e
H
h
L
α
H
INCHES
MAX
MIN
0.069
0.053
0.010
0.004
0.019
0.014
0.010
0.007
0.344
0.337
0.157
0.150
0.050 BSC
0.244
0.228
0.020
0.010
0.050
0.016
8˚
0˚
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.27
0˚
8˚
21-331A
h x 45˚
D
α
A
0.127mm
0.004in.
e
B
A1
C
L
14-PIN PLASTIC
SMALL-OUTLINE
PACKAGE
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.