Sample & Buy Product Folder Support & Community Tools & Software Technical Documents ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 Low-Power, Low-Noise, 24-Bit, Analog-to-Digital Converter for Small-Signal Sensors FEATURES DESCRIPTION • The ADS1220 is a precision, 24-bit, analog-to-digital converter (ADC) offered in a leadless QFN-16 or a TSSOP-16 package. The device features two differential or four single-ended inputs through a very flexible input multiplexer (mux), a low-noise, programmable gain amplifier (PGA), two programmable excitation current sources, an internal reference, an oscillator, a low-side bridge switch, and a precision temperature sensor. The many integrated features and the simple control of the ADS1220 through an SPI-compatible interface ease precision measurements of the most common sensor signals. 1 23 • • • • • • • • • • • • Low Current Consumption: – Duty-Cycle Mode: 120 μA – Normal Mode: 415 μA Wide Supply Range: 2.3 V to 5.5 V Programmable Gain: 1 V/V to 128 V/V Programmable Data Rates: Up to 2 kSPS 50-Hz and 60-Hz Rejection at 20 SPS Low-Noise PGA: 90 nVRMS at 20 SPS Dual Matched Programmable Current Sources: 10 μA to 1500 μA Internal Temperature Sensor: 0.5°C Error (max) Low-Drift Internal Reference Low-Drift Internal Oscillator Two Differential or Four Single-Ended Inputs SPI™-Compatible Interface 3,5 mm × 3,5 mm × 0,9 mm QFN Package APPLICATIONS • • • • Temperature Sensors: – Thermocouples – Resistance Temperature Detectors (RTDs) – 2-, 3-, and 4-Wire RTD Excitation Bridge Sensors Portable Instrumentation Factory Automation and Process Control The device can perform conversions at data rates of up to 2000 samples-per-second (SPS) with singlecycle settling. The internal PGA offers gains of up to 128 V/V. This PGA makes the ADS1220 ideallysuited for applications measuring small signals, such as thermocouples, resistance temperature detectors (RTDs), thermistors, and bridge sensors. The device supports true bipolar analog supplies in the event that single-ended signals referenced to ground must be measured using the PGA. Alternatively, the device can be configured to bypass the internal PGA while still providing gains of up to 4 V/V, allowing for rail-torail input signals with no loss of signal integrity when running from a single analog supply. The device operates in either duty-cycle mode (consuming 120 µA of current), normal mode (consuming 415 µA of current), or turbo mode (for highest data rates). The ADS1220 operates over a temperature range of –40°C to +125°C. REFP0 AVDD REFN0 DVDD 10 A to 1.5 mA Internal Reference AIN0/REFP1 Reference Mux Device 24-bit ûADC Digital Filter and SPI Interface Low Drift Oscillator Precision Temp Sensor CLK DGND AIN1 Mux PGA AIN2 AIN3/REFN1 AVSS CS SCLK DIN DOUT/DRDY DRDY 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. PRODUCT FAMILY DEVICE RESOLUTION (Bits) MAXIMUM GAIN MAXIMUM SAMPLE RATE (SPS) ADS1120 16 128 2000 ADS1220 24 128 2000 PACKAGE DESIGNATOR QFN-16 TSSOP-16 QFN-16 TSSOP-16 ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT MIN MAX AVDD to AVSS –0.3 +7 V DVDD to DGND –0.3 +7 V AVSS to DGND –2.8 +0.3 V V Analog input voltage AIN0/REFP1, AIN1, AIN2, AIN3/REFN1, REFP0, REFN0 AVSS – 0.3 AVDD + 0.3 Digital input voltage CS, SCLK, DIN, DOUT/DRDY, DRDY, CLK Analog input current Temperature DGND – 0.3 DVDD + 0.3 Momentary –100 +100 mA Continuous –10 +10 mA Maximum junction, TJMax (1) +150 °C –60 +150 °C –2000 +2000 V –500 +500 V Storage, Tstg Human body model (HBM) Electrostatic discharge (ESD) JEDEC standard 22, test method A114-C.01, all pins ratings Charged device model (CDM) JEDEC standard 22, test method C101, all pins V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. THERMAL INFORMATION ADS1220 THERMAL METRIC (1) QFN (RVA) TSSOP (PW) 16 PINS 16 PINS θJA Junction-to-ambient thermal resistance 43.4 99.5 θJCtop Junction-to-case (top) thermal resistance 47.3 35.2 θJB Junction-to-board thermal resistance 18.4 44.3 ψJT Junction-to-top characterization parameter 0.6 2.4 ψJB Junction-to-board characterization parameter 18.4 43.8 θJCbot Junction-to-case (bottom) thermal resistance 2.0 n/a (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS Minimum and maximum specifications are at TA = –40°C to +125°C. Typical specifications are at TA = +25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, and DR = 20 SPS using external VREF = 2.5 V, unless otherwise noted. (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale differential input voltage range VCM ±VREF / PGA (2) VIN = (AINP – AINN) Absolute input voltage AINP or AINN, PGA disabled Common-mode input voltage range [VCM = (AINP + AINN) / 2] PGA disabled (3) (3) PGA = 1...128 V AVSS – 0.1 AVDD + 0.1 V AVSS – 0.1 AVDD + 0.1 V See the Low-Noise PGA section Absolute input current See the Typical Characteristics Differential input current See the Typical Characteristics SYSTEM PERFORMANCE Resolution No missing codes 24 Normal mode DR Data rate SPS Duty-cycle mode 5, 11.25, 22.5, 44, 82.5, 150, 250 SPS Turbo mode 40, 90, 180, 350, 660, 1200, 2000 SPS Noise (input-referred) INL Integral nonlinearity See the Noise Performance section PGA = 1…128, VCM = 0.5 AVDD, external reference, best fit -15 PGA disabled, TA = +25°C, differential inputs VIO Offset voltage (input-referred) CMRR PSRR 15 ppm PGA = 1, TA = +25°C, differential inputs –30 ±4 µV 30 µV ±4 µV PGA = 1…128, TA = –40°C to +85°C (4) 0.08 PGA = 1…128, TA = –40°C to +125°C 0.25 µV/°C Offset match Match between any two inputs ±20 µV Gain error PGA = 1…128, TA = +25°C Gain drift PGA = 1…128, TA = –40°C to +125°C (4) Offset drift NMRR ±6 ±4 PGA = 2…128, TA = +25°C, differential inputs GE Bits 20, 45, 90, 175, 330, 600, 1000 Normal-mode rejection ratio (5) Common-mode rejection ratio Power-supply rejection ratio -0.1% 0.3 ±0.015% 0.1% 1 4 µV/°C ppm/°C 50 Hz ±3%, DR = 20 SPS, external CLK, bit 50/60 = 10 105 dB 60 Hz ±3%, DR = 20 SPS, external CLK, bit 50/60 = 11 105 dB 50 Hz or 60 Hz ±3%, DR = 20 SPS, external CLK, Bit 50/60 = '01' 90 dB At dc and PGA = 1 90 105 dB fCM = 50 Hz, DR = 2000 SPS (4) 95 115 dB fCM = 60 Hz, DR = 2000 SPS (4) 95 115 dB AVDD at dc, VCM = 0.5 AVDD, PGA = 1 80 105 dB 100 115 dB 2.045 2.048 2.051 5 40 DVDD at dc, VCM = 0.5 AVDD, PGA = 1 (4) INTERNAL VOLTAGE REFERENCE Initial accuracy TA = +25°C Reference drift TA = –40°C to +125°C (4) V ppm/°C VOLTAGE REFERENCE INPUT VREF (1) (2) (3) (4) (5) Reference input range VREF = (REFPx – REFNx) AVDD V Negative reference absolute input REFNx to AVSS AVSS – 0.1 0.75 2.5 REFPx – 0.75 V Positive reference absolute input REFPx to AVSS REFNx + 0.75 AVDD + 0.1 Reference input current REFN0 = AVSS, REFP0 = VREF ±10 V nA PGA disabled means the low-noise PGA is bypassed. Only gains of 1, 2, and 4 are possible in this case with the switched-capacitor input structure. PGA = 1…128 denotes that the low-noise PGA is enabled and set to the respective gain setting. Limited to [(AVDD – AVSS) – 0.4 V] / PGA, when the PGA is enabled. See the Bypassing the PGA section for more information. Minimum and maximum values are ensured by design and characterization data. Minimum values are ensured by design. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 3 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –40°C to +125°C. Typical specifications are at TA = +25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, and DR = 20 SPS using external VREF = 2.5 V, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXCITATION CURRENT SOURCES (IDACs) Current settings 10, 50, 100, 250, 500, 1000, 1500 µA Compliance voltage All currents AVDD – 0.9 Accuracy All currents, each IDAC Current match Between IDACs (not valid for 10-µA setting) ±0.3% Temperature drift Each IDAC (not valid for 10-µA setting) 50 ppm/°C Temperature drift matching Between IDACs (not valid for 10-µA setting) 10 ppm/°C –6% ±1% V 6% CLOCK SOURCES Internal oscillator accuracy External clock Normal mode Frequency range Duty cycle –2% ±1% 0.5 4.096 40% 2% 4.5 MHz 60% TEMPERATURE SENSOR Temperature sensor resolution Conversion resolution TA = 0°C to +75°C Temperature sensor accuracy 14 Temperature resolution TA = –40°C to +125°C Bits 0.03125 °C –0.5 ±0.25 0.5 –1 ±0.5 1 0.0625 0.25 3.5 5.5 Ω 30 mA vs analog supply voltage °C °C °C/V LOW-SIDE POWER SWITCH RON On resistance Current through switch DIGITAL INPUT/OUTPUT VIH High-level input voltage 0.7 DVDD DVDD V VIL Low-level input voltage DGND – 0.3 0.3 DVDD V VOH High-level output voltage IOH = 3 mA VOL Low-level output voltage IOL = 3 mA IH Input leakage, high VIH = 5.5 V IL Input leakage, low VIL = DGND 4 Submit Documentation Feedback 0.8 DVDD V 0.2 DVDD V –10 10 µA –10 10 µA Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications are at TA = –40°C to +125°C. Typical specifications are at TA = +25°C. All specifications are at AVDD = 3.3 V, AVSS = 0 V, DVDD = 3.3 V, and DR = 20 SPS using external VREF = 2.5 V, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER-SUPPLY REQUIREMENTS VDD Supply voltage Digital DVDD to DGND 2.3 5.5 V Analog, unipolar AVDD to AVSS, AVSS = DGND 2.3 5.5 V AVDD to DGND 2.3 2.75 V AVSS to DGND –2.75 –2.3 V 3 µA Analog, bipolar Power-down mode 0.1 Duty-cycle mode, PGA disabled IAVDD ICC Supply current (6) IDVDD PD Power dissipation (6) 65 µA Normal mode, PGA disabled 240 Normal mode, PGA = 1…16 340 µA Normal mode, PGA = 32 425 µA Normal mode, PGA = 64, 128 510 µA Turbo mode, PGA = 1…16 540 Power-down mode 0.3 Duty-cycle mode 55 Normal mode 75 Turbo mode 95 µA Duty-cycle mode, PGA disabled 0.4 mW Normal mode, PGA = 1…16 1.4 mW Turbo mode, PGA = 1…16 2.1 mW 490 µA µA 5 µA µA 110 µA TEMPERATURE RANGE Tstg (6) Storage temperature –60 +150 °C Specified temperature –40 +125 °C Internal voltage reference selected, internal oscillator enabled, both IDACs turned off. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 5 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com SPI TIMING CHARACTERISTICS tCSH tCSSC tSCLK tSPWL tDIHD tCSDOD § § § DIN tDOPD tCSDOZ Hi-Z § § Hi-Z § § DOUT/DRDY § tDIST tSCCS tSPWH § SCLK § § CS Figure 1. Serial Interface Timing Timing Characteristics for Figure 1 (1) PARAMETER MIN MAX UNIT tCSSC CS low to first SCLK high: setup time 50 ns tSCCS Final SCLK falling edge to CS high 25 ns tDIST DIN setup time 50 ns tDIHD DIN hold time 25 tDOPD SCLK rising edge to new data valid: propagation delay (2) 0 ns 50 ns tSCLK SCLK period 150 ns tSPWH SCLK pulse width: high (2) 60 ns tSPWL SCLK pulse width: low (2) 60 ns tCSDOZ CS high to DOUT high impedance: propagation delay 50 ns tCSDOD CS low to DOUT driven: propagation delay 50 ns tCSH CS high pulse width (1) (2) 6 50 ns At TA = –40°C to +125°C, DVDD = 2.3 V to 5.5 V, and DOUT load = 20 pF || 10 kΩ to DGND, unless otherwise noted. If a complete command is not sent within 13955 × tMOD (normal mode, duty-cycle mode) or 27910 × tMOD (turbo mode), respectively, the serial interface resets and the next SCLK pulse starts a new communication cycle. tMOD = 1 / fMOD. Modulator frequency (fMOD) is 256 kHz in normal and duty-cycle mode and 512 kHz in turbo mode when using the internal oscillator or an external 4.096-MHz clock. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 PIN CONFIGURATIONS CS SCLK DIN DOUT/DRDY RVA PACKAGE QFN-16 (TOP VIEW) 16 15 14 13 DGND 2 11 DVDD AVSS 3 10 AVDD AIN3/REFN1 4 9 AIN2 5 6 7 8 AIN1 12 DRDY REFP0 1 REFN0 CLK AIN0/REFP1 PIN DESCRIPTIONS (QFN PACKAGE) NAME PIN NO. ANALOG OR DIGITAL INPUT/OUTPUT CLK 1 Digital input DGND 2 Digital Digital ground AVSS 3 Analog Negative analog power supply AIN3/REFN1 4 Analog input Differential or single-ended input; negative reference input AIN2 5 Analog input Differential or single-ended input REFN0 6 Analog input Negative reference input REFP0 7 Analog input Positive reference input AIN1 8 Analog input Differential or single-ended input AIN0/REFP1 9 Analog input Differential or single-ended input; positive reference input AVDD 10 Analog Positive analog power supply DVDD 11 Digital Positive digital power supply DRDY 12 Digital output Data ready; active low DOUT/DRDY 13 Digital output Serial data output combined with data ready; active low DIN 14 Digital input Serial data input SCLK 15 Digital input Serial clock input CS 16 Digital input Chip select; active low Thermal pad Thermal pad — DESCRIPTION External clock source pin; connect to DGND if not used Thermal power pad. Do not connect or only connect to AVSS. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 7 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com PW PACKAGE TSSOP-16 (TOP VIEW) SCLK 1 16 DIN CS 2 15 DOUT/DRDY CLK 3 14 DRDY DGND 4 13 DVDD AVSS 5 12 AVDD AIN3/REFN1 6 11 AIN0/REFP1 AIN2 7 10 AIN1 REFN0 8 9 REFP0 PIN DESCRIPTIONS (TSSOP PACKAGE) 8 NAME PIN NO. ANALOG OR DIGITAL INPUT/OUTPUT SCLK 1 Digital input Serial clock input DESCRIPTION CS 2 Digital input Chip select; active low CLK 3 Digital input External clock source pin; connect to DGND if not used DGND 4 Digital Digital ground AVSS 5 Analog Negative analog power supply AIN3/REFN1 6 Analog input Differential or single-ended input; negative reference input AIN2 7 Analog input Differential or single-ended input REFN0 8 Analog input Negative reference input REFP0 9 Analog input Positive reference input AIN1 10 Analog input Differential or single-ended input AIN0/REFP1 11 Analog input Differential or single-ended input; positive reference input AVDD 12 Analog Positive analog power supply DVDD 13 Digital Positive digital power supply DRDY 14 Digital output Data ready; active low DOUT/DRDY 15 Digital output Serial data output combined with data ready; active low DIN 16 Digital input Serial data input Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 40 40 PGA = 1 PGA = 128 30 20 10 0 20 10 -10 -40 -20 0 20 40 60 80 100 120 Temperature (C) -40 -20 0 20 40 60 80 100 120 Temperature (C) C017 Figure 2. INPUT-REFERRED OFFSET VOLTAGE vs TEMPERATURE (AVDD = 3.3 V) C018 Figure 3. INPUT-REFERRED OFFSET VOLTAGE vs TEMPERATURE (AVDD = 5.0 V) 500 500 PGA = 1 AVDD = 3.3 V PGA = 128 400 PGA = 1 AVDD = 5.0 V Gain Error (ppm of FS) Gain Error (ppm of FS) PGA Disabled 0 -10 PGA Disabled 300 200 100 0 PGA = 128 400 PGA Disabled 300 200 100 0 -40 -20 0 20 40 60 80 100 Temperature (C) 120 -40 15 PGA = 32 INL (ppm of FS) 0 -5 AVDD = 3.3 V External 2.5-V Reference Normal Mode -50 -25 0 25 50 75 VIN (% of FS) 60 80 100 120 C020 PGA = 32 10 5 -75 40 PGA = 1 PGA Disabled PGA Disabled -15 -100 20 Figure 5. GAIN ERROR vs TEMPERATURE (AVDD = 5.0 V) 15 -10 0 Temperature (C) PGA = 1 10 -20 C019 Figure 4. GAIN ERROR vs TEMPERATURE (AVDD = 3.3 V) INL (ppm of FS) AVDD = 5.0 V PGA = 128 30 PGA Disabled Offset Voltage (µV) Offset Voltage (µV) PGA = 1 AVDD = 3.3 V 5 0 -5 AVDD = 5.0 V External 2.5-V Reference Normal Mode -10 100 -15 -100 C025 Figure 6. INTEGRAL NONLINEARITY vs DIFFERENTIAL INPUT SIGNAL (AVDD = 3.3 V, External Reference) -75 -50 -25 0 25 50 75 VIN (% of FS) Product Folder Links: ADS1220 C029 Figure 7. INTEGRAL NONLINEARITY vs DIFFERENTIAL INPUT SIGNAL (AVDD = 5.0 V, External Reference) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 100 9 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 20 15 PGA = 1 15 PGA = 32 PGA Disabled PGA = 32 PGA Disabled 10 INL (ppm of FS) 10 INL (ppm of FS) 20 PGA = 1 5 0 -5 -10 5 0 -5 -10 AVDD = 3.3 V Internal Reference Normal Mode -15 -20 -100 -75 -50 -25 0 25 50 75 VIN (% of FS) AVDD = 5.0 V Internal Reference Normal Mode -15 -20 -100 100 -25 0 25 50 75 100 C029 Figure 9. INTEGRAL NONLINEARITY vs DIFFERENTIAL INPUT SIGNAL (AVDD = 5.0 V, Internal Reference) 2.051 1000 AVDD = 3.3 V Data from 5490 Devices TA = +25°C AVDD = 5.0 V 2.05 Reference Voltage (V) 800 Counts -50 VIN (% of FS) Figure 8. INTEGRAL NONLINEARITY vs DIFFERENTIAL INPUT SIGNAL (AVDD = 3.3 V, Internal Reference) 600 400 200 2.049 2.048 2.047 Initial Reference Voltage (V) 2.051 2.050 2.049 2.048 2.047 2.046 2.046 2.045 0 -75 C025 2.045 -40 -20 0 20 40 60 80 100 120 Temperature (C) C021 C042 Figure 10. INTERNAL REFERENCE VOLTAGE HISTOGRAM Figure 11. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE 1 0 0.75 -20 0.5 -40 0.25 -60 PSRR (dB) Frequency Error (%) PGA = 1 0 -0.25 -0.5 -80 -100 -120 DVDD = 3.3 V Normal Mode -0.75 -140 -1 -160 -40 -20 0 20 40 60 Temperature (C) 80 100 120 0.1 1 10 Frequency (kHz) C002 Figure 12. INTERNAL OSCILLATOR ACCURACY vs TEMPERATURE 10 PGA = 128 100 1000 C016 Figure 13. AVDD POWER-SUPPLY REJECTION RATIO vs FREQUENCY Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 15 AIN0 AIN1 AIN2 AIN3 10 AVDD = 3.3 V PGA Enabled TA = -40°C Absolute Input Current (nA) Absolute Input Current (nA) 15 5 0 -5 -10 -15 AIN0 AIN1 AIN2 AIN3 10 5 0 -5 -10 -15 0.5 1 1.5 2 2.5 3 Absolute Input Voltage VAINx (V) 0.5 10 AIN0 AIN1 AIN2 AIN3 1.5 2 2.5 3 Absolute Input Voltage VAINx (V) C031 Figure 15. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Enabled, TA = +25°C) 100 AVDD = 3.3 V PGA Enabled TA = +85°C Absolute Input Current (nA) Absolute Input Current (nA) 20 1 C030 Figure 14. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Enabled, TA = –40°C) 0 -10 -20 -30 -40 50 AIN0 AIN1 AIN2 AIN3 AVDD = 3.3 V PGA Enabled TA = +125°C 0 -50 -100 -150 -200 -50 -250 0.5 1 1.5 2 2.5 3 Absolute Input Voltage VAINx (V) 0.5 20 2 2.5 3 C033 Figure 17. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Enabled, TA = +125°C) 40 Ta = -40C Ta = +25C Ta = +85C Ta = +125C 1.5 Absolute Input Voltage VAINx (V) AVDD = 3.3 V PGA Enabled AIN0:AIN1 Differential Input Current (nA) 40 1 C032 Figure 16. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Enabled, TA = +85°C) Differential Input Current (nA) AVDD = 3.3 V PGA Enabled TA = +25°C 0 -20 -40 -60 Ta = -40C Ta = +25C Ta = +85C Ta = +125C 20 AVDD = 3.3 V PGA Enabled AIN3:AIN2 0 -20 -40 -60 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Differential Input Voltage VIN (V) 2 -2 Figure 18. DIFFERENTIAL INPUT CURRENT vs DIFFERENTIAL INPUT VOLTAGE (PGA Enabled, AIN0:AIN1) -1.5 -1 -0.5 0 0.5 1 1.5 Differential Input Voltage VIN (V) C038 2 C023 Figure 19. DIFFERENTIAL INPUT CURRENT vs DIFFERENTIAL INPUT VOLTAGE (PGA Enabled, AIN3:AIN2) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 11 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 15 AIN0 AIN1 AIN2 AIN3 10 AVDD = 3.3 V PGA Disabled TA = -40°C Absolute Input Current (nA) Absolute Input Current (nA) 15 5 0 -5 -10 -15 AIN0 AIN1 AIN2 AIN3 10 5 0 -5 -10 -15 0.5 1 1.5 2 2.5 3 Absolute Input Voltage VAINx (V) 0.5 10 AIN0 AIN1 AIN2 AIN3 2 2.5 3 C035 Figure 21. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Disabled, TA = +25°C) 100 AVDD = 3.3 V PGA Disabled TA = +85°C 0 -10 -20 -30 -40 50 AIN0 AIN1 AIN2 AIN3 AVDD = 3.3 V PGA Disabled TA = +125°C 0 -50 -100 -150 -200 -50 -250 0.5 1 1.5 2 2.5 3 Absolute Input Voltage VAINx (V) 0.5 20 2 2.5 3 C037 Figure 23. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Disabled, TA = +125°C) 40 Ta = -40C Ta = +25C Ta = +85C Ta = +125C 1.5 Absolute Input Voltage VAINx (V) AVDD = 3.3 V PGA Disabled AIN0:AIN1 Differential Input Current (nA) 40 1 C036 Figure 22. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Disabled, TA = +85°C) Differential Input Current (nA) 1.5 Absolute Input Voltage VAINx (V) Absolute Input Current (nA) Absolute Input Current (nA) 20 1 C034 Figure 20. ABSOLUTE INPUT CURRENT vs ABSOLUTE INPUT VOLTAGE (PGA Disabled, TA = –40°C) 0 -20 -40 -60 Ta = -40C Ta = +25C Ta = +85C Ta = +125C 20 AVDD = 3.3 V PGA Disabled AIN3:AIN2 0 -20 -40 -60 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Differential Input Voltage VIN (V) 2 -2 -1.5 -1 -0.5 0 0.5 1 1.5 Differential Input Voltage VIN (V) C040 Figure 24. DIFFERENTIAL INPUT CURRENT vs DIFFERENTIAL INPUT VOLTAGE (PGA Disabled, AIN0:AIN1) 12 AVDD = 3.3 V PGA Disabled TA = +25°C 2 C041 Figure 25. DIFFERENTIAL INPUT CURRENT vs DIFFERENTIAL INPUT VOLTAGE (PGA Disabled, AIN3:AIN2) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 6 6 IDAC = 1000 µA IDAC = 500 µA IDAC = 500 µA 4 Absolute IDAC Error (%) 4 IDAC Error (%) IDAC = 100 µA 2 0 -2 -4 2 0 -2 -4 -6 -6 0.5 0.6 0.7 0.8 0.9 1 Compliance Voltage (V) -40 20 IDAC = 500 µA 0.5 IDAC = 100 µA 60 80 100 120 C005 600 IDAC = 1000 µA 0.75 40 Figure 27. IDAC ACCURACY vs TEMPERATURE 500 400 0.25 IAVDD (µA) IDAC Matching Error (%) 0 Temperature (C) Figure 26. IDAC ACCURACY vs COMPLIANCE VOLTAGE 1 -20 C006 0 -0.25 300 200 -0.5 PGA = 64, 128 AVDD = 3.3 V Internal Reference Normal Mode 100 -0.75 -1 PGA = 1...16 PGA Disabled 0 -40 -20 0 20 40 60 80 100 120 Temperature (C) -40 -20 0 20 40 60 80 100 120 Temperature (C) C007 Figure 28. IDAC MATCHING vs TEMPERATURE C011 Figure 29. IAVDD vs TEMPERATURE (Normal Mode) 150 1000 125 800 IAVDD (µA) IAVDD (µA) 100 600 400 75 50 PGA = 64, 128 200 AVDD = 3.3 V Internal Reference Turbo Mode PGA Disabled 0 -40 -20 0 PGA = 64, 128 20 40 60 80 100 Temperature (C) AVDD = 3.3 V Internal Reference Duty-Cycle Mode 25 PGA = 1...16 PGA = 1...16 PGA Disabled 0 120 -40 C012 Figure 30. IAVDD vs TEMPERATURE (Turbo Mode) -20 0 20 40 60 80 100 Temperature (C) Product Folder Links: ADS1220 C013 Figure 31. IAVDD vs TEMPERATURE (Duty-Cycle Mode) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 120 13 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 600 120 500 100 400 80 IDVDD (µA) IAVDD (µA) At TA = +25°C, AVDD = 3.3 V, and AVSS = 0 V using external VREF = 2.5 V, unless otherwise noted. 300 200 60 40 Turbo Mode PGA = 64, 128 100 20 PGA = 1...16 Normal Mode Internal Reference Normal Mode PGA Disabled 0 Duty-Cycle Mode 0 2.5 3 3.5 4 4.5 5 5.5 AVDD (V) 2.5 3 1 0.75 Temperature Error (%) 100 IDVDD (µA) 80 60 40 Turbo Mode Normal Mode 0 20 40 60 5.5 C010 80 Mean Mean - 61 0.5 0.25 0 -0.25 -0.5 -0.75 Duty-Cycle Mode -20 5 Mean + 61 DVDD = 3.3 V 0 4.5 Figure 33. IDVDD vs DVDD 120 20 4 DVDD (V) C004 Figure 32. IAVDD vs AVDD -40 3.5 100 -1 120 Temperature (C) -40 -20 0 20 40 60 Temperature (C) C014 Figure 34. IDVDD vs TEMPERATURE 80 100 120 C015 Figure 35. INTERNAL TEMPERATURE SENSOR ACCURACY vs TEMPERATURE 6 5 RON ( 4 3 2 AVDD = 2.3 V 1 AVDD = 3.3 V AVDD = 5.0 V 0 -40 -20 0 20 40 60 Temperature (C) 80 100 120 C001 Figure 36. LOW-SIDE POWER SWITCH RON vs TEMPERATURE 14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 NOISE PERFORMANCE As is the case with any delta-sigma (ΔΣ) ADC, noise performance can be optimized by adjusting the output data rate. When reducing the data rate, the input-referred noise drops correspondingly because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the inputreferred noise, which is particularly useful when measuring low-level signals. Table 1 to Table 4 summarize the device noise performance. Data are representative of typical noise performance at TA = +25°C with the internal 2.048-V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 1 and Table 3 list the input-referred noise in units of μVRMS for the conditions shown. Note that µVPP values are shown in parenthesis. Table 2 and Table 4 list the corresponding data in effective number of bits (ENOB) calculated from μVRMS values using Equation 1. Note that noise-free bits calculated from peak-to-peak noise values are shown in parenthesis. The input-referred noise (Table 1 and Table 3) only changes marginally when using an external low-noise reference, such as the REF5020. To calculate ENOB values when using a reference voltage other than 2.048 V, use Equation 1 and Equation 2: ENOB = ln (Full-Scale Range / Noise) / ln(2) Full-Scale Range = 2 × VREF / PGA (1) (2) Table 1. Noise in μVRMS (μVPP) at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V DATA RATE (SPS) GAIN (PGA ENABLED) 1 20 45 90 2 4 8 16 32 64 128 3.71 (13.67) 1.54 (5.37) 1.15 (4.15) 0.80 (3.36) 0.35 (1.16) 0.23 (0.73) 0.10 (0.35) 0.09 (0.41) 7.36 (29.54) 2.93 (13.06) 1.71 (9.28) 0.88 (4.06) 0.50 (2.26) 0.29 (1.49) 0.19 (0.82) 0.12 (0.51) 10.55 (47.36) 4.50 (20.75) 2.43 (11.35) 1.51 (6.65) 0.65 (3.62) 0.42 (2.14) 0.27 (1.22) 0.18 (0.85) 175 11.90 (63.72) 6.45 (34.06) 3.26 (17.76) 1.82 (11.20) 1.01 (5.13) 0.57 (3.09) 0.34 (2.14) 0.26 (1.60) 330 19.19 (106.93) 9.38 (50.78) 4.25 (26.25) 2.68 (14.13) 1.45 (7.52) 0.79 (4.66) 0.50 (2.69) 0.34 (1.99) 600 24.78 (151.61) 13.35 (72.27) 6.68 (39.43) 3.66 (19.26) 2.10 (12.77) 1.14 (6.87) 0.70 (4.76) 0.55 (3.34) 1000 37.53 (227.29) 18.87 (122.68) 9.53 (58.53) 5.37 (31.52) 2.95 (18.08) 1.65 (10.71) 1.03 (6.52) 0.70 (4.01) 2000 36.23 (265.14) 18.24 (127.32) 9.24 (65.43) 5.49 (37.02) 2.89 (18.89) 1.77 (12.00) 1.13 (7.60) 0.82 (5.81) Table 2. ENOB from RMS Noise (Peak-to-Peak Noise) at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V DATA RATE (SPS) GAIN (PGA ENABLED) 1 2 4 8 16 32 64 128 20 20.08 (18.19) 20.34 (18.54) 19.76 (17.91) 19.28 (17.22) 19.48 (17.75) 19.10 (17.42) 19.33 (17.49) 18.49 (16.26) 45 19.09 (17.08) 19.42 (17.26) 19.19 (16.75) 19.15 (16.94) 18.95 (16.79) 18.74 (16.39) 18.38 (16.25) 18.00 (15.49) 90 18.57 (16.40) 18.80 (16.59) 18.68 (16.46) 18.37 (16.23) 18.60 (16.11) 18.20 (15.87) 17.87 (15.67) 17.44 (15.20) 175 18.39 (15.97) 18.28 (15.88) 18.26 (15.82) 18.10 (15.48) 17.96 (15.61) 17.78 (15.34) 17.53 (14.87) 16.91 (14.29) 330 17.70 (15.23) 17.74 (15.30) 17.88 (15.25) 17.54 (15.15) 17.43 (15.05) 17.30 (14.74) 16.96 (14.54) 16.50 (13.97) 600 17.33 (14.72) 17.23 (14.79) 17.23 (14.66) 17.09 (14.70) 16.89 (14.29) 16.77 (14.18) 16.48 (13.72) 15.83 (13.23) 1000 16.74 (14.14) 16.73 (14.03) 16.71 (14.09) 16.54 (13.99) 16.41 (13.79) 16.25 (13.54) 15.92 (13.26) 15.49 (12.96) 2000 16.79 (13.92) 16.78 (13.97) 16.76 (13.93) 16.51 (13.76) 16.44 (13.73) 16.14 (13.38) 15.79 (13.04) 15.25 (12.43) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 15 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com Table 3. Noise in μVRMS (μVPP) with PGA Disabled at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V GAIN (PGA DISABLED) DATA RATE (SPS) 1 2 4 20 3.89 (13.43) 1.85 (6.84) 1.26 (3.91) 45 6.97 (31.98) 2.94 (12.94) 1.41 (5.62) 90 8.50 (42.48) 4.49 (18.92) 2.07 (9.95) 175 12.99 (65.92) 6.24 (35.40) 3.04 (18.92) 330 18.18 (94.24) 8.12 (50.17) 4.71 (28.75) 600 25.29 (138.67) 12.77 (78.13) 6.27 (39.79) 1000 38.04 (260.50) 18.40 (120.97) 9.48 (63.72) 2000 36.11 (250.98) 17.30 (131.35) 8.77 (68.18) Table 4. ENOB from RMS Noise (Peak-to-Peak Noise) with PGA Disabled at AVDD = 3.3 V, AVSS = 0 V, and Internal Reference = 2.048 V 16 GAIN (PGA DISABLED) DATA RATE (SPS) 1 2 4 20 20.01 (18.22) 20.08 (18.19) 19.63 (18.00) 45 19.61 (16.97) 19.41 (17.27) 19.47 (17.48) 90 18.88 (16.56) 18.80 (16.72) 18.91 (16.65) 175 18.27 (15.92) 18.32 (15.82) 18.36 (15.72) 330 17.78 (15.41) 17.94 (15.32) 17.73 (15.12) 600 17.31 (14.85) 17.29 (14.68) 17.32 (14.65) 1000 16.72 (13.94) 16.76 (14.05) 16.72 (13.97) 2000 16.79 (13.99) 16.85 (13.93) 16.83 (13.87) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 OVERVIEW The ADS1220 is a small, low-power, 24-bit, highly-integrated, ΔΣ analog-to-digital converter (ADC). The device is easy to configure and design into a wide variety of applications and allows precise measurements to be obtained with little effort. In addition to the ΔΣ ADC core and single-cycle settling digital filter, the ADS1220 offers a low-noise, high input impedance, programmable gain amplifier (PGA), an internal voltage reference, a clock oscillator, and an SPIcompatible interface. The device also integrates a highly linear and accurate temperature sensor as well as two matched programmable current sources (IDACs) for sensor excitation. All of these features are intended to reduce the required external circuitry in typical sensor applications and improve overall system performance. An additional low-side power switch eases the design of low-power bridge sensor applications. Figure 37 shows the ADS1220 functional block diagram. REFP0 AVDD REFN0 DVDD 10 A to 1.5 mA Internal Reference AIN0/REFP1 AIN1 Device 24-bit ûADC Digital Filter and SPI Interface Low Drift Oscillator Precision Temp Sensor CLK DGND AINP Mux AIN2 Reference Mux PGA AINN AIN3/REFN1 AVSS CS SCLK DIN DOUT/DRDY DRDY Figure 37. Functional Block Diagram The ADS1220 ADC measures a differential signal, VIN, which is the difference of AINP and AINN. The converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. This architecture results in a very strong attenuation in any common-mode signals. The device has two available conversion modes: single-shot and continuous conversion mode. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal data buffer. The device then enters a low-power state to save power. Single-shot mode is intended to provide significant power savings in systems that require only periodic conversions or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. New data are available at the programmed data rate. Data can be read at any time without concern of data corruption and always reflect the most recently completed conversion. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 17 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com MULTIPLEXER The device contains a very flexible input multiplexer, as shown in Figure 38. Either four single-ended signals, two differential signals, or a combination of two single-ended signals and one differential signal can be measured. The multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are measured, the ADC negative input is internally connected to AVSS by a switch within the multiplexer. For system-monitoring purposes, the analog supply (AVDD – AVSS) / 4 or the currently-selected external reference (REFPx – REFNx) / 4 can be selected as inputs to the ADC. The multiplexer also offers the possibility to route any of the two programmable current sources to any analog input (AINx) or to any dedicated reference pin (REFP0, REFN0). System Monitors (REFPx ± REFNx)/4 (AVDD ± AVSS)/4 AVDD AVDD IDAC1 AVDD AVSS AVDD AVSS IDAC2 (AVDD + AVSS)/2 AIN0/REFP1 AVDD AIN1 Burnout Current Source (10 µA) AVDD AVSS AVDD AVSS AIN2 AINP PGA To ADC AINN AIN3/REFN1 AVDD AVSS AVDD AVSS Burnout Current Source (10 µA) REFP0 AVSS AVSS REFN0 Figure 38. Analog Input Multiplexer Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range of Equation 3: AVSS – 0.3 V < AINx < AVDD + 0.3 V (3) If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Although the analog inputs can support signals marginally above supply, under no circumstances should any analog or digital input or output be driven to greater than 5.5 V with respect to the GND pin. Overdriving an unused input on the device may affect conversions taking place on other input pins. If any overdrive on unused inputs is possible, TI recommends clamping the signal with external Schottky diodes. 18 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 LOW-NOISE PGA The device features a low-noise, low-drift, high input impedance, programmable gain amplifier (PGA). The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Three bits (GAIN[2:0]) in the configuration register are used to configure the gain. A simplified diagram of the PGA is shown in Figure 39. The PGA consists of two chopperstabilized amplifiers (A1 and A2) and a resistor feedback network that sets the PGA gain. The PGA input is equipped with an electromagnetic interference (EMI) filter. 200 W AINP 25 pF A1 R ADC C R A2 200 W AINN 25 pF Figure 39. Simplified Diagram of the PGA The differential full-scale (FS) input voltage range of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4: FS = ±VREF / PGA (4) Table 5 shows the corresponding full-scale ranges when using the internal 2.048-V reference. Table 5. PGA Full-Scale Range GAIN SETTING FS 1 ±2.048 V 2 ±1.024 V 4 ±0.512 V 8 ±0.256 V 16 ±0.128 V 32 ±0.064 V 64 ±0.032 V 128 ±0.016 V Note that as with any PGA, the input voltage must remain within a specified common-mode input voltage range. The common-mode input voltage (VCM) must stay within the minimum and maximum limits given by Equation 5 and Equation 6: VIN ´ PGA AVDD - AVSS VCM (MIN) ³ AVSS + VCM (MIN) ³ AVSS + 0.2 V + and 4 2 (5) VIN ´ PGA VCM (MAX) £ AVDD - 0.2 V 2 (6) where: • • • VCM = (AINP + AINN) / 2, PGA = PGA gain, and VIN = the maximum differential input voltage (AINP – AINN) in the application, which is limited to [(AINP – AINN) ≤ ±VREF / PGA]. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 19 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com Figure 40 and Figure 41 show a graphical representation of the common-mode voltage limits for AVDD = 3.3 V, PGA = 1 and PGA = 16, respectively. 3.3 3.3 AVDD = 3.3 V PGA = 1 AVDD = 3.3 V PGA = 16 2.75 2.2 VCM Range (V) VCM Range (V) 2.75 1.65 3.3 V / 4 1.1 0.55 2.2 1.65 3.3 V / 4 1.1 0.55 0 0 0 0.5 1 1.5 2 2.5 VIN (V) 3 0 Figure 40. Common-Mode Voltage Limits (AVDD = 3.3 V, PGA = 1) 0.03 0.06 0.09 0.12 0.15 0.18 VIN (V) C009 C008 Figure 41. Common-Mode Voltage Limits (AVDD = 3.3 V, PGA = 16) The following paragraphs explain how to apply Equation 5 and Equation 6 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and PGA = 16, using an external reference VREF= 2.5 V. The maximum differential input voltage VIN = (AINP – AINN) that can be applied is then limited to the full-scale range of FS = ±2.5 V / 16 = ±0.156 V. Equation 5 and Equation 6 then yield an allowed VCM range of 1.45 V ≤ VCM ≤ 1.85 V. However, the sensor signal that is connected to the inputs in this example application does not make use of the entire full-scale range but is limited to VIN = ±0.1 V. Accordingly, this reduced input signal relaxes the VCM restriction to 1.0 V ≤ VCM ≤ 2.3 V. In the case of a fully-differential sensor signal, each input (AINP, AINN) can swing up to ±50 mV around the center voltage (AINP + AINN) / 2, which must remain between the common-mode voltage limits of 1.0 V and 2.3 V. The output of a symmetrical wheatstone bridge is an example of a fully-differential signal. In contrast, the signal of an RTD is of a pseudo-differential nature (depending on the circuit implementation), where the negative input is held at a constant voltage other than 0 V. When a pseudo-differential signal must be measured, the negative input must be biased at a voltage between 1.0 V and 2.25 V. The positive input can then swing up to 100 mV above the negative input. Figure 42 and Figure 43 illustrate both fully-differential and pseudo-differential cases for this specific example, respectively. AINP AINP 100 mV 100 mV 1.0 V 1.0 V AINN AINN 0V 0V Figure 42. Fully-Differential Input Signal 20 Figure 43. Pseudo-Differential Input Signal Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 BYPASSING THE PGA At gains of 1, 2, and 4, the ADS1220 can be configured to disable and bypass the low-noise PGA. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 5 and Equation 6 for the common-mode input voltage range, VCM. The usable absolute and common-mode input voltage range is (AVSS – 0.1 V ≤ VCM ≤ AVDD + 0.1 V) when the PGA is disabled. In order to measure single-ended signals that are referenced to AVSS (VINP = VIN, VINN = AVSS), the PGA must be turned off. NOTE When measuring single-ended inputs, the negative range of the output codes is not used. These codes are for measuring negative differential signals, such as (AINP – AINN) < 0 V. Consequently, one bit of resolution is lost because only half of the full-scale range is used. When the PGA is disabled by setting the PGA_BYPASS bit in the configuration register, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An internal buffer in front of the switched-capacitor stage ensures that the impact on the input loading as a result of the capacitors charging and discharging is minimal. Refer to Figure 20 to Figure 25 for the typical values of absolute (current flowing into or out of each input) and differential (difference in absolute current between positive and negative input) input currents when the PGA is disabled. For signal sources with high output impedance, external buffering may still be necessary. Note that active buffers introduce noise and also introduce offset and gain errors. All of these factors should be considered in highaccuracy applications. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 21 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com MODULATOR A ΔΣ modulator is used in the ADS1220 to convert the analog input voltage into a pulse code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 16 in normal and duty-cycle mode and fMOD = fCLK / 8 in turbo mode, where fCLK is either provided by the internal oscillator or the external clock source. Table 6 shows the modulator frequency for each mode using either the internal oscillator or an external clock of 4.096 MHz. Table 6. Modulator Clock Frequency for Different Operating Modes using the Internal Oscillator OPERATING MODE fMOD Duty-cycle mode 256 kHz Normal mode 256 kHz Turbo mode 512 kHz DIGITAL FILTER 0 0 -40 -40 Magnitude (dB) Magnitude (dB) The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the different data rates and always settles within a single cycle. Only at data rates of 5 SPS and 20 SPS can the filter be configured to reject 50-Hz or 60-Hz line frequencies or to simultaneously reject 50 Hz and 60 Hz. Two bits (50/60[1:0]) in the configuration register are used to configure the filter accordingly. The frequency responses of the digital filter are shown in Figure 44 to Figure 57 for different output data rates using the internal oscillator. -80 -120 -160 -200 0 20 40 60 80 100 120 140 Frequency (Hz) 160 180 200 46 47 48 C006 Figure 44. Filter Response (Data Rate = 20 SPS, 50-Hz Rejection Only) 49 50 51 Frequency (Hz) 52 53 54 C004 Figure 45. Detailed View of Filter Response (Data Rate = 20 SPS, 50-Hz Rejection Only) 0 0 -40 -40 Magnitude (dB) Magnitude (dB) -120 -160 -200 -80 -120 -160 -80 -120 -160 -200 -200 0 20 40 60 80 100 120 140 Frequency (Hz) 160 180 200 56 C010 Figure 46. Filter Response (Data Rate = 20 SPS, 60-Hz Rejection Only) 22 -80 57 58 59 60 61 Frequency (Hz) 62 63 64 C008 Figure 47. Detailed View of Filter Response (Data Rate = 20 SPS, 60-Hz Rejection Only) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 0 0 -40 -40 Magnitude (dB) Magnitude (dB) www.ti.com -80 -120 -160 -120 -160 -200 -200 0 20 40 60 80 100 120 140 Frequency (Hz) 160 180 200 46 50 52 0 -20 -20 Magnitude (dB) 0 -40 54 56 58 Frequency (Hz) 60 62 64 C001 Figure 49. Detailed View of Filter Response (Data Rate = 20 SPS, Simultaneous 50- and 60-Hz Rejection) -60 -40 -60 -80 -80 0 20 40 60 80 100 120 140 160 Frequency (Hz) 180 200 0 20 40 60 -20 -20 Magnitude (dB) 0 -60 100 120 140 160 180 200 C015 Figure 51. Filter Response (Data Rate = 45 SPS) 0 -40 80 Frequency (Hz) C016 Figure 50. Filter Response (Data Rate = 20 SPS, No 50- or 60-Hz Rejection) Magnitude (dB) 48 C002 Figure 48. Filter Response (Data Rate = 20 SPS, Simultaneous 50- and 60-Hz Rejection) Magnitude (dB) -80 -40 -60 -80 -80 0 100 200 300 400 500 600 700 Frequency (Hz) 800 900 1000 0 C014 Figure 52. Filter Response (Data Rate = 90 SPS) 100 200 300 400 500 600 700 800 900 1000 Frequency (Hz) C013 Figure 53. Filter Response (Data Rate = 175 SPS) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 23 ADS1220 www.ti.com 0 0 -20 -20 Magnitude (dB) Magnitude (dB) SBAS501A – MAY 2013 – REVISED JULY 2013 -40 -60 -40 -60 -80 -80 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (Hz) 0 1500 2000 2500 3000 3500 4000 C008 Figure 55. Filter Response (Data Rate = 600 SPS) 0 0 -20 -20 Magnitude (dB) Magnitude (dB) 1000 Frequency (Hz) Figure 54. Filter Response (Data Rate = 330 SPS) -40 -60 -40 -60 -80 -80 0 1 2 3 4 5 6 7 Frequency (kHz) 8 9 10 0 C010 Figure 56. Filter Response (Data Rate = 1 kSPS) 24 500 C012 1 2 3 4 5 6 7 Frequency (kHz) 8 9 10 C009 Figure 57. Filter Response (Data Rate = 2 kSPS) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 OUTPUT DATA RATE Table 7, Table 8, and Table 9 show the actual conversion times for each data rate setting. The values provided are in terms of tCLK cycles using an external clock with a clock frequency of fCLK = 4.096 MHz. Single-shot mode data rates are timed from the last SCLK falling edge of the START/SYNC command to the DRDY falling edge and rounded to the next tCLK. In case the internal oscillator is used, an additional oscillator wake-up time of up to 50 µs (normal mode, duty-cycle mode) or 25 µs (turbo mode), respectively, for each conversion in single-shot mode must be added. The internal oscillator starts to power up at the first SCLK rising edge. Depending on the SCLK frequency, the oscillator cannot be ensured to be fully powered up at the end of the START/SYNC command. A conversion therefore only starts after the internal oscillator is fully powered up. Continuous conversion data rates are timed from one DRDY falling edge the next DRDY falling edge. The first conversion starts 210 × tCLK (normal mode, duty-cycle mode) or 114 × tCLK (turbo mode), respectively, after the last SCLK falling edge of the START/SYNC command. Table 7. Normal Mode ACTUAL CONVERSION TIME (tCLK) NOMINAL DATA RATE (SPS) –3-dB BANDWIDTH (Hz) SINGLE-SHOT MODE CONTINUOUS CONVERSION MODE 20 13.1 204850 204768 45 20.0 91218 91120 90 39.6 46226 46128 175 77.8 23762 23664 330 150.1 12562 12464 600 279.0 6994 6896 1000 483.8 4242 4144 Table 8. Duty-Cycle Mode ACTUAL CONVERSION TIME (tCLK) NOMINAL DATA RATE (SPS) –3-dB BANDWIDTH (Hz) SINGLE-SHOT MODE CONTINUOUS CONVERSION MODE 5 13.1 204850 823120 11.25 20.0 91218 364560 22.5 39.6 46226 184592 44 77.8 23762 94736 82.5 150.1 12562 49936 150 279.0 6994 27664 250 483.8 4242 16656 Table 9. Turbo Mode ACTUAL CONVERSION TIME (tCLK) NOMINAL DATA RATE (SPS) –3-dB BANDWIDTH (Hz) SINGLE-SHOT MODE CONTINUOUS CONVERSION MODE 40 26.2 102434 102384 90 39.9 45618 45560 180 79.2 23122 23064 350 155.6 11890 11832 660 300.3 6290 6232 1200 558.1 3506 3448 2000 967.6 2130 2072 Note that even though the data rate at the 20-SPS setting is not exactly 20 SPS, this discrepancy does not effect the 50-Hz or 60-Hz rejection. To achieve the specified 50-Hz and 60-Hz rejection, the external clock frequency must only be ensured to be exactly 4.096 MHz. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 25 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com ALIASING As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing describes the effect that frequency components in the input signal that are higher than half the sampling frequency of the ADC (also known as the Nyquist frequency) are folded back and show up in the actual frequency band of interest below half the sampling frequency. Note that inside a ΔΣ ADC, the input signal is sampled at the modulator frequency fMOD and not at the output data rate. The filter response of the digital filter repeats at multiples of the sampling frequency (fMOD), as shown in Figure 58. Signals or noise up to a frequency where the filter response repeats are attenuated by the digital filter. However, any frequency components present in the input signal around the modulator frequency or multiples thereof are not attenuated and thus alias back into the band of interest, unless attenuated by an external analog filter. Some signals are inherently bandlimited; for example, the output of a thermocouple has a limited rate of change. Nevertheless, these signals can contain noise and interference components at higher frequencies, which can fold back into the frequency band of interest. A simple RC filter is (in most cases) sufficient to reject these high-frequency components. When designing an input filter circuit, be sure to take into account the interaction between the filter network and the input impedance of the ADS1220. Magnitude Sensor Signal Unwanted Signals Unwanted Signals Output Data Rate fMOD/2 fMOD Frequency fMOD Frequency fMOD Frequency Magnitude Digital Filter Aliasing of Unwanted Signals Output Data Rate fMOD/2 Magnitude Anti-Aliasing Filter Roll-Off Output Data Rate fMOD/2 Figure 58. Effect of Aliasing 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 VOLTAGE REFERENCE The ADS1220 offers an integrated low-drift, 2.048-V reference. For applications that require a different reference voltage value or a ratiometric measurement approach, the device offers two differential reference inputs (REFPx and REFNx). In addition, the analog supply (AVDD) can be used as a reference. The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are dedicated reference inputs whereas REFP1 and REFN1 are shared with inputs AIN0 and AIN3, respectively. The reference inputs are internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required when using an external reference and the reference inputs do not load any external circuitry when used in ratiometric applications. The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal reference is selected. CLOCK SOURCE The device system clock can either be provided by the internal low-drift oscillator or by an external clock source on the CLK input. Connect the CLK pin to DGND before power-up or reset to activate the internal oscillator. Connecting an external clock to the CLK pin at any time deactivates the internal oscillator after two rising edges on the CLK pin are detected. The device then operates on the external clock. After the ADS1220 switches to the external clock, the device cannot be switched back to the internal oscillator without cycling the power supplies or sending a RESET command. EXCITATION CURRENT SOURCES The ADS1220 provides two matched programmable excitation current sources (IDACs) for RTD applications. The output current of the current sources can be programmed to 10 μA, 50 μA, 100 μA, 250 μA, 500 μA, 1000 μA, or 1500 μA using the respective bits (IDAC[2:0]) in the configuration register. Each current source can be connected to any of the analog inputs (AINx) as well as to any of the dedicated reference inputs (REFP0 and REFN0). Both current sources can also be connected to the same pin. Routing of the IDACs is configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care should be taken not to exceed the compliance voltage of the IDACs. In other words, the voltage on the pin where the IDAC is routed to should be limited to ≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD applications, the matched current sources can be used to cancel the errors caused by sensor lead resistance. The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using bits IDAC[2:0]. If configuration register 2 and 3 are not written during the same WREG command, TI recommends to first set the IDAC current to the respective value using bits IDAC[2:0] and thereafter select the routing for each IDAC (I1MUX[2:0], I2MUX[2:0]). In single-shot mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is issued. SENSOR DETECTION To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources. When enabled by setting the respective bit (BCS) in the configuration register, one current source sources current to the positive analog input (AINP) currently selected and the other current source sinks current form the selected negative analog input (AINN). In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading may also indicate that the sensor is overloaded or that the reference voltage is absent. A near-zero reading may indicate a shorted sensor. However, because the absolute value of the burn-out current sources typically varies by ±10% and the internal multiplexer adds a small series resistance, distinguishing a shorted sensor condition from a normal reading can be difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor fails short, the voltage drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read a value higher than zero. If a higher precision current source is required for sensor short detection, TI recommends using the excitation current sources (IDACs). Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are enabled. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 27 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com LOW-SIDE POWER SWITCH A low-side power switch with low on-resistance connected between the analog input AIN3/REFN1 and AVSS is integrated in the ADS1220 as well. This power switch can be used to reduce system power consumption in bridge sensor applications by powering down the bridge circuit between conversions. When the respective bit (PSW) in the configuration register is set, the switch automatically closes during conversions and opens when the device is in power-down mode. By default, the switch is always open. SYSTEM MONITOR The device provides some means for monitoring the AVDD analog power supply and the external voltage reference. To select any monitoring voltages, the internal multiplexer (MUX[3:0]) must be configured accordingly in the configuration register. Note that the system monitor function only provides a coarse result and is not meant to be a precision measurement. When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD – AVSS) / 4. The device uses the internal reference for the measurement regardless of what reference source is selected in the configuration register (VREF[1:0]). When monitoring one of the two possible external reference voltage sources (MUX[3:0] = 1100), the result is approximately (REFPx – REFNx) / 4. REFPx and REFNx denote the external reference input pair selected in the configuration register (VREF[1:0]). The ADS1220 automatically uses the internal reference for the measurement. OFFSET CALIBRATION The internal multiplexer offers the option to short both PGA inputs (AINP and AINN) to mid-supply (AVDD + AVSS) / 2. This option can be used to calibrate the device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and consequently subtracting the result from each following reading. TI recommends taking multiple readings with the inputs shorted and averaging the result to reduce the effect of noise. POWER SUPPLIES The device has two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power supply can be bipolar (for example, AVDD = +2.5 V, AVSS = –2.5 V) or single supply (for example, AVDD = +3.3 V, AVSS = 0 V) and is independent of the digital power supply. The digital supply range sets the digital I/O levels. The power supplies can be sequenced in any order but in no case should any of the analog or digital inputs exceed the respective analog or digital power-supply voltage limits. 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 TEMPERATURE SENSOR The temperature measurement mode of the device is configured as a 14-bit result when enabled by the TS bit in the configuration register. Data are output starting with the most significant byte (MSB). When reading the three data bytes, the first 14 bits are used to indicate the temperature measurement result. The last 10 bits are random data and must be ignored. That is, the 14-bit temperature result is left-justified within the 24-bit conversion result. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format. Table 10. 14-Bit Temperature Data Format TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX 128 01 0000 0000 0000 1000 127.96875 00 1111 1111 1111 0FFF 100 00 1100 1000 0000 0C80 80 00 1010 0000 0000 0A00 75 00 1001 0110 0000 0960 50 00 0110 0100 0000 0640 25 00 0011 0010 0000 0320 0.25 00 0000 0000 1000 0008 0 00 0000 0000 0000 0000 –0.25 11 1111 1111 1000 3FF8 –25 11 1100 1110 0000 3CE0 –55 11 1001 0010 0000 3920 Converting from Temperature to Digital Codes For Positive Temperatures (for example, +50°C): Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 14-bit, left-justified format with the MSB = 0 to denote the positive sign. Example: (+50°C) / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000 For Negative Temperatures (for example, –25°C): Generate the twos complement of a negative number by complementing the absolute binary number and adding '1'. Then, denote the negative sign with the MSB = 1. Example: (|–25°C|) / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000 Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000 Converting from Digital Codes to Temperature To convert from digital codes to temperature, first check whether the MSB is a '0' or a '1'. If the MSB is a '0', simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract '1' from the result and complement all bits. Then, multiply the result by –0.03125°C. Example: The ADS1220 reads back 0960h: 0960h has an MSB = 0. (0960h) × (0.03125°C) = (2400) × (0.03125°C) = +75°C Example: The ADS1220 reads back 3CE0h: 3CE0h has an MSB = 1. Complement the result: 3CE0h → 0320h (0320h) × (–0.03125°C) = (800) × (–0.03125°C) = –25°C Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 29 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com RESET AND POWER-UP When the device powers up, a reset is performed. As part of the reset process, the device sets all bits in the configuration registers to the respective default settings. By default, the device is set to single-shot mode. After power-up, the device performs a single conversion using the default register settings and then enters a lowpower state. The power-up behavior is intended to prevent systems with tight power-supply requirements from encountering a current surge during power-up. CONVERSION MODES The device can be operated in one of two conversion modes that can be selected by the CM bit in the configuration register. These conversion modes are single-shot or continuous conversion mode. Single-Shot Mode In single-shot mode, the device only performs a conversion when a START/SYNC command is issued. The device consequently performs one single conversion and returns to a low-power state afterwards. The internal oscillator and all analog circuitry (except for the excitation current sources) are turned off while the device waits in this low-power state until the next conversion is started. In addition, every write access to any configuration register also starts a new conversion. Writing to any configuration register while a conversion is ongoing functions as a new START/SYNC command that stops the current conversion and restarts a single new conversion. Because the ADS1220 digital filter settles within a single cycle, each conversion is fully settled assuming the analog input signal is settled to its final value before the conversion starts. Continuous Conversion Mode In continuous conversion mode, the device continuously performs conversions. When a conversion completes, the device places the result in the output buffer and immediately begins another conversion. In order to start continuous conversion mode, the CM bit must be set to '1' followed by a START/SYNC command. The first conversion starts 210 × tCLK (normal mode, duty-cycle mode) or 114 × tCLK (turbo mode), respectively, after the last SCLK falling edge of the START/SYNC command. Writing to any configuration register while the START/SYNC command is not issued starts a single conversion, whereas a write access to the configuration register during an ongoing conversion restarts the current conversion. TI recommends to always send a START/SYNC command immediately after the CM bit is set to '1'. OPERATING MODES In addition to the different conversion modes, the ADS1220 can also be operated in different operating modes that can be selected to trade off power consumption, noise performance, and output data rate. Normal Mode Normal mode is the default mode the device operates in. In this mode, the internal modulator of the ΔΣ ADC runs at a modulator clock frequency of fMOD = fCLK / 16, where the system clock (fCLK) is either provided by the internal oscillator or the external clock source. The modulator frequency using the internal oscillator is 256 kHz. Normal mode offers output data rate options ranging from 20 SPS to 1 kSPS with the internal oscillator. The data rate is selected by bits (DR[2:0]) in the configuration register. In case an external clock source with a clock frequency other than 4.096 MHz is used, the data rates scale accordingly. For example, using an external clock with fCLK = 2.048 MHz yields data rates ranging from 10 SPS to 500 SPS. Duty-Cycle Mode The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator can be averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the device supports an internal duty cycling that can yield significant power savings by periodically entering a low-power state between conversions. In principle, the device runs in normal mode with a duty cycle of 25%. This functionality means the device performs one conversion in the same manner as when running in normal mode but then automatically enters a low power-state for three consecutive conversion cycles. The noise performance in duty-cycle mode is therefore comparable to the noise performance in normal mode at four times the data rate. Data rates in duty-cycle mode range from 5 SPS to 250 SPS with the internal oscillator. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 Turbo Mode Applications that require higher data rates up to 2 kSPS can operate the device in turbo mode. In this mode, the internal modulator runs at a higher frequency of fMOD = fCLK / 8. fMOD = 512 kHz when the internal oscillator or an external 4.096-MHz clock is used. Note that the device power consumption does increase because the modulator runs at a higher frequency. Power-Down Mode When the POWERDOWN command is issued, the device enters power-down mode after completing the current conversion. In this mode, all analog circuitry is powered down and the device typically only uses 400 nA of current. During this time, the device holds the configuration register settings and responds to commands, but does not perform any data conversion. Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous conversion mode depending on the conversion mode selected by the CM bit. Writing to any configuration register bit wakes up the device as well, but only starts a single conversion regardless of what conversion mode (CM) the device is set to. TI recommends to always send a START/SYNC command immediately after writing to any of the configuration registers. SERIAL INTERFACE The SPI-compatible serial interface of the device is used to read conversion data, read and write the device configuration registers, and control device operation. The interface consists of five control lines (CS, SCLK, DIN, DOUT/DRDY, and DRDY) but can be used with four or even three control signals (SCLK, DIN, and DOUT/DRDY) as well. In the latter case, CS may be tied low if the serial bus is not shared with any other device. The dedicated data-ready signal (DRDY) can be configured to be shared with DOUT/DRDY. CHIP SELECT (CS) Chip select (CS) is an active-low input that selects the device for SPI communication. This feature is useful when multiple devices share the same serial bus. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state; as such, DOUT/DRDY cannot indicate when data are ready. In situations where multiple devices are present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the result status. New data can be transferred at anytime without concern of data corruption. When a transmission starts, the current result is loaded into the output shift register and does not change until the communication is complete. This implementation avoids any possibility of data corruption. If the serial bus is not shared with another peripheral, CS may be tied low. SERIAL CLOCK (SCLK) The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data into and out of the device on the DIN and DOUT/DRDY pins, respectively. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. If a complete command is not sent within 13955 × tMOD (normal mode, duty-cycle mode) or 27910 × tMOD (turbo mode), respectively, the serial interface resets and the next SCLK pulse starts a new communication cycle. This timeout feature can be used to recover communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK low. DATA READY (DRDY) DRDY indicates when a new conversion result is ready for retrieval. When DRDY falls low, new conversion data are ready. DRDY always transitions high on the next SCLK rising edge. When no data are read during continuous conversion mode, DRDY remains low but pulses high 2 × tMOD before the next DRDY falling edge. The DRDY pin is always actively driven even when CS is high. DATA INPUT (DIN) The data input pin (DIN) is used along with SCLK to send data (commands and register data) to the device. The device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 31 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com DATA OUTPUT AND DATA READY (DOUT/DRDY) DOUT/DRDY has a dual output function. This pin is used with SCLK to read conversion and register data from the device but can, in addition, be configured as a data-ready indicator. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY goes to a high-impedance state when CS is high. Setting the DRDYM bit in the configuration register high also configures DOUT/DRDY as a data-ready indicator. DOUT/DRDY then transitions low at the same time the DRDY pin goes low to indicate new conversion data are available. Both signals can be used to detect if new data are ready. However, because DOUT/DRDY is disabled when CS is high, only the dedicated DRDY pin can be used in case multiple devices on the bus must be monitored for end of conversion. DATA FORMAT The device provides 24 bits of data in binary twos complement format. The positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale (FS). Table 11 summarizes the ideal output codes for different input signals. Table 11. Ideal Output Code versus Input Signal INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE (1) ≥ +FS (223 – 1) / 223 7FFFFFh 23 000001h 0 0 –FS / 223 FFFFFFh ≤ –FS 800000h +FS / 2 (1) Excludes the effects of noise, INL, offset, and gain errors. Mapping of the analog input signal to the output codes is illustrated in Figure 59. 7FFFFFh 000001h 000000h FFFFFFh ¼ Output Code ¼ 7FFFFEh 800001h 800000h ¼ -FS 2 23 -FS 2 0 ¼ FS Input Voltage (AINP - AINN) -1 23 2 23 FS 2 -1 23 Figure 59. Code Transition Diagram 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 COMMANDS The device offers six different commands to control device operation. Four commands are stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG) and write (WREG) configuration register data from and to the device require additional information as part of the instruction. Operands: rr = Configuration register (00 to 11) nn = Number of bytes – 1 (00 to 11) x = Don't care WREG (0100 rrnn) Writes the number of bytes specified by nn (number of bytes to be written – 1) to the device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are clocked in after the WREG command byte. The configuration registers are updated on the last SCLK falling edge. For example, the command to write two bytes (nn = 01) starting at configuration register 0 (rr = 00) is 0100 0001. RREG (0010 rrnn) Reads the number of bytes specified by nn (number of bytes to be read – 1) from the device configuration register, starting at register address rr. The command is completed after nn + 1 bytes are clocked out after the RREG command byte. For example, the command to read three bytes (nn = 10) starting at configuration register 1 (rr = 01) is 0010 0110. RESET (0000 011x) Resets the device to the default values. START/SYNC (0000 100x) In single-shot mode, the START/SYNC command is used to start a single conversion or when sent during an ongoing conversion, to reset the digital filter, and to restart a single new conversion. When the device is set to continuous conversion mode, the START/SYNC command must be issued to start converting. Sending the START/SYNC command while converting in continuous conversion mode resets the digital filter and starts converting from there. POWERDOWN (0000 001x) Places the device into power-down mode. This command shuts down all internal analog components, opens the low-side switch, turns off both IDACs, but holds all register values. As soon as a START/SYNC command is issued, all analog components return to their previous states. RDATA (0001 xxxx) Loads the output shift register with the most recent conversion result. This command can be used when DOUT/DRDY or DRDY are not monitored to indicate that a new conversion result is available. If a conversion finishes in the middle of the RDATA command byte, the more reliable result (either the old result or the new one) is loaded into the output shift register. The state of the DRDY pin signals whether the old or the new result is loaded. If the old result is loaded, DRDY stays low, indicating that the new result has not been read out. The new conversion result loads when DRDY is high. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 33 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com SENDING COMMANDS The device serial interface is capable of full-duplex operation, which means commands are decoded at the same time that conversion data are read. Commands may be sent on any 8-bit data boundary during a data read operation. When a RREG or RDATA command is recognized, the current data read operation is overridden and the data is corrupted, unless the command is sent together with the last byte of the data read operation. The device starts to output the requested data on DOUT/DRDY at the first SCLK rising edge after the command byte. To read data without interruption, keep DIN low. A WREG command can be sent without corrupting an ongoing read operation. Figure 60 shows an example for sending a WREG command to write two configuration registers while reading conversion data in continuous conversion mode. Note that after the command is clocked in (after the 32nd SCLK falling edge), the device resets the digital filter and starts converting using the new register settings. The WREG command can be sent on any of the 8-bit boundaries. That means on the first, ninth, 17th or 25th SCLK rising edge in Figure 60. Hi-Z DATA MSB 17 DATA 25 DATA LSB § DRDY 9 § § DOUT/DRDY 1 § § § § § SCLK § § CS Next Data Ready 2· tMOD REG_DATA REG_DATA § WREG § DIN Figure 60. Example of a WREG Command READING DATA Output pins DRDY and DOUT/DRDY (if configured in the respective DRDYM configuration register bit) transition low when new data are ready for retrieval. The conversion data are written to an internal data buffer. Data can be read directly from this buffer on DOUT/DRDY when DRDY falls low. A command does not have to be sent. Data are shifted out on the SCLK rising edges, MSB first, and consist of three bytes of data. Figure 61 to Figure 63 show the timing diagrams for continuous conversion mode and single-shot mode. Hi-Z DRDY 9 DATA MSB 17 DATA § § § § DOUT/DRDY 1 § § § § § SCLK § § CS DATA LSB Next Data Ready 2· tMOD § § DIN Figure 61. Continuous Conversion Mode (DRDYM = 0) DRDY Hi-Z 9 DATA MSB 17 DATA § § § § DOUT/DRDY 1 § § § § § SCLK § § CS DATA LSB Next Data Ready 2· tMOD § § DIN Figure 62. Continuous Conversion Mode (DRDYM = 1) 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 Hi-Z DRDY START/SYNC 9 DATA MSB 17 DATA DATA LSB Next Data Ready § § DIN 1 § § § § DOUT/DRDY 1 § § § § § SCLK § § CS Figure 63. Single-Shot Mode (DRDYM = 0) Data can also by read at any time without necessarily synchronizing to the DRDY signal using the RDATA command. When an RDATA command is issued, the conversion result currently stored in the data buffer can be shifted out on DOUT/DRDY on the following SCLK rising edge. Data can be read continuously with the RDATA command as an alternative to monitoring DRDY or DOUT/DRDY. The DRDY pin must then be polled after the LSB is clocked out to determine if a new conversion result is loaded. If a new conversion completes during the read operation but data from the previous conversion is read, then DRDY is low. Otherwise, if the most recent result is read, DRDY is high. Figure 64 and Figure 65 illustrate the behavior for both cases. Hi-Z DRDY 9 DATA MSB 17 DATA DATA LSB Next Data Ready § RDATA § DIN 1 § § § DOUT/DRDY 1 § § § § § SCLK § § CS Figure 64. State of DRDY when a New Conversion Finishes During an RDATA Command DRDY 9 DATA MSB 17 DATA RDATA DATA LSB Next Data Ready § § DIN Hi-Z 1 § § § § DOUT/DRDY 1 § § § § § SCLK § § CS Figure 65. State of DRDY when the Most Recent Conversion Result is Read During an RDATA Command Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 35 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com CONFIGURATION REGISTERS The device has four 8-bit configuration registers that are accessible via the SPI port. The configuration registers control how the device operates and can be changed at any time without causing data corruption. After power-up and reset, all registers are set to the default values (which are all '0'). Table 12 shows the register map of the configuration register. Table 12. Configuration Register Map (Read/Write) REGISTER (Hex) BIT 7 BIT 6 00h BIT 5 BIT 4 BIT 3 MUX[3:0] 01h VREF[1:0] 03h BIT 1 GAIN[2:0] DR[2:0] 02h BIT 2 MODE[1:0] 50/60 [1:0] I1MUX[2:0] PSW I2MUX[2:0] 00h Configuration Register 0 Bits [7:4] MUX[3:0]: Input multiplexer configuration CM BIT 0 PGA_BYPASS TS BCS IDAC[2:0] DRDYM RESERVED These bits configure the input multiplexer. No effect when in temperature sensor mode. For settings where AINN = AVSS, the PGA must be disabled (PGA_BYPASS = 1) and only gains 1, 2, and 4 can be used. 0000 : 0001 : 0010 : 0011 : 0100 : 0101 : 0110 : 0111 : Bits [3:1] AINP AINP AINP AINP AINP AINP AINP AINP = AIN0, AINN = AIN1 (default) = AIN0, AINN = AIN2 = AIN0, AINN = AIN3 = AIN1, AINN = AIN2 = AIN1, AINN = AIN3 = AIN2, AINN = AIN3 = AIN1, AINN = AIN0 = AIN3, AINN = AIN2 1000 : 1001 : 1010 : 1011 : 1100 : 1101 : 1110 : 1111 : AINP = AIN0, AINN = AVSS AINP = AIN1, AINN = AVSS AINP = AIN2, AINN = AVSS AINP = AIN3, AINN = AVSS (REFPx – REFNx) / 4 monitor (PGA bypassed) (AVDD – AVSS) / 4 monitor (PGA bypassed) AINP and AINN shorted to (AVDD + AVSS) / 2 Not used GAIN[2:0]: Gain configuration These bits configure the device gain. Gains 1, 2, and 4 can be used without the PGA. In this case, gain is obtained by a switched-capacitor structure. The gain setting has no effect when in temperature sensor mode. 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : Bit 0 Gain Gain Gain Gain Gain Gain Gain Gain = 1 (default) =2 =4 =8 = 16 = 32 = 64 = 128 PGA_BYPASS: Disables internal low-noise PGA Disabling the PGA reduces overall power consumption and allows the common-mode voltage range (VCM) to include AVSS and AVDD. The PGA can only be disabled for gains 1, 2, and 4. The PGA is always enabled for gain settings 8…128, regardless of the PGA_BYPASS setting. 0 : PGA enabled (default) 1 : PGA disabled and bypassed 36 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 01h Configuration Register 1 Bits [7:5] DR[2:0]: Data rate These bits control the data rate setting depending on the selected operating mode. Normal mode 000 : 20 SPS (default) 001 : 45 SPS 010 : 90 SPS 011 : 175 SPS 100 : 330 SPS 101 : 600 SPS 110 : 1000 SPS 111 : Not used Bits [4:3] Duty-cycle mode 000 : 5 SPS 001 : 11.25 SPS 010 : 22.5 SPS 011 : 44 SPS 100 : 82.5 SPS 101 : 150 SPS 110 : 250 SPS 111 : Not used Turbo mode 000 : 40 SPS 001 : 90 SPS 010 : 180 SPS 011 : 350 SPS 100 : 660 SPS 101 : 1200 SPS 110 : 2000 SPS 111 : Not used MODE[1:0]: Operating mode This bit controls the operating mode the device operates in. 00 01 10 11 Bit 2 : : : : Normal mode (256-kHz modulator clock) (default) Duty-cycle mode (internal duty cycle of 1:4) Turbo mode (512-kHz modulator clock) Not used CM: Conversion mode This bit sets the conversion mode for the device. 0 : Single-shot mode (default) 1 : Continuous conversion mode Bit 1 TS: Temperature sensor mode This bit enables the internal temperature sensor and puts the device in temperature sensor mode. 0 : Disables temperature sensor (default) 1 : Enables temperature sensor Bit 0 BCS: Burn-out current sources This bit controls the 10-µA, burn-out current sources to detect wire breaks and shorts in the sensor. 0 : Current sources off (default) 1 : Current sources on Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 37 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com 02h Configuration Register 2 Bits [7:6] VREF[1:0]: Voltage reference selection These bits select the voltage reference that is used for the conversion. 00 01 10 11 Bits [5:4] : : : : Internal 2.048-V reference selected (default) External reference selected using dedicated REFP0 and REFN0 inputs External reference selected using AIN0/REFP1 and AIN3/REFN1 inputs Analog supply AVDD used as reference 50/60[1:0]: FIR filter configuration Configures the filter coefficients for the internal FIR filter. Only affects 20-SPS setting in normal mode and 5-SPS setting in duty-cycle mode. 00 01 10 11 Bit [3] : : : : No 50-Hz or 60-Hz rejection (default) Simultaneous 50-Hz and 60-Hz rejection 50-Hz rejection only 60-Hz rejection only PSW: Low-side power switch configuration When enabled, the low-side switch connected to AIN3/REFN1 automatically opens when the device is in power-down mode. When the device is converting, the switch closes. 0 : Switch is always open (default) 1 : Switch closes during conversions Bits [2:0] IDAC[2:0]: IDAC current setting These bits set the current for both IDAC1 and IDAC2 excitation current sources. 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : 38 Off (default) 10 µA 50 µA 100 µA 250 µA 500 µA 1000 µA 1500 µA Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 03h Configuration Register 3 Bits [7:5] I1MUX[2:0]: IDAC1 routing configuration Selects the channel where IDAC1 is routed to. 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : Bits [4:2] IDAC1 disabled (default) IDAC1 connected to AIN0/REFP1 IDAC1 connected to AIN1 IDAC1 connected to AIN2 IDAC1 connected to AIN3/REFN1 IDAC1 connected to REFP0 IDAC1 connected to REFN0 Not used I2MUX[2:0]: IDAC2 routing configuration Selects the channel where IDAC2 is routed to. 000 : 001 : 010 : 011 : 100 : 101 : 110 : 111 : Bit 1 IDAC2 disabled (default) IDAC2 connected to AIN0/REFP1 IDAC2 connected to AIN1 IDAC2 connected to AIN2 IDAC2 connected to AIN3/REFN1 IDAC2 connected to REFP0 IDAC2 connected to REFN0 Not used DRDYM: DRDY mode Controls the behavior of the DOUT/DRDY pin when new data are ready. 0 : Only the dedicated DRDY pin is used to indicate when data are ready (default) 1 : Data ready is indicated simultaneously on DOUT/DRDY and DRDY Bit 0 Reserved Always write '0' Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 39 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com APPLICATION INFORMATION The following sections give example circuits and suggestions for using the ADS1220 in various situations. BASIC CONNECTIONS AND LAYOUT CONSIDERATIONS For many applications, connecting the ADS1220 is simple. Figure 66 shows the principle power-supply and interface connections for the ADS1220. GPIO/IRQ DVSS DVDD DIN 0.1 PF 47 O 47 O 47 O GPIO SCLK DOUT Microcontroller with SPI Interface 16 15 14 13 CS SCLK DIN DOUT/DRDY 3.3 V 1 CLK 2 DGND DRDY 12 DVDD 11 Device 3 AVSS 3.3 V 3.3 V 0.1 PF AVDD 10 REFN0 REFP0 AIN1 AIN0/REFP1 9 AIN2 4 AIN3/REFN1 5 6 7 8 0.1 PF Figure 66. Power-Supply and Interface Connections Most microcontroller SPI peripherals can operate with the ADS1220. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the ADS1220 can be found in the SPI Timing Characteristics. TI recommends to place 47-Ω resistors in series with all digital input pins (CS, SCLK, and DIN). This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to still meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines. Good power-supply decoupling is important to achieve optimum performance. Both AVDD and DVDD should be decoupled with at least a 0.1-μF bypass capacitor each. The bypass capacitors should be placed as close to the power-supply pins as possible with a low impedance connection. For very sensitive systems, or systems in harsh noise environments, avoiding the use of vias for connecting the bypass capacitor may offer superior bypass and noise immunity. 40 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 TI recommends employing best design practices when laying out a printed circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout should separate analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 67. While Figure 67 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog components. Microcontroller Device Ground fill or Ground plane Optional: Split Ground Cut Signal Conditioning (RC filters and amplifiers) Ground fill or Ground plane Optional: Split Ground Cut Ground fill or Ground plane Supply Generation Interface Tranceiver Connector or Antenna Ground fill or Ground plane Figure 67. System Component Placement The use of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground fill in PCB areas with no components is essential for optimum performance. If the system being used employs a split digital and analog ground plane, TI generally recommends that the ground planes be connected together as close to the ADS1220 as possible. TI also strongly recommends that digital components, especially RF portions, be kept as far as practically possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run through analog areas and avoid placing these traces near sensitive analog components. Digital return currents usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to a plane is not available, these currents may find paths back to the source that interfere with analog performance. The implications that layout has on the temperature sensing functions are much more significant than for ADC functions. CONNECTING MULTIPLE DEVICES When connecting multiple ADS1220 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective ADS1220, DOUT/DRDY enters a tri-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data are available if CS is high, regardless if bit DRDYM in the configuration register is set to '0' or '1'. Only the dedicated DRDY pin indicates that new data are available, because the DRDY pin is actively driven even when CS is high. In some cases, however, the DRDY pin cannot be interfaced to the microcontroller, perhaps because of insufficient GPIO channels on the microcontroller or because the serial interface must be galvanically isolated and thus the amount of channels has to be limited. Therefore, in order to evaluate when a new conversion of one of the devices is ready, the microcontroller can periodically drop CS to the respective ADS1220. When CS goes low, the DOUT/DRDY pin immediately drives either high or low, provided that bit DRDYM is configured to '1'. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out. If the DOUT/DRDY line drives high, no new data are available. Alternatively, valid data can be retrieved from the ADS1220 at any time without concern of data corruption by using the RDATA command. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 41 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com THERMOCOUPLE MEASUREMENT Figure 68 shows the basic connections of a thermocouple measurement system, using the internal high-precision temperature sensor for cold-junction compensation. Apart from the thermocouple itself, the only external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply decoupling capacitors. 3.3V 3.3V 0.1 PF 3.3V 0.1 PF REFP0 10 A to 1.5 mA CCM1 RB1 RF1 DVDD AVDD Internal Reference AIN0 REFN0 Reference Mux Device 24-bit ûADC Digital Filter and SPI Interface Low Drift Oscillator Precision Temp Sensor CDIF RF2 Thermocouple RB2 AIN1 Mux CCM2 PGA AIN2 AIN3 CLK AVSS CS SCLK DIN DOUT/DRDY DRDY DGND Figure 68. Thermocouple Measurement The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). In case the application requires the thermocouple to be biased to GND, a bipolar supply (for example, AVSS = –2.5 V and AVDD = +2.5 V) must be used for the ADS1220 to meet the common-mode voltage requirement. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple where it can cause self-heating and additional voltage drops in the thermocouple leads. In addition to biasing the thermocouple, RB1 and RB2 are also useful to detect an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs AIN0 and AIN1 to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition. While the digital filter of the ADS1220 attenuates high-frequency components of noise, TI generally recommends providing a first-order, passive RC filter at the inputs to further improve performance. The differential RC filter formed by RF1, RF2 and the differential capacitor CDIF offers a cutoff frequency of fC = 1 / (2π × RF1 × CDIF). Two common-mode filter capacitors CM1 and CM2 are also added to offer attenuation of high-frequency common-mode noise components. Because mismatches in the common-mode capacitors cause differential noise, TI recommends that the differential capacitor CDIF be at least an order of magnitude (10x) larger than the commonmode capacitors CM1 and CM2. The filter resistors RF1 and RF2 also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the ADS1220 to safe levels, should an overvoltage on the inputs occur. TI recommends limiting the filter resistor values to below 1 kΩ. Larger filter resistor values can lead to additional offset errors because of the voltage drops across them caused by the differential input currents of the ADS1220. The ADS1220 integrates a high-precision temperature sensor that can be used to measure the temperature of the cold junction. To measure the internal temperature of the ADS1220, the device must be set to internal temperature sensor mode by setting bit TS to '1' in the configuration register. For best performance, careful board layout is critical to achieve good thermal conductivity between the cold junction and the ADS1220 package. 42 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 However, the ADS1220 does not perform automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the ADS1220. The microcontroller requests one or multiple readings of the thermocouple voltage from the ADS1220 and then sets the device to internal temperature sensor mode (TS = 1) to acquire the temperature of the cold junction. The calculations to compensate for the cold-junction temperature must be implemented on the microcontroller. In some applications, the integrated temperature sensor cannot be used (for example, if the accuracy is not high enough or if the ADS1220 cannot be placed close enough to the cold junction). The additional analog input channels of the ADS1220 can be used in this case to measure the cold-junction temperature using a thermistor or RTD. RTD MEASUREMENT The ADS1220 integrates all necessary features (such as dual-matched programmable current sources, buffered reference inputs, PGA, and so forth) to ease the implementation of ratiometric 2-, 3-, and 4-wire RTD measurements. Figure 69 shows a typical implementation of a ratiometric 3-wire RTD measurement using the excitation current sources integrated in the ADS1220 to excite the RTD as well as to implement automatic RTD lead-resistance compensation. RFEF 3.3V RF3 CCM3 0.1 PF 10 A to 1.5 mA RLEAD3 RLEAD2 RF2 RLEAD1 RF1 CCM2 AVDD CDIF2 REFP0 Internal Reference AIN0 3.3V RF4 CCM4 0.1 PF REFN0 DVDD Reference Mux Device 24-bit ûADC Digital Filter and SPI Interface Low Drift Oscillator Precision Temp Sensor CDIF1 3-wire RTD AIN1 CCM1 Mux PGA IDAC1 IDAC2 AVSS CLK CS SCLK DIN DOUT/DRDY DRDY DGND Figure 69. 3-Wire RTD Measurement The circuit in Figure 69 employs a ratiometric measurement approach. In other words, the sensor signal (that is the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation source. Therefore, errors resulting from temperature drift or noise cancel out because these errors are common to both the sensor signal and the reference. In order to implement a ratiometric 3-wire RTD measurement using the ADS1220, IDAC1 is routed to one of the excitation leads of the RTD while IDAC2 is routed to the second excitation lead. Both currents have the same value, which is programmable by bits IDAC[2:0] in the configuration register. The design of the ADS1220 ensures that both IDAC values are closely matched, even across temperature. The sum of both currents flows through a low-drift reference resistor, RREF. The voltage, VREF, generated across the reference resistor is as shown in Equation 7. Because IDAC1 = IDAC2, Equation 8 is then used as the ADC reference voltage. VREF = (IDAC1 + IDAC2) × RREF VREF = 2 × IDAC1 × RREF (7) (8) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 43 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com Equation 9 assumes for the moment that the individual lead resistance values of the RTD (RLEADx) are zero. Only IDAC1 excites the RTD to produce a voltage VRTD, which is proportional to the temperature dependable RTD value and the IDAC1 value. VRTD = RRTD (Temperature) × IIDAC1 (9) The ADS1220 internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage against the reference voltage to produce a digital output code, which is proportional to Equation 10 to Equation 12: Code ∝ VRTD × PGA / VREF Code ∝ [RRTD (Temperature) × IIDAC1 × PGA] / [2 × IDAC1 × RREF] Code ∝ [RRTD (Temperature) × PGA] / [2 × RREF] (10) (11) (12) As can be seen from Equation 12, the output code only depends on the value of the RTD, the PGA gain and the reference resistor (RREF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current therefore does not matter. However, because the value of the reference resistor directly impacts the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced by the temperature drift of RREF. The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance. Also, IDAC1 and IDAC2 have the same value. Consequently, the differential voltage (VIN) across the ADC inputs, AIN0 and AIN1, is as shown in Equation 13: VIN = VAIN0 – VAIN1 = IIDAC1 × (RRTD + RLEAD1) – IIDAC2 × RLEAD2 (13) When RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, Equation 13 reduces to Equation 14: VIN = IIDAC1 × RRTD (14) In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is compensated, as long as the lead resistance values and the IDAC values are well matched. A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, CCM2) is placed on the ADC inputs, as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, CCM4). The same guidelines for designing the input filter apply as described in the Thermocouple Measurement section. For best performance, TI recommends to match the corner frequencies of the input and reference filter. More detailed information on matching the input and reference filter can be found in application report RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 (SBAA201). The reference resistor RREF not only serves to generate the reference voltage for the ADS1220, but also sets the common-mode voltage of the RTD to within the specified common-mode voltage range of the PGA. In other words, the voltage across the reference resistor must meet Equation 5. When designing the circuit, care should also be taken to meet the compliance voltage requirement of the IDACs. The IDACs require a minimum headroom of (AVDD – 0.9 V) in order to operate accurately. This requirement means that Equation 15 must be met at all times. AVSS + IIDAC1 × (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) × (RLEAD3 + RREF) ≤ AVDD – 0.9 V (15) The ADS1220 also offers the possibility to route the IDACs to the same inputs used for measurement. In case the filter resistor values RF1 and RF2 are small enough and well matched, IDAC1 can be routed to AIN1 and IDAC2 to AIN0, respectively, in Figure 69. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with a single ADS1220. Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement shown in Figure 69 except that only one IDAC is required. 44 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 ADS1220 www.ti.com SBAS501A – MAY 2013 – REVISED JULY 2013 HIGH-LEVEL CODE EXAMPLE The following list shows a high-level code sequence with steps necessary to set up the ADS1220 and the microcontroller interfacing to it, in order to take subsequent readings from the ADS1220 in continuous conversion mode. The dedicated DRDY pin is used to indicated availability of new conversion data. The default configuration register settings are changed to PGA = 16, continuous conversion mode, and simultaneous 50-Hz and 60-Hz rejection. • • • • • • • • • • • • • • • • Power-up Delay Configure the SPI interface of the microcontroller to SPI mode 1 If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an output Configure the microcontroller GPIO connected to the DRDY pin as an interrupt input Set CS to the ADS1220 low Delay Send the RESET command (06h) to make sure the ADS1220 is properly reset after power-up Write the respective register configuration using the WREG command (43h, 08h, 04h, 10h, and 00h) Delay Read back all configuration registers using the RREG command (23h) to make sure the correct values are written Delay Send the START/SYNC command (08h) to start converting in continuous conversion mode Delay Clear CS to high (resets the serial interface) Loop { Wait for DRDY to transition low Take CS low Delay Send 24 SCLK rising edges to read out conversion data on DOUT Delay Clear CS to high } • • • • • Take CS low Delay Send the POWERDOWN command (02h) to stop conversions and put the ADS1220 in power-down mode Delay Clear CS to high TI recommends running an offset calibration before performing any measurements or when changing the gain of the PGA. The internal offset of the ADS1220 can, for example, be measured by shorting the inputs to mid-supply (MUX[3:1] = 1110). The microcontroller then takes multiple readings from the ADS1220 with the inputs shorted and stores the average value in the microcontroller memory. When measuring the sensor signal, the microcontroller then subtracts the stored offset value from each ADS1220 reading to get an offset compensated result. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 45 ADS1220 SBAS501A – MAY 2013 – REVISED JULY 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2013) to Revision A • 46 Page Changed document status to Mixed Status; pre-RTM changes made throughout ............................................................... 1 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: ADS1220 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) ADS1220IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS1220 ADS1220IPWR ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS1220 ADS1220IRVAR PREVIEW VQFN RVA 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1220 ADS1220IRVAT PREVIEW VQFN RVA 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 1220 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS1220IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1220IPWR TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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