ADS130E08 www.ti.com SBAS574 – JULY 2012 Low-Cost, 8-Channel, Integrated Analog Front-End for Metering Applications Check for Samples: ADS130E08 FEATURES 1 • • 23 • • • • • • • • • • • • • • • • Eight Differential Current and Voltage Inputs Eight Low-Noise PGAs and Eight High-Resolution ADCs Exceeds Class 1.0 Performance CMRR: –110 dB Crosstalk: –105 dB THD: –108 dB Power: 750 µW/Channel Data Rates: 8 kSPS Programmable Gains (1, 2, and 8) DC Coupling: – Dual Supplies: +3 V to +5 V or +1.8 V to +3.6 V – Bipolar Supply: ±2.5 V Built-In Test Signals Fault Detection Comparators Four GPIO Pins Internal and External Reference Flexible Power-Down: STBY Mode SPI™ Data Interface Package: TQFP-64 (PAG) Operating Temperature Range: –40°C to +105°C The device incorporates commonly-required features in industrial metering applications. With high levels of integration and exceptional performance, the ADS130E08 enables the creation of scalable industrial power systems at significantly reduced size, power, and low overall cost. The ADS130E08 has a flexible input multiplexer per channel that can be independently connected to the internally-generated signals for test, temperature, and fault detection. The ADS130E08 operates at a data rate of 8 kSPS. Fault detection can be implemented internal to the device using the integrated comparators with digital-to-analog converter (DAC)controlled trigger levels. Multiple devices can be cascaded in high channel count systems in a daisy-chain configuration. These complete analog front-end (AFE) solutions are packaged in a TQFP-64 package and specified over the industrial temperature range of –40°C to +105°C. Current Sensing Channel 1 PGA û ADC Voltage Sensing Channel 2 PGA û ADC Current Sensing Channel 3 PGA û ADC Channel 4 PGA û ADC Line A Line B Voltage Sensing • Industrial Power Applications: – Three-Phase Metering – Industrial Applications Voltage Reference Oscillator Control and SPI Interface Channel 5 PGA û ADC Voltage Sensing Channel 6 PGA û ADC Fault Detection Current Sensing Channel 7 PGA û ADC Test Channel 8 PGA û ADC Current Sensing APPLICATIONS EMI Filters and Input MUX Device Line C Line N Voltage Sensing Op Amp DESCRIPTION The ADS130E08 is a multi-channel, simultaneous sampling, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a built-in programmable gain amplifier (PGA), internal reference, and an external oscillator interface. 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ADS130E08 SBAS574 – JULY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FAMILY AND ORDERING INFORMATION MAXIMUM SAMPLE RATE (kSPS) OPERATING TEMPERATURE RANGE PRODUCT PACKAGE OPTION NUMBER OF CHANNELS ADS130E08 TQFP-64 8 Class 1.0 8 –40°C to +105°C ADS131E04 TQFP-64 4 Class 0.1 64 –40°C to +105°C ADS131E06 TQFP-64 6 Class 0.1 64 –40°C to +105°C ADS131E08 TQFP-64 8 Class 0.1 64 –40°C to +105°C ACCURACY ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. VALUE UNIT –0.3 to +5.5 V DVDD to DGND –0.3 to +3.9 V AVSS to DGND –2.75 to +0.2 V VREF input to AVSS AVSS – 0.3 to AVDD + 0.3 V Analog input to AVSS AVDD to AVSS AVSS – 0.3 to AVDD + 0.3 V Digital input voltage to DVDD –0.3 to DVDD + 0.3 V Digital output voltage to DGND –0.3 to DVDD + 0.3 V Momentary 100 mA Continuous 10 mA Operating, TA –40 to +105 °C Storage, Tstg –60 to +150 °C Maximum junction, TJ +150 °C Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins ±1000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins ±500 V Input current Temperature Electrostatic discharge (ESD) ratings 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 ELECTRICAL CHARACTERISTICS Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. ADS130E08 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale differential input voltage (AINP – AINN) ±VREF / gain V See the Input Common-Mode Range subsection of the PGA Settings and Input Range section Input common-mode range CI Input capacitance 20 pF IIB Input bias current 2 nA 500 MΩ DC input impedance PGA PERFORMANCE Gain settings BW 1, 2, 8 Bandwidth See ADC PERFORMANCE DR Resolution No missing codes 16 Bits Data rate fCLK = 2.048 MHz 8 kSPS 89 dB CHANNEL PERFORMANCE (DC Performance) Dynamic range INL Integral nonlinearity EO Offset error G=1 G = 2 and 8 Full-scale with gain = 1, best fit 89 dB 3 ppm μV ±350 Offset error drift EG 86 Gain error Excluding voltage reference error Gain drift Excluding voltage reference drift Gain match between channels 0.6 μV/°C ±0.1 % of FS 3 ppm/°C 0.2 % of FS CHANNEL PERFORMANCE (AC Performance) CMRR Common-mode rejection ratio fCM = 50 Hz and 60 Hz –110 dB PSRR Power-supply rejection ratio fPS = 50 Hz and 60 Hz 80 dB Crosstalk fIN = 50 Hz and 60 Hz –105 dB Accuracy 1:3000 dynamic range with a 1-second measurement (VRMS / IRMS) 0.5 % SNR Signal-to-noise ratio fIN = 10-Hz input, –0.5 dBFs THD Total harmonic distortion 10 Hz, –0.5 dBFs 89 dB –108 dB ±30 mV AVDD = 3 V, VREF = (VREFP – VREFN) 2.5 V AVDD = 5 V, VREF = (VREFP – VREFN) 4 V AVSS V OPEN-CIRCUIT DETECT AND ALARM Comparator threshold accuracy EXTERNAL REFERENCE VI(ref) Reference input voltage VREFN Negative input VREFP Positive input AVSS + 2.5 Input impedance 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 V kΩ 3 ADS130E08 SBAS574 – JULY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. ADS130E08 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATIONAL AMPLIFIER Integrated noise 0.1 Hz to 100 Hz Noise density 2 kHz GBP Gain bandwidth product 50 kΩ || 10-pF load 100 kHz SR Slew rate 50 kΩ || 10-pF load 0.25 V/µs Load current 7 µVRMS 120 nV/√Hz 50 THD Total harmonic distortion CMIR Common-mode input range fIN = 100 Hz µA 70 AVSS + 0.7 Quiescent power consumption dB AVSS – 0.3 V 20 µA CONFIG3.VREF_4V = 0 2.4 V CONFIG3.VREF_4V = 1 4 V ±0.2 % INTERNAL REFERENCE VO Output voltage VREF accuracy Drift –40°C to +105°C Start-up time Settled to 0.2% 45 ppm/°C 150 ms Analog supply reading error 2 % Digital supply reading error 2 % From power-up to DRDY low 150 ms STANDBY mode 125 µs TA = +25°C 145 mV 490 μV/°C SYSTEM MONITORS Device wake up Temperature sensor Voltage reading Coefficient TEST SIGNAL Signal frequency fCLK / 221 See Register Map section for settings Signal voltage See Register Map section for settings Accuracy Hz fCLK / 220 Hz ±1 mV ±2 mV ±2 % CLOCK Nominal frequency Internal oscillator clock frequency 2.048 ±0.5 –40°C ≤ TA ≤ +105°C ±2.5 Internal oscillator start-up time 0.7 2.048 % μW 120 CLKSEL pin = 0 % μs 20 Internal oscillator power consumption External clock input frequency MHz TA = +25°C 2.25 MHz DIGITAL INPUT AND OUTPUT (DVDD = 1.8 V to 3.6 V) VIH Logic level, input voltage High 0.8 DVDD DVDD + 0.1 V Low –0.1 0.2 DVDD V High IOH = –500 µA VOL Logic level, output voltage Low IOL = +500 µA IIN Input current VIL VOH 4 0 V < VDigitalInput < DVDD Submit Documentation Feedback 0.9 DVDD –10 V 0.1 DVDD V +10 μA Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 ELECTRICAL CHARACTERISTICS (continued) Minimum and maximum specifications apply from –40°C to +105°C. Typical specifications are at +25°C. All specifications are at DVDD = 1.8 V, AVDD = 3 V, AVSS = 0 V, VREF = 2.4 V, external fCLK = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. ADS130E08 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.7 3 5.25 V 1.7 1.8 3.6 V 3.6 V POWER-SUPPLY REQUIREMENTS AVDD Analog supply DVDD Digital supply AVDD – AVSS AVDD – DVDD –2.1 SUPPLY CURRENT (Operational Amplifier Turned Off) IAVDD Normal operation IDVDD AVDD – AVSS = 3 V 1.8 mA AVDD – AVSS = 5 V 2.2 mA DVDD = 3.3 V 0.5 mA DVDD = 1.8 V 0.3 mA POWER DISSIPATION Normal mode Quiescent power dissipation (analog supply = 3 V) 6 Power-down mode Standby mode Normal mode Quiescent power dissipation (analog supply = 5 V) Power-down mode Standby mode 6.6 mW 10 µW 2 mW 11.5 mW 20 µW 4 mW TEMPERATURE Temperature range Specified –40 +105 °C Operating –40 +105 °C Storage –60 +150 °C THERMAL INFORMATION ADS130E08 THERMAL METRIC PAG (TQFP) UNITS 64 PINS θJA Junction-to-ambient thermal resistance 35 θJCtop Junction-to-case (top) thermal resistance 31 θJB Junction-to-board thermal resistance 26 ψJT Junction-to-top characterization parameter 0.1 ψJB Junction-to-board characterization parameter NA θJCbot Junction-to-case (bottom) thermal resistance NA °C/W Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 5 ADS130E08 SBAS574 – JULY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION TIMING CHARACTERISTICS tCLK CLK t CSSC 1 2 8 3 t DIHD t DIST t SPWL t SPWH t SCLK SCLK t CSH t SDECODE CS 1 2 t SCCS 3 t DOHD 8 t DOST DIN t CSDOZ t CSDOD DOUT Hi-Z Hi-Z NOTE: SPI settings are CPOL = 0 and CPHA = 1. Figure 1. Serial Interface Timing tDISCK2ST DAISY_IN SCLK MSBD1 1 2 tDISCK2HT LSBD1 3 152 153 154 155 tDOPD DOUT MSB LSB 'RQ¶W Care MSBD1 Figure 2. Daisy-Chain Interface Timing Timing Requirements For and 2.7 V ≤ DVDD ≤ 3.6 V PARAMETER DESCRIPTION tCLK Master clock period tCSSC CS low to first SCLK: setup time 1.7 V ≤ DVDD ≤ 2.0 V MIN MAX MIN MAX UNIT 414 514 414 514 ns 6 17 ns SCLK period 50 66.6 ns SCLK pulse width, high and low 15 25 ns tDIST DIN valid to SCLK falling edge: setup time 10 10 ns tDIHD Valid DIN after SCLK falling edge: hold time 10 11 ns tDOHD SCLK falling edge to invalid DOUT: hold time 10 10 tDOST SCLK rising edge to DOUT valid: setup time tCSH CS high pulse tCSDOD CS low to DOUT driven tSCCS tSCLK tSPWH, L 17 ns 32 ns 2 2 10 20 ns Eighth SCLK falling edge to CS high 4 4 tCLKs tSDECODE Command decode time 4 4 tCLKs tCSDOZ CS high to DOUT Hi-Z tDISCK2ST Valid DAISY_IN to SCLK rising edge: setup time 10 10 ns tDISCK2HT Valid DAISY_IN after SCLK rising edge: hold time 10 10 ns 6 10 Submit Documentation Feedback tCLKs 20 ns Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 PIN CONFIGURATION NC OPAMPOUT NC OPAMPN OPAMPP NC AVDD AVSS AVSS AVDD VCAP3 AVDD1 AVSS1 DGND DVDD DGND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PAG PACKAGE TQFP-64 (TOP VIEW) 8 41 DAISY_IN IN4N 9 40 SCLK IN4P 10 39 CS IN3N 11 38 START IN3P 12 37 CLK IN2N 13 36 RESET IN2P 14 35 PWDN IN1N 15 34 DIN IN1P 16 33 DGND AVSS TESTN TESTP 32 IN5P 31 GPIO1 RESV1 42 30 7 VCAP2 IN5N 29 DOUT NC 43 28 6 VCAP1 IN6P 27 GPIO2 NC 44 26 5 VCAP4 IN6N 25 GPIO3 VREFN 45 24 4 VREFP IN7P 23 GPIO4 AVSS 46 22 3 AVDD IN7N 21 DRDY AVDD 47 20 2 AVSS IN8P 19 DVDD AVDD 48 18 1 17 IN8N PIN ASSIGNMENTS NAME TERMINAL FUNCTION DESCRIPTION AVDD 19, 21, 22, 56, 59 Supply Analog supply AVDD1 54 Supply Charge pump analog supply AVSS 20, 23, 32, 57, 58 Supply Analog ground AVSS1 53 Supply Charge pump analog ground CLK 37 Digital input Master clock input CS 39 Digital input SPI chip select; active low DAISY_IN 41 Digital input Daisy-chain input DGND 33, 49, 51, 52 Supply Digital ground DIN 34 Digital input DOUT 43 Digital output SPI data in SPI data out DRDY 47 Digital output Data ready; active low DVDD 48, 50 Supply GPIO1 42 Digital input/output Digital power supply General-purpose input/output pin GPIO2 44 Digital input/output General-purpose input/output pin Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 7 ADS130E08 SBAS574 – JULY 2012 www.ti.com PIN ASSIGNMENTS (continued) 8 NAME TERMINAL FUNCTION GPIO3 45 Digital input/output DESCRIPTION General-purpose input/output pin GPIO4 46 Digital input/output General-purpose input/output pin IN1N 15 Analog input Differential analog negative input 1 IN1P 16 Analog input Differential analog positive input 1 IN2N 13 Analog input Differential analog negative input 2 IN2P 14 Analog input Differential analog positive input 2 IN3N 11 Analog input Differential analog negative input 3 IN3P 12 Analog input Differential analog positive input 3 IN4N 9 Analog input Differential analog negative input 4 IN4P 10 Analog input Differential analog positive input 4 IN5N 7 Analog input Differential analog negative input 5 IN5P 8 Analog input Differential analog positive input 5 IN6N 5 Analog input Differential analog negative input 6 IN6P 6 Analog input Differential analog positive input 6 IN7N 3 Analog input Differential analog negative input 7 IN7P 4 Analog input Differential analog positive input 7 IN8N 1 Analog input Differential analog negative input 8 IN8P 2 Analog input Differential analog positive input 8 NC 27, 29, 62, 64 — OPAMPN 61 Analog Op amp inverting input OPAMPOUT 63 Analog Op amp output OPAMPP 60 — PWDN 35 Digital input Power-down; active low RESET 36 Digital input System reset; active low RESV1 31 Digital input Reserved for future use; must tie to logic low (DGND) SCLK 40 Digital input SPI clock START 38 Digital input Start conversion TESTN 18 Analog output Internal test signal TESTP 17 Analog output Internal test signal VCAP1 28 VCAP2 30 VCAP3 VCAP4 No connection, leave floating Op amp noninverting input Analog input and output Analog bypass capacitor — Analog bypass capacitor 55 — Analog bypass capacitor 26 Analog output Analog bypass capacitor VREFN 25 Analog input Negative reference voltage VREFP 24 Analog input and output Positive reference voltage Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 TYPICAL CHARACTERISTICS All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. NOISE HISTOGRAM 5000 4000 Occurences 3000 2000 1000 0.9 0 1 G003 400 0.8 300 0.7 200 0.5 0.6 Time (s) 100 0.4 0 0.3 −100 0.2 −200 0.1 −300 0 −400 Input−Referred Noise (µV) INPUT-REFERRED NOISE 350 300 250 200 150 100 50 0 −50 −100 −150 −200 −250 −300 −350 Input−Referred Noise (µV) Figure 3. CMRR vs FREQUENCY THD vs FREQUENCY −75 AIN = AVDD − 0.3 V to AVSS + 0.3 V Total Harmonic Distortion (dB) Common−Mode Rejection Ratio (dB) −80 −90 −100 −110 −120 Gain = 1 Gain = 2 Gain = 8 −130 −140 10 100 Frequency (Hz) −85 −90 −95 −100 −105 −110 1000 Gain = 1 Gain = 2 Gain = 8 −80 10 100 Frequency (Hz) G005 Figure 5. POWER-SUPPLY REJECTION RATIO vs FREQUENCY G006 INL vs PGA GAIN 5 Gain = 1 Gain = 2 Gain = 8 4 Intergal Nonlinearity (ppm) 95 PSRR (dB) 1000 Figure 6. 100 90 85 80 Gain = 1 Gain = 2 Gain = 8 75 70 G004 Figure 4. 10 3 2 1 0 −1 −2 −3 −4 100 Frequency (Hz) 1000 G007 −5 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 Input (Normalized to Full−Scale) Figure 7. 0.8 1 G008 Figure 8. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 9 ADS130E08 SBAS574 – JULY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All plots are at TA = +25°C, AVDD = 3 V, AVSS = 0 V, DVDD = 1.8 V, internal VREFP = 2.4 V, VREFN = AVSS, external clock = 2.048 MHz, data rate = 8 kSPS, and gain = 1, unless otherwise noted. −2 −3 −4 −5 −6 THD FFT PLOT 0 −40°C +25°C +105°C PGA Gain = 1 THD = −109 dB SNR = 90 dB −20 −40 Amplitude (dBFS) Intergal Nonlinearity (ppm) INL vs TEMPERATURE 6 5 4 3 2 1 0 −1 −60 −80 −100 −120 −140 −160 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 Input (Normalized to Full−Scale) 0.8 −180 1 0 1000 2000 Frequency (Hz) G009 Figure 9. 3000 4000 G010 Figure 10. OFFSET vs PGA GAIN (Absolute Value) OFFSET DRIFT vs PGA GAIN 600 900 AVDD = 3 V AVDD = 5 V 500 AVDD = 3 V AVDD = 5 V 800 Offset Drift (nV/°C) 700 Offset (µV) 400 300 200 600 500 400 300 200 100 100 0 1 2 3 4 5 PGA Gain 6 7 0 8 1 2 3 4 5 PGA Gain G011 Figure 11. 6 7 8 G012 Figure 12. CHANNEL POWER 12 AVDD = 3 V AVDD = 5 V Power (mW) 10 8 6 4 2 0 0 1 2 3 4 5 6 Number of Channels Diasbled 7 8 G013 Figure 13. 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 OVERVIEW The ADS130E08 is a low-power, multichannel, simultaneously-sampling, 16-bit, delta-sigma (ΔΣ) analog-todigital converter (ADC) with an integrated programmable gain amplifier (PGA). This functionality make the ADS130E08 suitable for industrial power-metering applications. The ADS130E08 has a highly-programmable multiplexer that allows for temperature, supply, and input short measurements. PGA gain can be chosen from one of three settings (1, 2, and 8). The ADCs in the device offer a data rate of 8 kSPS. Communication to the device is accomplished using an SPI-compatible interface. The device provides four general-purpose IO (GPIO) pins for general use. Multiple devices can be synchronized using the START pin. The internal reference can be programmed to either 2.4 V or 4 V. Fault detection can be accomplished by using the integrated comparators, with programmable trigger-point settings. A detailed diagram of the ADS130E08 is shown in . V RE F P V RE F N AVD D AVD D1 Test Signal Temperature Fault Detect Supply Check D VDD Refer ence D RD Y IN1 P E MI F ilter û ADC1 P G A1 IN1 N S PI IN2 P E MI F ilter P G A2 û ADC2 E MI F ilter P G A3 û ADC3 CS S C LK DIN D OU T IN2 N IN3 P IN3 N C LK S E L IN4 P E MI F ilter IN4 N P G A4 û ADC4 P G A5 û ADC5 Control DGND C LK MU X GPIO1 IN5 P E MI F ilter GPIO2 GPIO3 IN5 N GPIO4 IN6 P E MI F ilter P G A6 û ADC6 E MI F ilter P G A7 û ADC7 E MI F ilter P G A8 IN6 N PW DN IN7 P R E S ET IN7 N S TAR T IN8 P û ADC8 IN8 N Operational A mplifi er AV S S AV S S1 OPAMPOUT OPAMPN OPAMPP DGND Figure 14. Functional Block Diagram Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 11 ADS130E08 SBAS574 – JULY 2012 www.ti.com THEORY OF OPERATION This section contains details of the ADS130E08 internal functional elements. The analog blocks are discussed first, followed by the digital interface. Blocks implementing power-specific functions are covered towards the end of this document. Throughout this document, fCLK denotes the CLK pin signal frequency, tCLK denotes the CLK pin signal period, fDR denotes the output data rate, tDR denotes the output data time period, and fMOD denotes the frequency at which the modulator samples the input. EMI FILTER An RC filter at the input acts as an electromagnetic interference (EMI) filter on all channels. The –3-dB filter bandwidth is approximately 3 MHz. INPUT MULTIPLEXER The ADS130E08 input multiplexers are very flexible and provide many configurable signal-switching options. shows a diagram of the multiplexer on a single channel of the device. VINP and VINN are separate for each of the eight blocks. This flexibility allows for significant device and sub-system diagnostics, calibration, and configuration. Switch settings for each channel are selected by writing the appropriate values to the CHnSET register (see the CHnSET: Individual Channel Settings (n = 1 to 8) Register in the Register Map section for details.) Device MUX INT_TEST TESTP INT_TEST MUX[2:0] = 101 TestP TempP MvddP (1) MUX[2:0] = 100 MUX[2:0] = 011 MUX[2:0] = 000 VINP MUX[2:0] = 001 EMI Filter (VREFP + VREFN) 2 MUX[2:0] = 000 VINN MvddN To PgaP (1) TempN MUX[2:0] = 001 To PgaN MUX[2:0] = 011 MUX[2:0] = 100 MUX[2:0] = 101 TestN INT_TEST TESTN INT_TEST (1) MVDD monitor voltage supply depends on channel number; see the Supply Measurements (MVDDP, MVDDN) section. Figure 15. Input Multiplexer Block for One Channel 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 Device Noise Measurements Setting CHnSET[2:0] = 001 sets the common-mode voltage of [(VREFP + VREFN) / 2] to both inputs of the channel. This setting can be used to test inherent device noise in the user system. Test Signals (TestP and TestN) Setting CHnSET[2:0] = 101 provides internally-generated test signals for use in sub-system verification at powerup. Test signals are controlled through register settings (see the CONFIG2: Configuration Register 2 subsection in the Register Map section for details). TEST_AMP controls the signal amplitude and TEST_FREQ controls switching at the required frequency. The test signals are multiplexed and transmitted out of the device at the TESTP and TESTN pins. A bit register (CONFIG2.INT_TEST = 0) deactivates the internal test signals so that the test signal can be driven externally. This feature allows the calibration of multiple devices with the same signal. Temperature Sensor (TempP, TempN) The ADS130E08 contains an on-chip temperature sensor. This sensor uses two internal diodes with one diode having a current density 16x that of the other, as shown in . The difference in diode current densities yields a difference in voltage that is proportional to absolute temperature. Temperature Sensor Monitor AVDD 1x 2x To MUX TempP To MUX TempN 8x 1x AVSS Figure 16. Temperature Sensor Measurement in the Input As a result of the low thermal resistance of the package to the printed circuit board (PCB), the internal device temperature tracks the PCB temperature closely. Note that self-heating of the ADS130E08 causes a higher reading than the temperature of the surrounding PCB. The scale factor of converts the temperature reading to degrees Celsius. Before using this equation, the temperature reading code must first be scaled to microvolts. Temperature (°C) = Temperature Reading (mV) - 168,000 mV 394 mV/°C + 25°C (1) Supply Measurements (MVDDP, MVDDN) Setting CHnSET[2:0] = 011 sets the channel inputs to different supply voltages of the device. For channels 1, 2, 5, 6, 7, and 8, (MVDDP – MVDDN) is [0.5(AVDD – AVSS)]; for channels 3 and 4, (MVDDP – MVDDN) is DVDD / 4. Note that to avoid saturating the PGA while measuring power supplies, the gain must be set to '1'. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 13 ADS130E08 SBAS574 – JULY 2012 www.ti.com ANALOG INPUT The ADS130E08 analog input is fully differential. Assuming PGA = 1, the input (INP – INN) can span between –VREF to +VREF. Refer to for an explanation of the correlation between the analog input and the digital codes. There are two general methods of driving the ADS130E08 analog input: single-ended or differential, as shown in and . Note that INP and INN are 180°C out-of-phase in the differential input method. When the input is singleended, the INN input is held at the common-mode voltage, preferably at mid-supply. The INP input swings around the same common voltage and the peak-to-peak amplitude is (common-mode + 1/2 VREF) and (commonmode – 1/2 VREF). When the input is differential, the common-mode is given by (INP + INN) / 2. Both INP and INN inputs swing from (common-mode + 1/2 VREF) to (common-mode – 1/2 VREF). For optimal performance, it is recommended that the ADS130E08 be used in a differential configuration. 1/2 VREF to +1/2 VREF VREF Peak-to-Peak Device Device Common Voltage Common Voltage VREF Peak-to-Peak a) Single-Ended Input b) Differential Input Figure 17. Methods of Driving the ADS130E08: Single-Ended or Differential CM + 1/2 VREF +1/2 VREF INP CM Voltage CM 1/2 VREF 1/2 VREF INN = CM Voltage t Single-Ended Inputs CM + 1/2 VREF INP +VREF CM Voltage CM 1/2 VREF INN VREF t Differential Inputs Common-Mode Voltage (Differential Mode) = (INP) + (INN) , Common-Mode Voltage (Single-Ended Mode) = INN 2 Input Range (Differential Mode) = (AINP – AINN) = 2 VREF Figure 18. Using the ADS130E08 in Single-Ended and Differential Input Modes 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 PGA SETTINGS AND INPUT RANGE The PGA is a differential input and output amplifier, as shown in . The PGA has three gain settings (1, 2, and 8) that can be set by writing to the CHnSET register (see the CHnSET: Individual Channel Settings (n = 1 to 8) Register in the Register Map section for details). The ADS130E08 has CMOS inputs and, therefore, has negligible current noise. shows the typical bandwidth values for various gain settings. Note that only shows small-signal bandwidth. For large signals, performance is limited by PGA slew rate. The PGA resistor string that implements the gain has 120 kΩ of resistance. This resistance provides a current path across the PGA outputs in the presence of a differential input signal. This current is in addition to the quiescent current specified for the device in the presence of a differential signal at the input. From MuxP PgaP R2 30 kΩ R1 60 kΩ (for Gain = 2) PgaN To ADC R2 30 kΩ From MuxN Figure 19. PGA Implementation Table 1. PGA Gain versus Bandwidth GAIN NOMINAL BANDWIDTH AT ROOM TEMPERATURE (kHz) 1 237 2 146 8 48 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 15 ADS130E08 SBAS574 – JULY 2012 www.ti.com Input Common-Mode Range The usable input common-mode range of the analog front-end depends on various parameters, including the maximum differential input signal, supply voltage, and PGA gain. describes this range. Gain VMAX_DIFF Gain VMAX_DIFF AVDD - 0.2 > CM > AVSS + 0.2 + 2 2 where: VMAX_DIFF = maximum differential signal at the PGA input CM = common-mode range (2) For example: If VDD = 3.3 V, gain = 2, and VMAX_DIFF = 1000 mV, Then 1.2 V < CM < 2.1 V Input Differential Dynamic Range The differential (INP – INN) signal range depends on the analog supply and reference used in the system. shows this range. VREF ±VREF 2 VREF Max (INP - INN) < ; Full-Scale Range = = Gain Gain Gain (3) For higher dynamic range, a 5-V supply with a 4-V reference (set by the VREF_4V bit of the CONFIG3: Configuration Register 3) can be used to increase the differential dynamic range. ADC ΔΣ Modulator Power Spectral Density (dB) Each ADS130E08 channel has a 16-bit, ΔΣ ADC. This converter uses a second-order modulator optimized for low-power applications. The modulator samples the input signal at the rate of fMOD = fCLK / 8. As in the case of any ΔΣ modulator, the ADS130E08 noise is shaped until fMOD / 2, as shown in . The on-chip digital decimation filters also provide antialias filtering. This feature of the ΔΣ converters drastically reduces the complexity of analog antialiasing filters typically required with nyquist ADCs. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 0.001 0.01 0.1 Normalized Frequency (fIN/fMOD) 1 G001 Figure 20. Modulator Noise Spectrum Up To 0.5 × fMOD 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 DIGITAL DECIMATION FILTER The digital filter receives the modulator output and decimates the data stream. A fixed sample rate of 8 kSPS, for all eight channels, is provided for simplicity. The digital filter on each channel consists of a third-order sinc filter. Sinc Filter Stage (sinx / x) The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. The sinc filter attenuates the high-frequency noise of the modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of the converter. shows the scaled Z-domain transfer function of the sinc filter. ½H(z)½ = 1 - Z- N 3 1 - Z- 1 (4) The frequency domain transfer function of the sinc filter is shown in . sin ½H(f)½ = Npf fMOD N ´ sin 3 pf fMOD where: N = decimation ratio (5) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 17 ADS130E08 SBAS574 – JULY 2012 www.ti.com 0 0 -20 -0.5 -40 -1 Gain (dB) Gain (dB) The sinc filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. shows the sinc filter frequency response and shows the sinc filter roll-off. With a step change at the input, the filter takes 3 tDR to settle. After a START signal rising edge, the filter takes tSETTLE time to output settled data. The settling time of the filters at various data rates is discussed in the START subsection of the SPI Interface section. and show the filter transfer function until fMOD / 2 and fMOD / 16, respectively, at different data rates. shows the transfer function extended until 4 fMOD. The ADS130E08 passband repeats at every fMOD. The input R-C antialiasing filters in the system should be chosen such that any interference in frequencies around multiples of fMOD is attenuated sufficiently. -60 -80 -1.5 -2 -100 -2.5 -120 -3 -140 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.05 0.1 Normalized Frequency (fIN/fDR) 0.25 0.3 0.35 Figure 22. Sinc Filter Roll-Off 0 0 −20 −20 −40 −40 −60 Gain (dB) Gain (dB) 0.2 Normalized Frequency (fIN/fDR) Figure 21. Sinc Filter Frequency Response −80 −100 −60 −80 −100 −120 −120 −140 −160 0.15 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Normalized Frequency (fIN/fMOD) G023 Figure 23. Transfer Function of On-Chip Decimation Filters Until fMOD / 2 −140 0 0.01 0.02 0.03 0.04 0.05 Normalized Frequency (fIN/fMOD) 0.06 0.07 G024 Figure 24. Transfer Function of On-Chip Decimation Filters Until fMOD / 16 0 −20 Gain (dB) −40 −60 −80 −100 −120 −140 0 0.5 1 1.5 2 2.5 3 Normalized Frequency (fIN/fMOD) 3.5 4 G025 Figure 25. Transfer Function of On-Chip Decimation Filters Until 4 fMOD for DR[2:0] = 000 and DR[2:0] = 110 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 REFERENCE shows a simplified block diagram of the ADS130E08 internal reference. The reference voltage is generated with respect to AVSS. When using the internal voltage reference, connect VREFN to AVSS. 22 F VCAP1 R1 (1) Bandgap 2.4 V or 4 V R3 VREFP (1) 100 F R2 (1) VREFN AVSS To ADC Reference Inputs (1) For VREF = 2.4 V: R1 = 12.5 kΩ, R2 = 25 kΩ, and R3 = 25 kΩ. For VREF = 4 V: R1 = 10.5 kΩ, R2 = 15 kΩ, and R3 = 35 kΩ. Figure 26. Internal Reference The external band-limiting capacitors determine the amount of reference noise contribution. For high-end systems, the capacitor values should be chosen such that the bandwidth is limited to less than 10 Hz so that the reference noise does not dominate system noise. When using a 3-V analog supply, the internal reference must be set to 2.4 V. In case of a 5-V analog supply, the internal reference can be set to 4 V by setting the VREF_4V bit in the CONFIG2: Configuration Register 2. Alternatively, the internal reference buffer can be powered down and VREFP can be driven externally. shows a typical external reference driver circuitry. Power-down is controlled by the PD_REFBUF bit in the CONFIG3: Configuration Register 3. This power-down is also used to share internal references when two devices are cascaded. By default, the device wakes up in external reference mode. 100 kΩ 10 pF +5 V 0.1 µF 100 Ω OPA211 100 Ω +5 V VIN 22 µF REF5025 TRIM To VREFP Pin 10 µF OUT 0.1 µF 100 µF 22 µF Figure 27. External Reference Driver Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 19 ADS130E08 SBAS574 – JULY 2012 www.ti.com CLOCK The ADS130E08 provides two device clocking methods: internal and external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room temperature. Accuracy varies over the specified temperature range; refer to the Electrical Characteristics for details. Clock selection is controlled by the CLKSEL pin and CLK_EN register bit. The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables and disables the oscillator clock to be output in the CLK pin. A truth table for these pins is shown in . The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. During power-down, the external clock is recommended to be shut down to save power. Table 2. CLKSEL Pin and CLK_EN Bit CLKSEL PIN CONFIG1.CLK_EN BIT CLOCK SOURCE CLK PIN STATUS 0 X External clock Input: external clock 1 0 Internal clock oscillator 3-state 1 1 Internal clock oscillator Output: internal clock oscillator DATA FORMAT The ADS130E08 outputs 16 bits of data per channel in binary twos complement format, MSB first. The LSB has a weight of [VREF / (215 – 1)]. A positive full-scale input produces an output code of 7FFFh and the negative fullscale input produces an output code of 8000h. The output clips at these codes for signals exceeding full-scale. summarizes the ideal output codes for different input signals. Table 3. Ideal Output Code versus Input Signal INPUT SIGNAL, VIN (AINP – AINN) IDEAL OUTPUT CODE ≥ VREF 7FFFh +VREF / (215 – 1) 0001h 0 0000h –VREF / (215 – 1) FFFFh ≤ –VREF (215 / 215 – 1) 8000h SPI INTERFACE The SPI-compatible serial interface consists of four signals: CS, SCLK, DIN, and DOUT. The interface reads conversion data, reads and writes registers, and controls device operation. The DRDY output is used as a status signal to indicate when data are ready. DRDY goes low when new data are available. Chip Select (CS) CS selects the ADS130E08 for SPI communication. CS must remain low for the entire serial communication duration. After the serial communication is finished, always wait four or more tCLK cycles before taking CS high. When CS is taken high, the serial interface is reset, SCLK and DIN are ignored, and DOUT enters a highimpedance state. DRDY asserts when data conversion is complete, regardless of whether CS is high or low. Serial Clock (SCLK) SCLK is the serial peripheral interface (SPI) serial clock. SCLK shifts commands in and shifts data out from the device. The serial clock features a Schmitt-triggered input and clocks data on the DIN and DOUT pins into and out of the ADS130E08. Care should be taken to prevent glitches on SCLK while CS is low. Glitches as small as 1 ns wide could be interpreted as a valid serial clock. After eight serial clock events, the ADS130E08 assumes an instruction must be interrupted and executed. If it is suspected that instructions are being interrupted erroneously, toggle CS high and back low to return the chip to normal operation. Issuing serial clocks in multiples of eight is also recommended. The absolute maximum SCLK limit is specified in the Serial Interface Timing table. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 For a single device, the minimum speed needed for SCLK depends on the number of channels, number of bits of resolution, and output data rate. (For multiple cascaded devices, see the Standard Mode subsection of the Multiple Device Configuration section.) For example, at 8 kSPS, the minimum serial clock rate must be 1.3 MHz. Data can be retrieved either by putting the device in RDATAC mode or by issuing an RDATA command for data on demand. The SCLK rate limitation, as described by , applies to RDATAC mode. For the RDATA command, the limitation applies if data must be read in between two consecutive DRDY signals. assumes that there are no other commands issued in between data captures. tDR - 4 tCLK tSCLK < 152 (6) Data Input (DIN) The data input pin (DIN) is used along with SCLK to communicate with the ADS130E08 (using opcode commands and register data). The device latches data on DIN on the SCLK falling edge. Data Output (DOUT) The data output pin (DOUT) is used with SCLK to read conversions and register data from the ADS130E08. Data on DOUT are shifted out on the SCLK rising edge. DOUT goes to a high-impedance state when CS is high. In read data continuous mode (see the SPI Command Definitions section for more details), the DOUT output line also indicates when new data are available. This feature can be used to minimize the number of connections between the device and system controller. shows the data output protocol for the ADS130E08. DRDY CS SC LK 152 SCLKS DOUT STAT CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 24-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit 16-Bit DIN Figure 28. SPI Bus Data Output Data Retrieval Data retrieval can be accomplished in one of two methods. The read data continuous command (see the RDATAC: Read Data Continuous section) can be used to set the device in a mode to read data continuously without sending opcodes. The read data command (see the RDATA: Read Data section) can be used to read just one data output from the device (see the SPI Command Definitions section for more details). Conversion data are read by shifting data out on DOUT. The MSB of the data on DOUT is clocked out on the first SCLK rising edge. DRDY returns to high on the first SCLK falling edge. DIN should remain low for the entire read operation. The number of bits in the data output depends on the number of channels and the number of bits per channel. For the ADS130E08, the number of data outputs is [(24 status bits + 16 bits × 8 channels) = 152 bits]. The format of the 24 status bits is (1100 + FAULT_STATP + FAULT_STATN + bits[7:4] of the GPIO: GeneralPurpose IO Register). The data format for each channel data is twos complement, MSB first. When channels are powered down using user register settings, the corresponding channel output is set to '0'. However, the channel output sequence remains the same. The ADS130E08 also provides a multiple readback feature. Data can be read out multiple times by simply giving more SCLKs, in which case the MSB data byte repeats after reading the last byte. The DAISY_IN bit in the CONFIG1: Configuration Register 1 must be set to '1' for multiple readbacks. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 21 ADS130E08 SBAS574 – JULY 2012 www.ti.com Data Ready (DRDY) DRDY is an output. When DRDY transitions low, new conversion data are ready. The CS signal has no effect on the data ready signal. DRDY behavior is determined by whether the device is in RDATAC mode or the RDATA command is being used to read data on demand. (See the RDATAC: Read Data Continuous and RDATA: Read Data subsections of the SPI Command Definitions section for further details). When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption. The START pin or the START command is used to place the device either in normal data capture mode or pulse data capture mode. shows the relationship between DRDY, DOUT, and SCLK during data retrieval. DOUT is latched out at the SCLK rising edge; DRDY is pulled high at the SCLK falling edge. Note that DRDY goes high on the first SCLK falling edge, regardless of whether data are being retrieved from the device or a command is being sent through the DIN pin. DRDY DOUT Bit 151 Bit 150 Bit 149 SCLK Figure 29. DRDY with Data Retrieval (CS = 0) GPIO The ADS130E08 has a total of four general-purpose digital input and output (GPIO) pins available in the normal mode of operation. The digital IO pins are individually configurable as either inputs or outputs through the GPIOC bits register. The GPIOD bits in the GPIO: General-Purpose IO Register control the level of the pins. When reading the GPIOD bits, the data returned are the logic level of the pins, whether they are programmed as inputs or outputs. When the GPIO pin is configured as an input, a write to the corresponding GPIOD bit has no effect. When configured as an output, a write to the GPIOD bit sets the output value. If configured as inputs, these pins must be driven (do not float). The GPIO pins are set as inputs after power-on or after a reset. shows the GPIO port structure. The pins should be shorted to DGND if not used. GPIO Data (Read) GPIO Pin GPIO Data (Write) GPIO Control Figure 30. GPIO Port Pin Power-Down (PWDN) When PWDN is pulled low, all on-chip circuitry is powered down. To exit power-down mode, take the PWDN pin high. Upon exiting from power-down mode, the internal oscillator and reference require time to wake up. During power-down, the external clock is recommended to be shut down to save power. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 Reset (RESET) There are two methods to reset the ADS130E08: pulling the RESET pin low, or sending the RESET opcode command. When using the RESET pin, take the pin low to force a reset. Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high. The RESET command takes effect on the eighth SCLK falling edge of the opcode command. On reset, 18 tCLK cycles are required to complete initialization of the configuration registers to the default states and start the conversion cycle. Note that an internal RESET is automatically issued to the digital filter whenever the CONFIG1 Register is set to a new value with a WREG command. START The START pin must be set high or the START command sent to begin conversions. When START is low or if the START command has not been sent, the device does not issue a DRDY signal (conversions are halted). When using the START opcode to control conversions, hold the START pin low. In multiple device configurations the START pin is used to synchronize devices (see the Multiple Device Configuration subsection of the SPI Interface section for more details). Settling Time The settling time (tSETTLE) is the time required for the converter to output fully-settled data when the START signal is pulled high. When START is pulled high, DRDY is also pulled high. The next DRDY falling edge indicates that data are ready. shows the timing diagram and shows the data rate settling time. The settling time depends on fCLK and is 1160 tCLK. Note that when START is held high and there is a step change in the input signal, 3 tDR is required for the filter to settle to the new value. Settled data are available on the fourth DRDY pulse. t SETTLE START Pin or DIN START Opcode t DR 4/f CLK DRDY Figure 31. Settling Time Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 23 ADS130E08 SBAS574 – JULY 2012 www.ti.com Continuous Mode Conversions begin when the START pin is taken high or when the START opcode command is sent. As seen in , the DRDY output goes high when conversions are started and then goes low when data are ready. Conversions continue indefinitely until the START pin is taken low or the STOP opcode command is transmitted. When the START pin is pulled low or the stop command is issued, the conversion in progress is allowed to complete. and show the required DRDY timing to the START pin and the START and STOP opcode commands when controlling conversions in this mode. To keep the converter running continuously, the START pin can be permanently tied high. START Pin or DIN or STOP(1) Opcode START(1) Opcode tDR DRDY (1) tSETTLE START and STOP opcode commands take effect on the seventh SCLK falling edge. Figure 32. Continuous Conversion Mode tSDSU DRDY and DOUT tDSHD START Pin or STOP Opcode (1) STOP(1) STOP(1) START and STOP commands take effect on the seventh SCLK falling edge at the end of the opcode transmission. Figure 33. START to DRDY Timing Table 4. Timing Characteristics for SYMBOL 24 MIN UNIT tSDSU START pin low or STOP opcode to DRDY setup time to halt further conversions DESCRIPTION 16 1/fCLK tDSHD START pin low or STOP opcode to complete current conversion 16 1/fCLK Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 MULTIPLE DEVICE CONFIGURATION The ADS130E08 is designed to provide configuration flexibility when multiple devices are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one additional chip select signal per device, multiple devices can be connected together. The number of signals needed to interface n devices is 3 + n. When using multiple devices, the devices can be synchronized with the START signal. The delay from START to the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more details on settling times). shows the behavior of two devices when synchronized with the START signal. There are two ways to connect multiple devices with an optimal number of interface pins: cascade mode and daisy-chain mode. Device START CLK START1 DRDY DRDY1 CLK Device START2 DRDY DRDY2 CLK CLK START DRDY1 DRDY2 Figure 34. Synchronizing Multiple Converters Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 25 ADS130E08 SBAS574 – JULY 2012 www.ti.com Cascade Mode a shows a configuration with two devices cascaded together. Both devices are an ADS130E08 device. Together, the devices create a system with 16 channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected by the corresponding CS being driven to logic '1', the DOUT of this device is high-impedance. This structure allows the other device to take control of the DOUT bus. This configuration method is suitable for the majority of applications. Daisy-Chain Mode Daisy-chain mode is enabled by setting the DAISY_IN bit in the CONFIG1: Configuration Register 1. b shows the daisy-chain configuration. In this mode SCLK, DIN, and CS are shared across multiple devices. The DOUT pin of one device is connected to the DAISY_IN of the other device, thereby creating a chain. One extra SCLK must be issued between each data set. Also, when using daisy-chain mode, the multiple readback feature is not available. Short the DAISY_IN pin to digital ground if not used. describes the required timing for the ADS130E08 shown in . Data from the ADS130E08 appear first on DOUT, followed by a don’t care bit, and finally by the status and data words from the second ADS130E08 device. When all devices in the chain operate in the same register setting, DIN can be shared as well. This configuration reduces the SPI communication signals to four, regardless of the number of devices. START(1) CLK START CLK DRDY CS INT GPO0 START(1) CLK START CLK DRDY INT CS GPO SCLK SCLK GPO1 Device 0 SCLK SCLK DIN MOSI DOUT0 MISO Device 0 DIN MOSI DAISY_IN0 DOUT0 MISO Host Processor START CLK Host Processor DOUT1 DRDY CS START SCLK CS SCLK CLK DIN Device 1 DRDY DIN DOUT1 Device 1 DAISY_IN1 a) Standard Configuration 0 b) Daisy-Chain Configuration (1) To reduce pin count, set the START pin low and use the START serial command to synchronize and start conversions. Figure 35. Multiple Device Configurations 26 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 Note that from , the SCLK rising edge shifts data out of the ADS130E08 on DOUT. The SCLK rising edge is also used to latch data into the device DAISY_IN pin down the chain. This architecture allows for a faster SCLK rate speed, but also makes the interface sensitive to board-level signal delays. The more devices in the chain, the more challenging it can become to adhere to setup and hold times. An SCLK star-pattern connection to all devices, minimizing DOUT length, and other printed circuit board (PCB) layout techniques helps. Placing delay circuits (such as buffers) between DOUT and DAISY_IN also helps mitigate this challenge. One other option is to insert a D flip-flop between DOUT and DAISY_IN clocked on an inverted SCLK. Also note that daisy-chain mode requires some software overhead to recombine data bits spread across byte boundaries. shows a timing diagram for daisy-chain mode. DOUT1 MSB1 DAISY_IN0 CLKS DOUT 1 0 LSB1 2 3 152 MSB0 153 LSB0 154 XX Data From First Device (ADS130E08) 155 MSB1 LSB1 Data From Second Device (ADS130E08) Figure 36. Daisy-Chain Timing The maximum number of devices that can be daisy-chained depends on the data rate at which the device is operated at. The maximum number of devices can be approximately calculated with . fSCLK NDEVICES = 152 ´ fDR (7) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 27 ADS130E08 SBAS574 – JULY 2012 www.ti.com SPI COMMAND DEFINITIONS The ADS130E08 provides flexible configuration control. The opcode commands summarized in control and configure device operation. The opcode commands are stand-alone, except for the register read and write operations that require a second command byte plus data. CS can be taken high or held low between opcode commands but must stay low for the entire command operation (especially for multibyte commands). System opcode commands and the RDATA command are decoded by the ADS130E08 on the seventh SCLK falling edge. The register read and write opcodes are decoded on the eighth SCLK falling edge. Be sure to follow SPI timing requirements when pulling CS high after issuing a command. Table 5. Command Definitions COMMAND DESCRIPTION FIRST BYTE SECOND BYTE System Commands WAKEUP Wake-up from standby mode 0000 0010 (02h) STANDBY Enter standby mode 0000 0100 (04h) RESET Reset the device 0000 0110 (06h) START Start or restart (synchronize) conversions 0000 1000 (08h) STOP Stop conversion 0000 1010 (0Ah) Data Read Commands RDATAC Enable Read Data Continuous mode. This mode is the default mode at power-up. 0001 0000 (10h) SDATAC Stop Read Data Continuously mode 0001 0001 (11h) RDATA Read data by command; supports multiple readback. 0001 0010 (12h) Register Read Commands RREG Read n nnnn registers starting at address r rrrr 001r rrrr (2xh) 000n nnnn WREG Write n nnnn registers starting at address r rrrr 010r rrrr (4xh) 000n nnnn WAKEUP: Exit STANDBY Mode This opcode exits the low-power standby mode; see the STANDBY: Enter STANDBY Mode subsection of the SPI Command Definitions section. Time is required when exiting standby mode (see the Electrical Characteristics for details). There are no SCLK rate restrictions for this command and it can be issued at any time. The next command must be sent after a delay of 4 tCLK cycles. STANDBY: Enter STANDBY Mode This opcode command enters the low-power standby mode. All parts of the circuit are shut down except for the reference section. The standby mode power consumption is specified in the Electrical Characteristics. There are no SCLK rate restrictions for this command and it can be issued at any time. Do not send any other commands other than the wakeup command after the device enters standby mode. RESET: Reset Registers to Default Values This command resets the digital filter cycle and returns all register settings to the default values. See the Reset (RESET) subsection of the SPI Interface section for more details. There are no SCLK rate restrictions for this command and it can be issued at any time. 18 tCLK cycles are required to execute the RESET command. Avoid sending any commands during this time. START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress, this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, then a gap of 4 tCLK cycles must be between them. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the START subsection of the SPI Interface section for more details.) There are no SCLK rate restrictions for this command and it can be issued at any time. 28 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no SCLK rate restrictions for this command and it can be issued at any time. RDATAC: Read Data Continuous This opcode enables conversion data output on each DRDY without the need to issue subsequent read data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read data continuous mode is the device default mode; the device defaults to this mode on power-up. RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. There is no SCLK rate restriction for this command. However, the subsequent data-retrieval SCLKs or the SDATAC opcode command should wait at least 4 tCLK cycles for the command to execute. RDATAC timing is shown in . As shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after the RDATAC command is issued, make sure either the START pin is high or the START command is issued. shows the recommended way to use the RDATAC command. RDATAC is ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to be reconfigured. START DRDY (1) t UPDATE CS SCLK RDATAC Opcode DIN Hi-Z DOUT Status Register + n-Channel Data Next Data (1) tUPDATE = 4 / fCLK. Do not read data during this time. Figure 37. RDATAC Usage Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 29 ADS130E08 SBAS574 – JULY 2012 www.ti.com SDATAC: Stop Read Data Continuous This opcode cancels the Read Data Continuous mode. There is no SCLK rate restriction for this command, but the next command must wait 4 tCLK cycles to execute. RDATA: Read Data Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode). There is no SCLK rate restriction for this command, and there is no wait time needed for subsequent commands or data-retrieval SCLKs. To retrieve data from the device after the RDATA command is issued, make sure either the START pin is high or the START command is issued. When reading data with the RDATA command, the read operation can overlap the next DRDY occurrence without data corruption. shows the recommended way to use the RDATA command. RDATA is best suited for systems where register settings must be read or changed often between conversion cycles. START DRDY CS SCLK RDATA Opcode DIN RDATA Opcode Hi-Z DOUT Status Register + n-Channel Data (216 Bits) Figure 38. RDATA Usage Sending Multibyte Commands The ADS130E08 serial interface decodes commands in bytes and requires 4 tCLK cycles to decode and execute. Therefore, when sending multibyte commands, a 4-tCLK period must separate the end of one byte (or opcode) and the next. Assuming CLK is 2.048 MHz, then tSDECODE (4 tCLK) is 1.96 µs. When SCLK is 16 MHz, one byte can be transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be inserted so the end of the second byte arrives 1.46 µs later. If SCLK is 4 MHz, one byte is transferred in 2 µs. Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without delay. In this later scenario, the serial port can be programmed to move from single-byte transfers per cycle to multiple bytes. 30 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 RREG: Read From Register This opcode reads register data. The Register Read command is a two-byte opcode followed by the register data output. The first byte contains the command opcode and register address. The second opcode byte specifies the number of registers to read – 1. First opcode byte: 001r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to read – 1. The 17th SCLK rising edge of the operation clocks out the MSB of the first register, as shown in . When the device is in read data continuous mode, an SDATAC command must be issued before the RREG command can be issued. The RREG command can be issued at any time. However, because this command is a multibyte command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA DOUT REG DATA + 1 Figure 39. RREG Command Example: Read Two Registers Starting from Register 00h (ID Register) (OPCODE 1 = 0010 0000, OPCODE 2 = 0000 0001) WREG: Write to Register This opcode writes register data. The Register Write command is a two-byte opcode followed by the register data input. The first byte contains the command opcode and the register address. The second opcode byte specifies the number of registers to write – 1. First opcode byte: 010r rrrr, where r rrrr is the starting register address. Second opcode byte: 000n nnnn, where n nnnn is the number of registers to write – 1. After the opcode bytes, the register data follows (in MSB-first format), as shown in . The WREG command can be issued at any time. However, because this command is a multibyte command, there are SCLK rate restrictions depending on how the SCLKs are issued. See the Serial Clock (SCLK) subsection of the SPI Interface section for more details. Note that CS must be low for the entire command. CS 1 9 17 25 SCLK DIN OPCODE 1 OPCODE 2 REG DATA 1 REG DATA 2 DOUT Figure 40. WREG Command Example: Write Two Registers Starting from 00h (ID Register) (OPCODE 1 = 0100 0000, OPCODE 2 = 0000 0001) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 31 ADS130E08 SBAS574 – JULY 2012 www.ti.com REGISTER MAP describes the various ADS130E08 registers. Table 6. Register Assignments ADDRESS REGISTER RESET VALUE (Hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 52 REV_ID3 REV_ID2 REV_ID1 1 0 DEV_ID1 NU_CH2 NU_CH1 Device Settings (Read-Only Registers) 00h ID Global Settings Across Channels 01h CONFIG1 01 0 0 CLK_EN 0 0 0 0 1 02h CONFIG2 60 0 1 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 03h CONFIG3 40 PD_REFBUF 1 VREF_4V 0 OPAMP_REF PD_OPAMP 0 0 04h FAULT 00 COMP_TH2 COMP_TH1 COMP_TH0 0 0 0 0 0 Channel-Specific Settings 05h CH1SET 10 PD1 GAIN12 GAIN11 GAIN10 0 MUX12 MUX11 MUX10 06h CH2SET 10 PD2 GAIN22 GAIN21 GAIN20 0 MUX22 MUX21 MUX20 07h CH3SET 10 PD3 GAIN32 GAIN31 GAIN30 0 MUX32 MUX31 MUX30 08h CH4SET 10 PD4 GAIN42 GAIN41 GAIN40 0 MUX42 MUX41 MUX40 09h CH5SET 10 PD5 GAIN52 GAIN51 GAIN50 0 MUX52 MUX51 MUX50 0Ah CH6SET 10 PD6 GAIN62 GAIN61 GAIN60 0 MUX62 MUX61 MUX60 0Bh CH7SET 10 PD7 GAIN72 GAIN71 GAIN70 0 MUX72 MUX71 MUX70 0Ch CH8SET 10 PD8 GAIN82 GAIN81 GAIN80 0 MUX82 MUX81 MUX80 Fault Detect Status Registers (Read-Only Registers) 12h FAULT_STATP 00 IN8P_FAULT IN7P_FAULT IN6P_FAULT IN5P_FAULT IN4P_FAULT IN3P_FAULT IN2P_FAULT IN1P_FAULT 13h FAULT_STATN 00 IN8N_FAULT IN7N_FAULT IN6N_FAULT IN5N_FAULT IN4N_FAULT IN3N_FAULT IN2N_FAULT IN1N_FAULT 0F GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIO and Other Registers 14h 32 GPIO Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 User Register Description ID: ID Control Register (Factory-Programmed, Read-Only) Address = 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REV_ID3 REV_ID2 REV_ID1 1 0 DEV_ID1 NU_CH2 NU_CH1 This register is programmed during device manufacture to indicate device characteristics. Bits[7:5] REV_ID[3:1]: Device family identification (read-only) These factory-programmed bits indicate the device version. 010 = ADS130E08 All others are reserved. Bit 4 Must be set to '1' Bit 3 Must be set to '0' Bits[1:0] DEV_ID1 and NU_CH[2:1]: Device identification bits (read-only) These factory-programmed bits indicate the device version. 010 = ADS130E08 All others are reserved. CONFIG1: Configuration Register 1 Address = 01h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 CLK_EN 0 0 0 0 1 This register is reserved for device manufacturing. Bits[7:6] Must be set to '0' Bit 5 CLK_EN: CLK connection This bit determines if the internal oscillator signal is connected to the CLK pin when the CLKSEL pin is '1'. 0 = Oscillator clock output disabled (default) 1 = Oscillator clock output enabled Bits[4:1] Must be set to '0' Bit 0 Must be set to '1' Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 33 ADS130E08 SBAS574 – JULY 2012 www.ti.com CONFIG2: Configuration Register 2 Address = 02h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 1 INT_TEST 0 TEST_AMP TEST_FREQ1 TEST_FREQ0 This register configures test signal generation. See the Input Multiplexer section for more details. Bit 7 Must be set to '0' Bits[6:5] Must be set to '1' Bit 4 INT_TEST: Test source This bit determines the test signal source. 0 = Test signals are driven externally (default) 1 = Test signals are generated internally Bit 3 Must be set to '0' Bit 2 TEST_AMP: Test signal amplitude This bit determines the Calibration signal amplitude. 0 = 1 × –(VREFP – VREFN) / 2.4 mV (default) 1 = 2 × –(VREFP – VREFN) / 2.4 mV Bits[1:0] TEST_FREQ[1:0]: Test signal frequency These bits determine the calibration signal frequency. 00 01 10 11 = Pulsed at fCLK / 221 (default) = Pulsed at fCLK / 220 = Not used = At dc CONFIG3: Configuration Register 3 Address = 03h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PD_REFBUF 1 VREF_4V 0 OPAMP_REF PD_OPAMP 0 0 This register configures multireference operation. Bit 7 PD_REFBUF: Power-down reference buffer This bit determines the power-down reference buffer state. 0 = Power-down internal reference buffer (default) 1 = Enable internal reference buffer Bit 6 Must be set to '1' Default is '1' at power-up. Bit 5 VREF_4V: Reference voltage This bit determines the reference voltage, VREFP. 0 = VREFP is set to 2.4 V (default) 1 = VREFP is set to 4 V (only use with a 5-V analog supply) Bit 4 Must be set to '0' Bit 3 OPAMP_REF: Op amp reference This bit determines whether the op amp noninverting input connects to the OPAMPP pin or to the internally-derived 1/2 supply (AVDD + AVSS) / 2. 0 = Noninverting input connected to the OPAMPP pin (default) 1 = Noninverting input connected to (AVDD + AVSS) / 2 Bit 2 PD_OPAMP: Power-down op amp This bit determines the power-down reference buffer state. 0 = Power-down op amp (default) 1 = Enable op amp Bits[1:0] 34 Must be set to '0' Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 FAULT: Fault Detect Control Register Address = 04h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 COMP_TH2 COMP_TH1 COMP_TH0 0 0 0 0 0 This register configures the fault detection operation. Bits[7:5] COMP_TH[2:0]: Fault detect comparator threshold These bits determine the fault detect comparator threshold level setting. See the Fault Detection section for a detailed description. Comparator positive-side threshold 000 = 95% (default) 001 = 92.5% 010 = 90% 011 = 87.5% 100 = 85% 101 = 80% 110 = 75% 111 = 70% Comparator negative-side threshold 000 = 5% (default) 001 = 7.5% 010 = 10% 011 = 12.5% 100 = 15% 101 = 20% 110 = 25% 111 = 30% Bits[4:0] Must be set to '0' Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 35 ADS130E08 SBAS574 – JULY 2012 www.ti.com CHnSET: Individual Channel Settings (n = 1 to 8) Address = 05h to 0Ch BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PDn GAINn2 GAINn1 GAINn0 0 MUXn2 MUXn1 MUXn0 The CH[8:1]SET Control Register configures the power mode, PGA gain, and multiplexer setting channels. See the Input Multiplexer section for details. CH[8:2]SET are similar to CH1SET, corresponding to the respective channels (refer to ). Bit 7 PDn: Power-down (n = individual channel number) This bit determines the channel power mode for the corresponding channel. 0 = Normal operation (default) 1 = Channel power-down Bits[6:4] GAINn[2:0]: PGA gain (n = individual channel number) These bits determine the PGA gain setting. 000 = Do not 001 = x1 010 = x2 011 = Do not 100 = Do not 101 = x8 110 = Do not 111 = Do not use use use use use Bit 3 Must be set to '0' Bits[2:0] MUXn[2:0]: Channel input (n = individual channel number) These bits determine the channel input selection. 000 = Normal input (default) 001 = Input shorted (for offset or noise measurements) 010 = Do not use 011 = MVDD for supply measurement 100 = Temperature sensor 101 = Test signal 110 = Do not use 111 = Do not use 36 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 FAULT_STATP: Fault Detect Positive Input Status Address = 12h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8P_FAULT IN7P_FAULT IN6P_FAULT IN5P_FAULT IN4P_FAULT IN3P_FAULT IN2P_FAULT IN1P_FAULT This register stores the status of whether a fault condition is present on the positive electrode of each channel. See the Fault Detection section for details. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set to '1'. Bits[7:0] INnP_FAULT: Input fault status (n = individual channel number) 0 = No fault present (default) 1 = Fault present FAULT_STATN: Fault Detect Negative Input Status Address = 13h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IN8N_FAULT IN7N_FAULT IN6N_FAULT IN5N_FAULT IN4N_FAULT IN3N_FAULT IN2N_FAULT IN1N_FAULT This register stores the status of whether a fault condition is present on the negative electrode of each channel. See the Fault Detection section for details. Ignore the LOFF_STATP values if the corresponding LOFF_SENSP bits are not set to '1'. Bits[7:0] INnN_FAULT: Input fault status (n = individual channel number) 0 = No fault present (default) 1 = Fault present GPIO: General-Purpose IO Register Address = 14h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 GPIOD4 GPIOD3 GPIOD2 GPIOD1 GPIOC4 GPIOC3 GPIOC2 GPIOC1 This register controls the action of the three GPIO pins. Bits[7:4] GPIOD[4:1]: GPIO data These bits are used to read and write data to the GPIO ports. When reading the register, the data returned correspond to the state of the GPIO external pins, whether they are programmed as inputs or outputs. As outputs, a write to the GPIOD sets the output value. As inputs, a write to the GPIOD has no effect. Bits[1:0] GPIOC[4:1]: GPIO control (corresponding to GPIOD) These bits determine if the corresponding GPIOD pin is an input or output. 0 = Output 1 = Input (default) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 37 ADS130E08 SBAS574 – JULY 2012 www.ti.com POWER-MONITORING SPECIFIC APPLICATIONS All ADS130E08 channels are independently configurable, allowing any channel to be selected for voltage or current monitoring. Also, the simultaneously sampling capability of the device allows both current and voltage to be monitored at the same time. The full-scale differential input voltage of each channel is determined by the PGA gain setting (see the CHnSET: Individual Channel Settings section) for the respective channel and VREF (see the CONFIG3: Configuration Register 3 section). summarizes the full-scale differential input voltage range for an internal VREF. Table 7. Full-Scale Differential Input (FSDI) Voltage Summary VREF 2.4 V 4.0 V PGA GAIN FULL-SCALE DIFFERENTIAL INPUT VOLTAGE (VPP) RMS VOLTAGE [= FSDI / (2√2)] (VRMS) 1 4.8 1.698 2 2.4 0.849 8 0.6 0.212 1 8.0 2.828 2 4.0 1.414 8 1 0.354 CURRENT SENSING shows a simplified diagram of typical configurations used for current sensing with a Rogowski coil, current transformer (CT), or an air coil that outputs a current or voltage. In the case of current-output transformers, the burden resistors (R1) are used for current-to-voltage conversion. The burden resistor output is connected to the ADS130E08 INP and INN inputs through an antialiasing RC filter for current sensing. In the case of voltageoutput transformers (such as certain types of Rogowski coils), the transformer output terminals are directly connected to the ADS130E08 INP and INN inputs through an antialiasing RC filter for current sensing. The common-mode bias voltage (AVDD + AVSS) / 2, can be obtained from the ADS130E08 by either configuring the internal op amp in a unity-gain configuration using the RF resistor and setting bit 3 of CONFIG3: Configuration Register 3, or it can be generated externally with a simple resistor divider network between the positive and negative supplies. The resistor R1 value for the current-output transformer, the output voltage (V) for the voltage-output transformer, and the turns ratio of the transformer should be carefully selected so as not to exceed the ADS130E08 FSDI range (see ). Furthermore, these values should not saturate the transformer over the full operating dynamic range of the energy meter. a shows differential input current sensing and b shows single-ended input sensing. Device N Device L N I R2 L R2 INP R1 EMI Filter C To PGA V INP EMI Filter C To PGA R1 R2 I INN INN Rf OPAMP_REF (AVDD + AVSS) OPAMPOUT 2 - Rf OPAMPN OPAMPP + OPAMPOUT + OPAMP_REF (AVDD + AVSS) 2 OPAMPN OPAMPP (a) Current Output CT with Differential Input (b) Voltage Output CT with Single-Ended Input Figure 41. Simplified Current-Sensing Connections 38 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 VOLTAGE SENSING shows a simplified diagram of commonly-used differential and single-ended methods of voltage sensing. A resistor divider network is used to step down the line voltage within the acceptable input range of the ADS130E08 and then directly connect to the inputs (INP and INN) through an antialiasing RC filter formed by resistor R3 and capacitor C. The common-mode bias voltage (AVDD + AVSS) / 2, can be obtained from the ADS130E08 by either configuring the internal op amp in a unity-gain configuration using the RF resistor and setting bit 3 of CONFIG3: Configuration Register 3, or it can be generated externally by using a simple resistor divider network between the positive and negative supplies. In either case presented in (a for a differential input and b for a single-ended input), the line voltage is divided down by a factor of [R2 / (R1 + R2)]. R1 and R2 values must be carefully chosen so that the voltage across the ADS130E08 inputs (INP and INN) does not exceed the ADS130E08 FSDI range (see ) over the full operating dynamic range of the energy meter. Device N Device L N R1 R3 EMI Filter C R2 R1 R3 R1 INP R2 L To PGA R3 R2 INP EMI Filter C INN INN RF OPAMP_REF (AVDD + AVSS) OPAMPOUT 2 - RF OPAMPN + + OPAMP_REF (AVDD + AVSS) OPAMPOUT To PGA 2 OPAMPN OPAMPP OPAMPP (a) Voltage Sensing with Differential Input (b) Voltage Sensing with Single-Ended Input Figure 42. Simplified Voltage Sensing Connections Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 39 ADS130E08 SBAS574 – JULY 2012 www.ti.com FAULT DETECTION The ADS130E08 has integrated comparators that can be used in conjunction with the external pull-up or pulldown resistors (R) to detect various fault conditions. The basic principle is to compare the input voltage with the voltage set by the 3-bit DAC fault comparator, as shown in . The comparator trigger threshold level is set by the COMP_TH[2:0] bits in the FAULT register. Assuming that the ADS130E08 is powered from a ±2.5-V supply and COMP_TH[2:0] = 000 (95% and 5%), the high-side trigger threshold is set at +2.25 V [equal to AVSS + (AVDD + AVSS) × 95%] and the low-side threshold is set at –2.25 V [equal to AVSS + (AVDD + AVSS) × 5%]. The threshold calculation formula applies to unipolar as well as bipolar supplies. A fault condition, such as an input signal going out of a predetermined range, can be detected by setting the appropriate threshold level using the COMP_TH[2:0] bits. An open-circuit fault at the INP or INN pin can be detected by using the external pull-up and pull-down resistors, which rails the corresponding input when the input circuit breaks, causing the fault comparators to trip. To pinpoint which of the inputs is out of range, the status of the FAULT_STATP and FAULT_STATN registers can be read, which is available as part of the output data stream; see the Data Output (DOUT) subsection of the SPI Interface section. 3-Bit DAC(1) COMP_TH[2:0] Fault Detect Control Register AVDD FAULT_STATP R Voltage Or Current Sensing + INP EMI Filter INN PGA To ADC - R FAULT_STATN AVSS Device (1) The configurable 3-bit DAC is common to all channels. Figure 43. Fault Detect Comparators 40 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 QUICK-START GUIDE PCB LAYOUT Power Supplies and Grounding The ADS130E08 has three supplies: AVDD, AVDD1, and DVDD. Both AVDD and AVDD1 should be as quiet as possible. AVDD1 provides the supply to the charge pump block and has transients at fCLK. Therefore, AVDD1 and AVSS1 are recommended to be star-connected to AVDD and AVSS. It is important to eliminate noise from AVDD and AVDD1 that is non-synchronous with the ADS130E08 operation. Each ADS130E08 supply should be bypassed with 10-μF and a 0.1-μF solid ceramic capacitors. It is recommended that placement of the digital circuits (such as DSPs, microcontrollers, and FPGAs) in the system be done such that the return currents on those devices do not cross the ADS130E08 analog return path. The ADS130E08 can be powered from unipolar or bipolar supplies. The capacitors used for decoupling can be surface-mount, low-cost, low-profile multilayer ceramic capacitors. In most cases the VCAP1 capacitor can also be a multilayer ceramic. However, in systems where the board is subjected to high- or low-frequency vibration, it is recommend that a non-ferroelectric capacitor such as a tantalum or class 1 capacitor (C0G or NPO for example) be installed. EIA class 2 and class 3 dielectrics (such as X7R, X5R, and X8R) are ferroelectric. The piezoelectric property of these capacitors can appear as electrical noise coming from the capacitor. When using the internal reference, noise on the VCAP1 node results in performance degradation. Connecting the Device to Unipolar (+3 V or +1.8 V) Supplies shows the ADS130E08 connected to a unipolar supply. In this example, the analog supply (AVDD) is referenced to analog ground (AVSS) and the digital supplies (DVDD) are referenced to digital ground (DGND). +3 V +1.8 V 0.1 µF 1 µF 1 µF 0.1 µF AVDD AVDD1 DVDD VREFP VREFN 0.1 µF 10 µF VCAP1 RESV1 VCAP2 Device VCAP3 VCAP4 AVSS1 AVSS DGND 1 µF 1 µF 0.1 µF 1 µF 22 µF NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible. Figure 44. Single-Supply Operation Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 41 ADS130E08 SBAS574 – JULY 2012 www.ti.com Connecting the Device to Bipolar (±1.5 V or 1.8 V) Supplies illustrates the ADS130E08 connected to a bipolar supply. In this example, the analog supplies connect to the device analog supply (AVDD). This supply is referenced to the device analog return (AVSS), and the digital supply (DVDD) is referenced to the device digital ground return (DGND). +1.5 V +1.8 V 1 µF 0.1 µF 0.1 µF 1 µF AVDD AVDD1 DVDD VREFP VREFN 0.1 µF 10 µF 1.5 V VCAP1 Device VCAP2 RESV1 VCAP3 VCAP4 AVSS1 AVSS DGND 1 µF 1 µF 1 µF 0.1 µF 1 µF 22 µF 0.1 µF 1.5 V NOTE: Place the capacitors for supply, reference, and VCAP1 to VCAP4 as close to the package as possible. Figure 45. Bipolar Supply Operation Shielding Analog Signal Paths As with any precision circuit, careful PCB layout ensures the best performance. It is essential to make short, direct interconnections and avoid stray wiring capacitance—particularly at the analog input pins and AVSS. These analog input pins are high-impedance and extremely sensitive to extraneous noise. The AVSS pin should be treated as a sensitive analog signal and connected directly to the supply ground with proper shielding. Leakage currents between the PCB traces can exceed the ADS130E08 input bias current if shielding is not implemented. Digital signals should be kept as far as possible from the analog input signals on the PCB. 42 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 ADS130E08 www.ti.com SBAS574 – JULY 2012 POWER-UP SEQUENCING Before device power-up, all digital and analog inputs must be low. At the time of power-up, all of these signals should remain low until the power supplies have stabilized, as shown in . At this time, begin supplying the master clock signal to the CLK pin. Wait for time tPOR, then transmit a RESET pulse. After releasing RESET, the configuration register must be programmed (see the CONFIG1: Configuration Register 1 subsection of the Register Map section for details). The power-up sequence timing is shown in . tPOR Power Supplies tRST RESET 18 tCLK Start Using the Device Figure 46. Power-Up Timing Diagram Table 8. Power-Up Sequence Timing SYMBOL DESCRIPTION tPOR Wait after power-up until reset tRST Reset low width MIN TYP MAX UNIT 216 tCLK 2 tCLK SETTING THE DEVICE FOR BASIC DATA CAPTURE This section outlines the procedure to configure the device in a basic state and capture data. This procedure is intended to put the device in a data sheet condition to check if the device is working properly in the user system. This procedure is recommended to be followed initially to get familiar with the device settings. When this procedure is verified, the device can be configured as needed. For details on the timings for commands refer to the appropriate sections in the data sheet. The flow chart of details the initial configuration and setup of the ADS130E08. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 43 ADS130E08 SBAS574 – JULY 2012 www.ti.com Analog and Digital Power-Up Set CLKSEL Pin = 0 and Provide External Clock fCLK = 2.048 MHz Yes // Follow Power-Up Sequencing External Clock No Set CLKSEL Pin = 1 and Wait for Oscillator to Wake Up Set PWDN/RESET = 1 Wait for 1 s for Power-On Reset Issue Reset Pulse, Wait for 18 tCLKs Set PD_REFBUF = 1 and Wait for Internal Reference To Settle // If START is Tied High, After This Step // DRDY Toggles at fCLK / 256 // Delay for Power-On Reset and Oscillator Start-Up // Activate DUT //CS Can Either Be Tied Permanently Low // Or Selectively Pulled Low Before Sending // Commands or Reading and Sending Data From or To the Device Send SDATAC Command // Device Wakes Up in RDATAC Mode, so Send // SDATAC Command so Registers can be Written SDATAC External Reference // If Using Internal Reference, Send This Command -- WREG CONFIG3 C0h No Yes Write Certain Registers, Including Input Short WREG CONFIG1 01h WREG CONFIG2 60h // Set All Channels to Input Short WREG CHnSET 11h Set START = 1 // Activate Conversion // After This Point DRDY Should Toggle at // fCLK / 256 RDATAC // Put the Device Back in RDATAC Mode RDATAC Capture Data and Check Noise // Look for DRDY and Issue 152 SCLKs Set Test Signals Capture Data and Test Signals // Activate a (1 mV u VREF / 2.4) Square-Wave Test Signal // On All Channels SDATAC WREG CONFIG2 70h WREG CHnSET 15h RDATAC // Look for DRDY and Issue 152 SCLKs Figure 47. Initial Flow at Power-Up 44 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): ADS130E08 PACKAGE OPTION ADDENDUM www.ti.com 24-Jul-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) ADS130E08IPAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS130E08IPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS130E08IPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS130E08IPAGR TQFP PAG 64 1500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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