a FEATURES 7 ns Propagation Delay at 5 V Single Supply Operation: 3 V to 10 V Low Power Latch Function TSSOP Packages APPLICATIONS High Speed Timing Clock Recovery and Clock Distribution Line Receivers Digital Communications Phase Detectors High Speed Sampling Read Channel Detection PCMCIA Cards Upgrade for LT1016 Designs GENERAL DESCRIPTION Ultrafast 7 ns Single Supply Comparator AD8561 PIN CONFIGURATIONS 8-Lead Plastic DIP (N-8) 8-Lead Narrow Body SO (SO-8) OUT OUT GND LATCH Vⴙ ⴙIN ⴚIN Vⴚ AD8561 Vⴙ 1 8 OUT ⴙIN 2 7 OUT ⴚIN 3 6 GND 5 LATCH Vⴚ 4 AD8561 8-Lead TSSOP (RU-8) Vⴙ ⴙIN ⴚIN Vⴚ 1 8 AD8561 4 5 OUT OUT GND LATCH The AD8561 is a single 7 ns comparator with separate input and output sections. Separate supplies enable the input stage to be operated from ± 5 V dual supplies and +5 V single supplies. Fast 7 ns propagation delay makes the AD8561 a good choice for timing circuits and line receivers. Propagation delays for rising and falling signals are closely matched and track over temperature. This matched delay makes the AD8561 a good choice for clock recovery, since the duty cycle of the output will match the duty cycle of the input. The AD8561 has the same pinout as the LT1016, with lower supply current and a wider common-mode input range, which includes the negative supply rail. The AD8561 is specified over the industrial (–40°C to +85°C) temperature range. The AD8561 is available in both the 8-lead plastic DIP, 8-lead TSSOP or narrow SO-8 surface mount packages. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD8561–SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V+ = +5.0 V, V– = V Parameter Symbol INPUT CHARACTERISTICS Offset Voltage VOS Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance LATCH ENABLE INPUT Logic “1” Voltage Threshold Logic “0” Voltage Threshold Logic “1” Current Logic “0” Current Latch Enable Pulsewidth Setup Time Hold Time ∆VOS/∆T IB IB IOS VCM CMRR AVO CIN VIH VIL IIH IIL GND = 0 V, TA = +25ⴗC unless otherwise noted) Conditions Min –40°C ≤ TA ≤ +85°C VCM = 0 V –40°C ≤ TA ≤ +85°C VCM = 0 V 0 V ≤ VCM ≤ +3.0 V RL = 10 kΩ –6 –7 0.0 65 2.0 VLH = 3.0 V VLL = 0.3 V –1.0 –4 tPW(E) tS tH Typ Max Units 2.3 7 8 mV mV µV/°C µA µA µA V dB V/V pF 4 –3 –3.5 ±4 +3.0 85 3000 3.0 1.65 1.60 –0.3 –2 0.8 V V µA µA 6 1 1.2 ns ns ns 3.5 0.25 V V V DIGITAL OUTPUTS Logic “1” Voltage Logic “1” Voltage Logic “0” Voltage VOH VOH VOL IOH = –50 µA, ∆VIN > 250 mV IOH = –3.2 mA, ∆VIN > 250 mV IOL = 3.2 mA, ∆VIN > 250 mV DYNAMIC PERFORMANCE␣ Propagation Delay tP 200 mV Step with 100 mV Overdrive –40°C ≤ TA ≤ +85°C 100 mV Step with 5 mV Overdrive 6.75 8 8 9.8 13 ns ns ns ∆tP 100 mV Step with 100 mV Overdrive1 20% to 80% 80% to 20% 0.5 3.8 1.5 2.0 ns ns ns PSRR I+ +4.5 V ≤ V+ ≤ +5.5 V Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time POWER SUPPLY␣ Power Supply Rejection Ratio Positive Supply Current tP Ground Supply Current IGND Analog Supply Current I– –40°C ≤ TA ≤ +85°C VO = 0 V, RL = ∞ –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C 3.5 2.4 50 65 4.5 2.2 2.3 0.4 6.0 7.5 3.3 3.8 4.5 5.5 dB mA mA mA mA mA mA NOTES 1 Guaranteed by design. Specifications subject to change without notice. –2– REV. 0 AD8561 ELECTRICAL SPECIFICATIONS (@ V+ = +5.0 V, V– = V Parameter Symbol INPUT CHARACTERISTICS Offset Voltage VOS Offset Voltage Drift Input Bias Current Input Offset Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Input Capacitance LATCH ENABLE INPUT Logic “1” Voltage Threshold Logic “0” Voltage Threshold Logic “1” Current Logic “0” Current Latch Enable Pulsewidth Setup Time Hold Time ∆VOS/∆T IB IB IOS VCM CMRR AVO CIN VIH VIL IIH IIL GND = 0 V, V– = –5 V, TA = +25ⴗC unless otherwise noted) Conditions Min –40°C ≤ TA ≤ +85°C VCM = 0 V –40°C ≤ TA ≤ +85°C VCM = 0 V –5.0 V ≤ VCM ≤ +3.0 V RL = 10 kΩ –6 –7 –5.0 65 2.0 VLH = 3.0 V VLL = 0.3 V –1 –4 Typ Max Units 1 7 8 mV mV µV/°C µA µA µA V dB V/V pF 4 –3 –2.5 ±4 +3.0 85 3000 3.0 1.65 1.60 –0.5 –2 0.8 20 20 6 1.0 1.2 tPW(E) tS tH V V µA µA ns ns ns DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage VOH VOL IOH = –3.2 mA IOL = 3.2 mA DYNAMIC PERFORMANCE␣ Propagation Delay tP 200 mV Step with 100 mV Overdrive –40°C ≤ TA ≤ +85°C 100 mV Step with 5 mV Overdrive 6.5 8 7 9.8 13 ns ns ns ∆tP 100 mV Step with 100 mV Overdrive1 20% to 80% 80% to 20% 0.5 3.8 1.5 1 2 ns ns ns ns PSRR ± 4.5 V ≤ VCC and VEE ≤ ± 5.5 V VO = 0 V, RL = ∞ Propagation Delay Differential Propagation Delay (Rising Propagation Delay vs. Falling Propagation Delay) Rise Time Fall Time Dispersion POWER SUPPLY Power Supply Rejection Ratio Supply Current Positive Supply Current tP I+ Ground Supply Current IGND Negative Supply Current I– –40°C ≤ TA ≤ +85°C VO = 0 V, RL = ∞ –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C NOTES 1 Guaranteed by design. Specifications subject to change without notice. REV. 0 –3– 2.6 55 3.5 0.2 0.3 70 4.7 2.2 2.4 V V dB 6.5 7.5 3.3 3.8 4.5 5.5 mA mA mA mA mA mA AD8561–SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter (@ V+ = +3.0 V, V– = VGND = 0 V, TA = +25ⴗC unless otherwise noted) Symbol INPUT CHARACTERISTICS␣ Offset Voltage Input Bias Current Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS␣ Output High Voltage Output Low Voltage POWER SUPPLY␣ Power Supply Rejection Ratio Supply Currents V+ Supply Current Min Typ VCM = 0 V –40°C ≤ TA ≤ +85°C –6 –7 0 60 –3.0 –4 VOS IB IB VCM CMRR 0.1 V ≤ VCM ≤ 1.5 V VOH VOL IOH = –3.2 mA, VIN > 250 mV IOL = +3.2 mA, VIN > 250 mV PSRR +2.7 V ≤ VCC, VEE ≤ +6 V VO = 0 V, RL = ∞ I+ Ground Supply Current IGND V– Supply Current I– DYNAMIC PERFORMANCE␣ Propagation Delay Conditions tP Max Units 7 mV µA µA V dB +1.5 1.21 0.3 40 dB 4.0 –40°C ≤ TA ≤ +85°C 1.6 –40°C ≤ TA ≤ +85°C 2.4 –40°C ≤ TA ≤ +85°C 100 mV Step with 20 mV Overdrive2 V V 8.5 4.5 5.5 2.5 3.0 3.3 3.8 mA mA mA mA mA mA 9.8 ns NOTES 1 Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation. 2 Guaranteed by design. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V Analog Positive Supply–Digital Positive Supply . . . . . –600 mV Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . ±8 V Output Short-Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range N, R, RU Package . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300°C Package Type JA2 JC Units 8-Lead Plastic DIP (N) 8-Lead SO (R) 8-Lead TSSOP 103 158 240 43 43 43 °C/W °C/W °C/W NOTES 1 The analog input voltage is equal to ±7 V or the analog supply voltage, whichever is less. 2 θ JA is specified for the worst case conditions, i.e., θ JA is specified for device in socket for P-DIP and θ JA is specified for device soldered in circuit board for SOIC and TSSOP packages. ORDERING GUIDE Model Temperature Range Package Description Package Options AD8561AN AD8561ARU AD8561AR –40°C to +85°C –40°C to +85°C –40°C to +85°C 8-Lead Plastic DIP 8-Lead Thin Shrink Small Outline 8-Lead Small Outline IC N-8 RU-8 SO-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8561 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD8561 Typical Performance Characteristics (V+ = +5 V, V– = 0 V, T = +25ⴗC unless otherwise noted) A 5 3 +258C 2 1 0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 DIFFERENTIAL INPUT VOLTAGE – mV Figure 1. Output Voltage vs. Differential Input Voltage 100 –5 –4 –3 –2 –1 0 1 2 3 INPUT VOLTAGE – mV 4 tPD – FALLING EDGE 10 tPD + FALLING EDGE 5 20 30 40 10 LOAD CAPACITANCE – pF 10 5 30 STEP SIZE = 800mV 20 400mV 200mV 100mV 10 0 0.5 1 1.5 SOURCE RESISTANCE – kV 15 5 5 4.75 5 5.25 SUPPLY VOLTAGE – Volts 5.5 Figure 6. Propagation Delay vs. Positive Supply Voltage 4 15 125 3 –408C +1258C 10 5 0 100 Figure 7. Propagation Delay vs. Temperature REV. 0 50 SINGLE SUPPLY, TA = +258C STEP SIZE = 100mV OVERDRIVE = 5mV CAPACITANCE LOAD = 10pF 0 4.5 TIME – ns PROPAGATION DELAY – ns 10 0 25 75 50 TEMPERATURE – 8C 40 +258C VS = +5V, SINGLE SUPPLY STEP SIZE = 100mV OVERDRIVE = 5mV, LOAD CAPACITANCE = 10pF –25 20 30 OVERDRIVE – mV 10 20 0 –50 10 Figure 3. Propagation Delay vs. Overdrive 2 Figure 5. Propagation Delay vs. Source Resistance 20 0 20 VS = 5V, SINGLE SUPPLY TA = +258C OVERDRIVE = 10mV CAPACITANCE LOAD = 10pF 0 50 TA = +258C 0 PROPAGATION DELAY – ns 15 15 5 Figure 2. Typical Distribution of Input Offset Voltage PROPAGATION DELAY – ns PROPAGATION DELAY – ns 200 40 VS = 5V, SINGLE SUPPLY STEP SIZE = 100mV OVERDRIVE LOAD = 5mV Figure 4. Propagation Delay vs. Load Capacitance PROPAGATION DELAY – ns 300 0 20 15 400 PROPAGATION DELAY – ns NUMBER OF COMPARATORS OUTPUT VOLTAGE – Volts –408C 0 VS = 5V, SINGLE SUPPLY STEP SIZE = 100mV CAPACITANCE LOAD = 10pF VS = 5V, SINGLE SUPPLY 4 0 20 500 +1258C 2 3 4 1 COMMON-MODE VOLTAGE – Volts 5 Figure 8. Propagation Delay vs. VCM –5– HOLD TIME SET-UP TIME 1 VS = 5V STEP SIZE = 100mV OVERDRIVE = 5mV LOAD CAPACITANCE = 10pF 0 2 0 –50 –25 0 25 50 75 TEMPERATURE – 8C 100 125 Figure 9. Latch Setup-and-Hold Time vs. Temperature AD8561 5.0 0.4 0.3 TA = –408C TA = +258C 0.2 TA = +1258C 0.1 4.4 TA = +1258C 3.8 TA = +258C 3.2 TA = –408C 2.6 2.0 0 0 3 6 9 12 SINK CURRENT – mA 0 15 Figure 10. Output Low Voltage, VOL vs. Sink Current 3 6 9 12 SOURCE CURRENT – mA 15 Figure 11. Output High Voltage, V OH vs. Source Current 0 –1.0 V+ = 5V, V– = 0V –2.0 V+ = 5V, V– = –5V –3.0 –4.0 –5.0 –75 –50 –25 0 TA = –408C –2.0 TA = +258C –3.0 TA = +1258C –4.0 –5.0 35 30 25 20 +1258C 15 +258C 10 –408C 4 6 8 10 SUPPLY VOLTAGE –Volts 12 Figure 13. Analog Supply Current vs. Supply Voltage for +5 V, –5 V Supplies –1 –2 –3 –4 5 0 2 INPUT BIAS CURRENT – mA –1.0 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 12. Analog Supply Current vs. Temperature for +5 V, –5 V Supplies 40 POSITIVE SUPPLY CURRENT – mA I–, ANALOG SUPPLY CURRENT – mA 0 I–, ANALOG SUPPLY CURRENT – mA OUTPUT HIGH VOLTAGE – Volts OUTPUT LOW VOLTAGE – Volts 0.5 1 10 FREQUENCY – MHz 100 Figure 14. Positive Supply Current vs. Frequency –5 –5 –2.5 0 2.5 –7.5 5 INPUT COMMON-MODE VOLTAGE – Volts Figure 15. Input Bias Current vs. Input Common-Mode Voltage for +5 V, –5 V Supplies INPUT BIAS CURRENT – mA 0 –1.0 –2.0 –3.0 –4.0 –5.0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE – 8C Figure 16. Input Bias Current vs. Temperature –6– REV. 0 AD8561 Example: A comparator compares a fast moving signal to a fixed 2.5 V reference. Since the comparator only needs to operate when the signal is near 2.5 V, both signals will be within the input range (near 2.5 V and well under 3.0 V) when the comparator needs to change output. APPLICATIONS OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator or amplifier, proper design and layout techniques should be used to ensure optimal performance from the AD8561. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance or other layout issues. Note that signals much greater than 3.0 V will result increased input currents and may cause the device to operate more slowly. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the AD8561. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the AD8561 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is slower than the 5 ns capability of the AD8561. Source impedances should be less than 1 kΩ for the best performance. The input bias current of the AD8561 is lower (–3 µA typical) than the LT1016 (+5 µA typical), and the current flows out of the AD8561 and into LT1016. If relatively low value resistors and/or low impedance sources are used on the inputs, the voltage shift due to bias current should be small. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin, Pin 1 and Pin 4, to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The AD8561 uses less current (typically 5 mA) than the LT1016 (typically 25 mA). The AD8561 (6.75 ns typical) is faster than the LT1016 (10 ns typical). While this is beneficial to many systems, timing may need to be adjusted to take advantage of the higher speed. The AD8561 has slightly more output voltage swing, from 0.2 V above ground to within 1.1 V of the positive supply voltage. A ground plane is recommended for proper high speed performance. This can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary current paths. The ground plane provides a low inductive ground, eliminating any potential differences at different ground points throughout the circuit board caused from “ground bounce.” A proper ground plane also minimizes the effects of stray capacitance on the circuit board. Although not required for normal operation, the output voltage swing of the AD8561 can be increased by connecting a 5 kΩ resistor from the output of the device to the V+ power supply. This configuration can be useful in low voltage power supply applications where maximizing output voltage swing is important. Adding a 5 kΩ pull-up resistor to the device’s output will not adversely affect the specifications of the AD8561. OUTPUT LOADING CONSIDERATIONS The AD8561 output can deliver up to 40 mA of output current without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 Ω. To ensure the best performance from the AD8561 it is important to minimize capacitive loading of the output of the device. Capacitive loads greater than 50 pF will cause ringing on the output waveform and will reduce the operating bandwidth of the comparator. REPLACING THE LT1016 The AD8561 is pin compatible with the LT1016 comparator. While it is easy to replace the LT1016 with the higher performance AD8561, please note that there are differences, and it is useful to check these to ensure proper operation. There are five major differences between the AD8561 and the LT1016—input voltage range, input bias currents, speed, output swing and power consumption. SETUP AND HOLD TIMES FOR LATCHING THE OUTPUT The latch input, Pin 5, can be used to retain data at the output of the AD8561. When the voltage at the latch input goes high, the output of the device will remain constant regardless of the input voltages. The setup time for the latch is 2 ns–3 ns and the hold time is 3 ns. This means that to ensure data retention at the output, the input signal must be valid at least 5 ns before the latch pin goes high and must remain valid at least 3 ns after the latch pin goes high. Once the latch input voltage goes low, new output data will appear in approximately 8 ns. When operated on a +5 V single supply, the LT1016 has an input voltage range from +1.25 V to +3.5 V. The AD8561 has a wider input range from 0 V to 3.0 V. Signals above 3.0 V may result in slower response times (see Figure 8). If both signals exceed 3.0 V, the signals may be shifted or attenuated to bring them into range, keeping in mind the note about source resistance in Optimizing High Speed Performance. If only one of the signals exceeds 3.0 V only slightly, and the other signal is always well within the 0 V to 3 V range, the comparator may operate without changes to the circuit. REV. 0 INCREASING OUTPUT SWING A logic high for the latch input is a minimum of +2.0 V and a logic low is a maximum of +0.8 V. This makes the latch input easily interface with TTL or CMOS logic gates. The latch circuitry in the AD8561 has no built-in hysteresis. –7– AD8561 The input signal is connected directly to the noninverting input of the comparator. The output is fed back to the inverting input through R1 and R2. The ratio of R1 to R1 + R2 establishes the width of the hysteresis window with VREF setting the center of the window, or the average switching voltage. The Q output will switch high when the input voltage is greater than VHI and will not switch low again until the input voltage is less than VLO as given in Equation 1: INPUT STAGE AND BIAS CURRENTS The AD8561 uses a PNP differential input stage that enables the input common-mode range to extend all the way from the negative supply rail to within 2.2 V of the positive supply rail. The input common-mode voltage can be found as the average of the voltage at the two inputs of the device. To ensure the fastest response time, care should be taken not to allow the input common-mode voltage to exceed either of these voltages. The input bias current for the AD8561 is 3 µA. As with any PNP differential input stage, this bias current will go to zero on an input that is high and will double on an input that is low. Care should be taken in choosing resistor values to be connected to the inputs as large resistors could cause significant voltage drops due to the input bias current. ( V HI = V + –1–V REF The capacitor CF can also be added to introduce a pole into the feedback network. This has the effect of increasing the amount of hysteresis at high frequencies. This can be useful when comparing a relatively slow signal in a high frequency noise environ- Hysteresis can easily be added to a comparator through the addition of positive feedback. Adding hysteresis to a comparator offers an advantage in noisy environments where it is not desirable for the output to toggle between states when the input signal is near the switching threshold. Figure 17 shows a method for configuring the AD8561 with hysteresis. R1 (1) Where V+ is the positive supply voltage. USING HYSTERESIS VREF REF R1 V LO =V REF 1– R1+ R2 The input capacitance for the AD8561 is typically 3 pF. This is measured by inserting a 5 kΩ source resistance to the input and measuring the change in propagation delay. SIGNAL ) R1+R1R2 +V 1 , the hysteresis 2π CF R2 window approaches VHI = V+ – 1 V and VLO = 0 V. At frequencies less than fP the threshold voltages remain as in Equation 1. ment. At frequencies greater than fP = COMPARATOR R2 CF Figure 17. Configuring the AD8561 with Hysteresis –8– REV. 0 AD8561 SPICE Model * AD8561 SPICE Macro-Model Typical Values * 4/98, Ver. 1.0 * TAM / ADSC * * Node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative * | | | | * | | | | * | | | | * | | | | * | | | | .SUBCKT AD8561 1 2 99 50 * * INPUT STAGE * * Q1 4 3 5 PIX Q2 6 2 5 PIX IBIAS 99 5 800E-6 RC1 4 50 1E3 RC2 6 50 1E3 CL1 4 6 1E-12 CIN 1 2 3E-12 VCM1 99 7 1 D1 5 7 DX EOS 3 1 POLY(1) (31,98) 1E-3 1 * * Reference Voltage * EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5 RREF 98 0 100E3 * * CMRR=80dB, ZERO AT 1kHz * ECM1 30 98 POLY(2) (1,98) (2,98) 0 0.5 0.5 RCM1 30 31 10E3 RCM2 31 98 1 CCM1 30 31 15.9E-9 * * Latch Section * RX 80 51 100E3 E1 10 98 (4,6) 1 S1 10 11 (80,51) SLATCH1 R2 11 12 1 C3 12 98 10E-12 E2 13 98 (12,98) 1 R3 12 13 500 * * Power Supply Section * REV. 0 –9– supply Latch | | | | 80 DGND | | | 51 Q | | 45 QNOT | 65 AD8561 GSY1 99 52 POLY(1) (99,50) 4E-3 -2.6E-4 GSY2 52 50 POLY(1) (99,50) 3.7E-3 -.6E-3 RSY 52 51 10 * * Gain Stage Av=250 fp=100MHz * G2 98 20 (12,98) 0.25 R1 20 98 1000 C1 20 98 10E-13 D2 20 21 DX D3 22 20 DX V1 99 21 DC 0.8 V2 22 50 DC 0.8 * * Q Output * Q3 99 41 46 NOX Q4 47 42 50 NOX RB1 43 41 200 RB2 40 42 5E3 CB1 99 41 10E-12 CB2 42 50 5E-12 RO1 46 45 2E3 RO2 47 45 500 EO1 98 43 POLY(1) (20,98) 0 1 EO2 40 98 POLY(1) (20,98) 0 1 * * Q NOT Output * Q5 99 61 66 NOX Q6 67 62 50 NOX RB3 63 61 200 RB4 60 62 5E3 CB3 99 61 10E-12 CB4 62 50 5E-12 RO3 66 65 2E3 RO4 67 65 500 EO3 63 98 POLY(1) (20,98) 0 1 EO4 98 60 POLY(1) (20,98) 0 1 * * MODELS * .MODEL PIX PNP(BF=100,IS=1E-16) .MODEL NOX NPN(BF=100,VAF=130,IS=1E-14) .MODEL DX D(IS=1E-16) .MODEL SLATCH1 VSWITCH(ROFF=1E6,RON=500,VOFF=2.1,VON=1.4) .ENDS AD8561 –10– REV. 0 AD8561 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3220–3–6/98 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 1 4 0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 8-Lead Thin Shrink Small Outline (RU-8) 0.122 (3.10) 0.114 (2.90) 1 5 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 8 4 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0118 (0.30) SEATING PLANE 0.0075 (0.19) 8° 0° 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8-Lead Small Outline IC (SO-8) 8 0.1574 (4.00) 0.1497 (3.80) 1 PIN 1 0.0098 (0.25) 0.0040 (0.10) 5 4 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19) REV. 0 –11– 0.0196 (0.50) x 45° 0.0099 (0.25) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 0.1968 (5.00) 0.1890 (4.80)