a Dual Low Power Frequency Synthesizers ADF4217L/ADF4218L/ADF4219L FEATURES Total I DD: 7.1 mA Bandwidth/RF 3.0 GHz ADF4217L/ADF4218L, IF 1.1 GHz ADF4219L, IF 1.0 GHz 2.6 V to 3.3 V Power Supply 1.8 V Logic Compatibility Separate VP Allows Extended Tuning Voltage Selectable Dual Modulus Prescaler Selectable Charge Pump Currents Charge Pump Current Matching of 1% 3-Wire Serial Interface Power-Down Mode GENERAL DESCRIPTION The ADF4217L/ADF4218L/ADF4219L are low power dual frequency synthesizers that can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual modulus prescaler (P/P + 1). The A and B counters, in conjunction with the dual modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (voltage controlled oscillators). APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA) Wireless LANs Communications Test Equipment Cable TV Tuners (CATV) Control of all the on-chip registers is via a simple 3-wire interface with 1.8 V compatibility. The devices operate with a power supply ranging from 2.6 V to 3.3 V and can be powered down when not in use. FUNCTIONAL BLOCK DIAGRAM ADF4219L ONLY NC VDD1 VDD2 VP1 VP2 N = BP + A 11(13)-BIT IF B COUNTER IFINA IFINB ADF4217L ADF4218L ONLY REFIN PHASE COMPARATOR IF PRESCALER 6(5)-BIT IF A COUNTER DATA LE CHARGE PUMP CPIF OUTPUT MUX MUXOUT CHARGE PUMP CPRF IF LOCK DETECT BUFFER 14(15)-BIT IF R COUNTER CLOCK ADF4217L/ ADF4218L/ ADF4219L 22-BIT DATA SDOUT REGISTER RF LOCK DETECT 14(15)-BIT RF R COUNTER N = BP + A 11(13)-BIT RF B COUNTER RFINA RFINB RF PRESCALER PHASE COMPARATOR 6(5)-BIT RF A COUNTER FEATURES IN ( ) REFER TO ADF4219L NC = NO CONNECT DGNDRF AGNDRF DGNDIF AGNDIF REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS1 (VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.) Parameter B Version 1 BChips2 (Typical) Unit RF CHARACTERISTICS RF Input Frequency (RFIN) ADF4217L, ADF4218L ADF4217L, ADF4218L ADF4219L RF Input Sensitivity ADF4217L, ADF4218L ADF4219L IF Input Frequency (IFIN) ADF4217L/ADF4218L ADF4219L P = 16/17 ADF4219L P = 8/9 IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS Reference Input Frequency Test Conditions/Comments Use a square wave for operation below minimum frequency spec. 0.15/3.0 0.15/2.5 0.8/2.2 0.15/3.0 0.15/2.5 0.8/2.2 GHz min/max GHz min/max GHz min/max –15/0 –20/0 –15/0 –20/0 dBm min/max dBm min/max 0.045/1.1 0.045/1.0 0.045/0.55 –15/0 0.045/1.1 0.045/1.0 0.045/0.55 –15/0 GHz min/max GHz min/max GHz min/max dBm min/max 188 188 MHz max 10/110 10/110 MHz min/max Reference Input Sensitivity 0.5 0.5 V p-p min REFIN Input Capacitance REFIN Input Current 10 ± 100 10 ± 100 pF max µA max PHASE DETECTOR Phase Detector Frequency4 56 56 MHz max CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature 4 1 1 1 6 5 2 4 1 1 1 6 5 2 mA typ mA typ % typ nA typ % max % max % typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Reference Input Current 1.4 0.6 ±1 10 ± 100 1.4 0.6 ±1 10 ± 100 V min V max µA max pF max µA max LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage VDD – 0.4 0.4 VDD – 0.4 0.4 V min V max POWER SUPPLIES VDD1 VDD2 VP1, VP2 IDD (RF + IF)5 (RF only)5 (IF only)5 IP (IP1 + IP2) Low Power Sleep Mode 2.6/3.3 VDD1 VDD1/5.5 V 10 7 5 0.6 1 2.6/3.3 VDD1 VDD1/5.5 V 10 7 5 0.6 1 V min/V max –2– V min/V max mA max mA mA mA typ µA typ –10 dBm minimum input signal –15 dBm minimum input signal –20 dBm minimum input signal –15 dBm minimum input signal –10 dBm minimum input signal –10 dBm minimum input signal For f < 10 MHz, use dc-coupled square wave, (0 to VDD). AC-coupled. When dc-coupled, 0 to VDD max. (CMOS compatible) 0.5 V < VCP < VP – 0.5, 1% typ 0.5 V < VCP < VP – 0.5, 0.1% typ VCP = VP/2 IOH = 1 mA IOL = 1 mA 7.1 mA typ 4.7 mA typ 3.4 mA typ TA = 25°C REV. C ADF4217L/ADF4218L/ADF4219L Parameter BChips2 (Typical) Unit Test Conditions/Comments –171 –163 –167 –159 –171 –163 –167 –159 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ –75 –90 –77 –86 –75 –90 –77 –86 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ 30 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output 1.95 GHz Output; 30 kHz PFD 900 MHz Output; 200 kHz PFD 900 MHz Output; 30 kHz PFD 900 MHz Output; 200 kHz PFD Measured at Offset of fPFD/2fPFD –78/–85 –80/–84 –79/–86 –80/–84 –78/–85 –80/–84 –79/–86 –80/–84 dBc typ dBc typ dBc typ dBc typ B Version 1 6 NOISE CHARACTERISTICS RF Phase Noise Floor7 IF Phase Noise Floor7 Phase Noise Performance8 RF9 RF10 IF11 IF12 Spurious Signals RF9 RF10 IF11 IF12 NOTES 1 Operating temperature range is as follows: B Version: –40°C to +85°C. 2 The BChip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 Guaranteed by design. Sample tested to ensure compliance. 5 This includes relevant I P. 6 VDD = 3 V; P = 16/32; IF IN /RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer. (f REFOUT = 10 MHz @ 0 dBm.) 9 fREFIN = 10 MHz; f PFD = 30 kHz; Offset frequency = 1 kHz; f RF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f RF = 900 MHz; N = 4500; Loop B/W = 20 kHz 11 fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 1 kHz; f IF = 900 MHz; N = 30000; Loop B/W = 3 kHz 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; f IF = 900 MHz; N = 4500; Loop B/W = 20 kHz Specifications subject to change without notice. TIMING CHARACTERISTICS (VDD1 = VDD2 = 3 V ⴞ 10%, 5 V ⴞ 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V ; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V; TA = TMIN to TMAX, unless otherwise noted.) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 10 10 25 25 10 50 ns min ns min ns min ns min ns min ns min DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth Guaranteed by design but not production tested. t3 t4 CLOCK t1 DATA DB21 (MSB) t2 DB20 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram REV. C –3– ADF4217L/ADF4218L/ADF4219L TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4°C/W LGA JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W Lead Temperature, Soldering TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C, unless otherwise noted.) VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . –0.3 V to VP + 0.3 V REFIN, RF1IN (A, B), IFIN (A, B) to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of < 2 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V. ORDERING GUIDE Model Temperature Range Package Description Package Option* ADF4217L/ADF4218L/ADF4219LBRU ADF4217L/ADF4218L/ADF4219LBCC –40°C to +85°C –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) Chip Array CASON (LGA) RU-20 CC-24 *Contact the factory for chip availability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4217L/ ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– REV. C ADF4217L/ADF4218L/ADF4219L PIN CONFIGURATIONS TSSOP TSSOP VDD1 1 20 VDD2 VDD1 1 20 VP1 2 19 VP2 VP1 2 19 VP2 CPRF 3 18 CPIF CPRF 3 18 CPIF DGNDRF 4 17 DGNDIF DGNDRF 4 17 RFINA 5 16 IFINA RFINA 5 16 DGNDIF IFIN RFINB AGNDRF 6 15 IFINB 15 AGNDIF 14 AGNDIF RFINB AGNDRF 6 7 7 14 NC REFIN 8 13 LE REFIN 8 13 DGNDIF 9 12 DGNDIF 9 12 MUXOUT 10 11 DATA CLK MUXOUT 10 11 LE DATA CLK ADF4217L/ ADF4218L ADF4219L VDD2 CHIP SCALE 1 VP1 2 20 CPIF CPRF 3 19 DGNDIF 18 IFINA 17 IFINB 21 NC DGNDRF 4 RFINA 5 RFINB 6 16 AGNDIF AGNDRF 7 15 LE ADF4217L/ ADF4218L DATA 13 NC 10 11 12 CLK 14 9 MUXOUT 8 NC DGNDIF REFIN VP2 23 22 1 21 NC 2 20 CPIF DGNDIF IFIN CPRF 3 19 DGNDRF 4 18 RFINA 5 17 AGNDIF RFINB 6 16 NC AGNDRF 7 15 LE REFIN 8 14 DATA NC 9 13 NC ADF4219L 10 11 12 NC = NO INTERNAL CONNECT NC = NO INTERNAL CONNECT REV. C 24 NC VP1 CLK NC VDD1 22 VDD2 23 DGNDIF VDD2 VP2 24 MUXOUT VDD1 CHIP SCALE –5– ADF4217L/ADF4218L/ADF4219L PIN FUNCTION DESCRIPTIONS Mnemonic Function VDD1 Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD. Output from the RF Charge Pump. When enabled, this provides ± ICP to the external loop filter, which in turn drives the external VCO. Ground Pin for the RF Digital Circuitry Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Ground Pin for the RF Analog Circuitry Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. Ground Pin for the IF Digital, Interface, and Control Circuitry This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to be accessed externally (Table V). Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. Ground Pin for the IF Analog Circuitry This pin is not connected internally (ADF4219L only). Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF (ADF4217L/ADF4218L only). Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO. Ground Pin for the IF Digital, Interface, and Control Circuitry Output from the IF Charge Pump. When enabled, this provides ± ICP to the external loop filter, which in turn drives the external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to VDD. Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V. VDD2 must have the same potential as VDD1. VP 1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN DGNDIF MUXOUT CLK DATA LE AGNDIF NC IFINB IFINA DGNDIF CPIF VP 2 VDD2 –6– REV. C Typical Performance Characteristics–ADF4217L/ADF4218L/ADF4219L 0 0 VDD = 3V VP = 3V –5 REFERENCE LEVEL = –11.2dBm –10 –20 OUTPUT POWER – dB RF INPUT POWER – dBm –10 –15 –20 –25 TA = 25ⴗC –30 VDD = 3V, VP = 5V ICP = 4mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 10 –40 –50 –60 –78dBc –70 –30 –80 –35 –90 –100 –40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 –400kHz –200kHz TPC 1. Input Sensitivity, RF Input 200kHz 400kHz TPC 4. Reference Spurs, RF Side (1960 MHz, 200 kHz, 20 kHz) 10dB/DIVISION –40 0 VDD = 3V VP = 3V –5 1960MHz FREQUENCY RF INPUT FREQUENCY – GHz RL = –40dBc/Hz rms NOISE = 1.2ⴗ –50 PHASE NOISE – dBc/Hz IF INPUT POWER – dBm –60 –10 –15 –20 –25 –30 1.2ⴗ rms –70 –80 –90 –100 –110 –120 –35 –130 –140 100Hz –40 0.1 0.6 1.1 IF INPUT FREQUENCY – GHz 1.6 TPC 2. Input Sensitivity, IF Input 0 –20 –30 –40 VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20 –20 –50 –60 –83dBc/Hz –70 REFERENCE LEVEL = –4.2dBm –10 OUTPUT POWER – dB REFERENCE LEVEL = –11.2dBm –10 OUTPUT POWER – dB 1MHz TPC 5. Integrated Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz) 0 –30 VDD = 3V, VP = 5V ICP = 4mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20 –40 –50 –60 –87dBc/Hz –70 –80 –80 –90 –90 –100 –100 –2kHz –1kHz 1960MHz FREQUENCY 1kHz 2kHz –2kHz –1kHz 900MHz 1kHz 2kHz FREQUENCY TPC 3. Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz) REV. C FREQUENCY OFFSET FROM 1960MHz CARRIER TPC 6. Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz) –7– ADF4217L/ADF4218L/ADF4219L 0 –120 OUTPUT POWER – dB –20 –30 –40 VDD = 3V VP = 5V VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS AVERAGES = 20 –130 PHASE NOISE – dBc/Hz REFERENCE LEVEL = –4.2dBm –10 –50 –60 –70 –140 –150 –160 –83dBc –80 –170 –90 –100 –400kHz –200kHz 900MHz FREQUENCY 200kHz –180 400kHz TPC 7. Reference Spurs, IF Side (900 MHz, 200 kHz, 20 kHz) 10dB/DIVISION –40 RL = –40dBc/Hz 10 100 1000 PHASE DETECTOR FREQUENCY – kHz 1 10000 TPC 10. Phase Noise Referred to CP Output vs. PFD Frequency, IF Side rms NOISE = 0.9ⴗ –60 VDD = 3V VP = 5V –50 –70 PHASE NOISE – dBc/Hz PHASE NOISE – dBc/Hz –60 –70 –80 –90 –100 –110 –80 –90 –120 –130 –140 100Hz FREQUENCY OFFSET FROM 900MHz CARRIER –100 –40 1MHz TPC 8. Integrated Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz) –20 0 20 40 TEMPERATURE – ⴗC 60 100 TPC 11. Phase Noise vs. Temperature, RF Side (1960 MHz, 200 kHz, 20 kHz) –120 –60 VDD = 3V VP = 5V VDD = 3V VP = 5V PHASE NOISE – dBc/Hz –130 PHASE NOISE – dBc/Hz 80 –140 –150 –160 –70 –80 –90 –170 –180 1 10 100 1000 PHASE DETECTOR FREQUENCY – kHz –100 –40 10000 TPC 9. Phase Noise Referred to CP Output vs. PFD Frequency, RF Side –20 0 20 40 TEMPERATURE – ⴗC 60 80 100 TPC 12. Phase Noise vs. Temperature, IF Side (900 MHz, 200 kHz, 20 kHz) –8– REV. C ADF4217L/ADF4218L/ADF4219L 6 VP = 5V ICP = 4mA 4 ICP – mA 2 0 –2 –4 –6 0 0.5 1.0 1.5 2.0 2.5 3.0 VCP – V 3.5 4.0 4.5 5.0 TPC 13. Charge Pump Output Characteristics CIRCUIT DESCRIPTION Reference Input Section Prescaler The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. The prescaler is selectable. On the IF side, it can be set to either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set to 1). On the RF side of the ADF4217L/ADF4218L, it can be set to 64/65 or 32/33. On the ADF4219L, the RF prescaler can be set to 16/17 or 32/33. See Tables V, VI, VIII, and IX. POWER-DOWN CONTROL 50k⍀ NC The dual modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the IF/RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. SW2 REFIN NC BUFFER SW1 TO R COUNTER SW3 NO NC = NORMALLY CLOSED NO = NORMALLY OPEN Figure 2. Reference Input Stage A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The devices are guaranteed to work when the prescaler output is 188 MHz or less. Typically they will work with 250 MHz output from the prescaler. IF/RF Input Stage The IF/RF input stage is shown in Figure 3. It is followed by a two-stage limiting amplifier to generate the CML clock levels needed for the prescaler. N = BP + A 11(13)-BIT B COUNTER TO PFD LOAD 1.6V BIAS GENERATOR FROM IF/RF INPUT STAGE AVDD 500⍀ PRESCALER P/P+1 MODULUS CONTROL 500⍀ LOAD 6(5)-BIT A COUNTER RFINA Figure 4. Reference Input Stage, A and B Counters RFINB AGND Figure 3. IF/RF Input Stage REV. C –9– ADF4217L/ADF4218L/ADF4219L The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: [ MUXOUT AND LOCK DETECT The output multiplexer on the ADF4217L family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11, and P12. See Tables IV and VII. Figure 6 shows the MUXOUT section in block diagram form. ] fVCO = (P × B) + A × fREFIN / R DVDD fVCO = Output frequency of external voltage controlled oscillator (VCO). P = Preset modulus of dual modulus prescaler (8/9, 16/17, and so on). IF ANALOG LOCK DETECT IF R COUNTER OUTPUT B A = Preset divide ratio of binary 11-bit counter (ADF4217L/ ADF4218L), binary 13-bit counter (ADF4219L). IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT MUX MUXOUT CONTROL RF R COUNTER OUTPUT = Preset divide ratio of binary 6-bit A counter (ADF4217L/ ADF4218L), binary 5-bit counter (ADF4219L). RF N COUNTER OUTPUT RF ANALOG LOCK DETECT fREFIN = Output frequency of the external reference frequency oscillator. R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). The ADF4219L has an R divide of 15 bits. DGND Figure 6. MUXOUT Circuit Lock Detect R COUNTER The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. The extra R15 bit on the ADF4219L allows ratios from 1 to 32767. MUXOUT can be programmed for analog lock detect. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, it is high with narrow low going pulses. INPUT SHIFT REGISTER PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic. VP HI D1 Q1 CHARGE PUMP UP U1 R DIVIDER CLR1 DELAY ELEMENT HI The functional block diagram for the ADF4217L family is shown on page 1. The main blocks include a 22-bit input shift register, a 14-bit R counter, and an N counter. The N counter is comprised of a 6-bit A counter and an 11-bit B counter for the ADF4217L and the ADF4218L. The 18-bit N counter on the ADF4219L is comprised of a 13-bit B counter and a 5-bit A counter. Data is clocked into the 22-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I. CP U3 Table I. C2, C1 Truth Table CLR2 DOWN D2 Q2 U2 N DIVIDER CPGND Control Bits C2 C1 Data Latch 0 0 1 1 IF R Counter IF AB Counter (and Prescaler Select) RF R Counter RF AB Counter (and Prescaler Select) 0 1 0 1 R DIVIDER N DIVIDER CP OUTPUT Figure 5. PFD Simplified Schematic –10– REV. C ADF4217L/ADF4218L/ADF4219L Table II. ADF4217L/ADF4218L Family Latch Summary NOT USED IF PD POLARITY IF CP GAIN THREE-STATE CPIF IF LOCK DETECT IF FO IF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P5 P1 CONTROL BITS 14-BIT REFERENCE COUNTER, R R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (0) C1 (0) IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 DB9 DB8 CONTROL BITS 6-BIT A COUNTER DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 B1 DB1 DB0 C2 (0) C1 (1) NOT USED RF PD POLARITY RF CP GAIN THREE-STATE CPIF RF LOCK DETECT RF FO RF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 CONTROL BITS 14-BIT REFERENCE COUNTER, R R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (1) C1 (0) RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 REV. C P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 –11– DB9 B1 DB8 CONTROL BITS 6-BIT A COUNTER DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C1 (1) ADF4217L/ADF4218L/ADF4219L Table III. ADF4219L Family Latch Summary IF PD POLARITY IF CP GAIN THREE-STATE CPIF IF LOCK DETECT IF FO IF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 P3 P2 P5 P1 CONTROL BITS 15-BIT REFERENCE COUNTER, R R15 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (0) C1 (0) IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 5-BIT A COUNTER B5 B4 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 DB1 DB0 C2 (0) C1 (1) RF PD POLARITY RF CP GAIN THREE-STATE CPIF RF LOCK DETECT RF FO RF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 CONTROL BITS 15-BIT REFERENCE COUNTER, R R15 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (1) C1 (0) RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 5-BIT A COUNTER B5 B4 –12– DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C1 (1) REV. C ADF4217L/ADF4218L/ADF4219L Table IV. ADF4217L/ADF4218L/ADF4219L IF Reference Counter Latch Map ADF4219L ONLY IF PD POLARITY IF CP GAIN THREE-STATE CPIF IF FO IF LOCK DETECT IF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P4 REV. C P3 P2 P5 P1 R15 R14 R13 P1 PD POLARITY 0 1 NEGATIVE POSITIVE P5 ICP 0 1 1.0mA 4.0mA P2 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE CONTROL BITS 14-BIT REFERENCE COUNTER, R R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (0) C1 (0) R15 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 .......... 0 0 1 1 0 0 0 0 .......... 0 1 0 2 0 0 0 0 .......... 0 1 1 3 0 0 0 0 .......... 1 0 0 4 . . . . .......... . . . . . . . . .......... . . . . . . . . .......... . . . . 0 1 1 1 .......... 1 0 0 16380 0 1 1 1 .......... 1 0 1 16381 0 1 1 1 .......... 1 1 0 16382 0 1 1 1 .......... 1 1 1 16383 . . . . .......... . . . . 1 1 1 1 .......... 1 1 1 32767 P12 P11 FROM RF R LATCH P4 P3 MUXOUT 0 0 0 0 LOGIC LOW STATE 0 0 0 1 IF ANALOG LOCK DETECT 0 X 1 0 IF REFERENCE DIVIDER OUTPUT 0 X 1 1 IF N DIVIDER OUTPUT 0 1 0 0 RF ANALOG LOCK DETECT 0 1 0 1 RF/IF ANALOG LOCK DETECT 1 X 0 0 RF REFERENCE DIVIDER 1 X 0 1 RF N DIVIDER 1 0 1 0 FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT 1 0 1 1 IF COUNTER RESET 1 1 1 0 RF COUNTER RESET 1 1 1 1 IF AND RF COUNTER RESET –13– ADF4217L/ADF4218L/ADF4219L Table V. ADF4217L/ADF4218L IF AB Counter Latch Map IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB9 B2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 B1 A5 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 0 62 1 1 1 1 1 1 63 B10 B9 .......... B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 .......... 0 0 1 NOT ALLOWED 0 0 0 .......... 0 1 0 NOT ALLOWED 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 2044 1 1 1 .......... 1 0 1 2045 1 1 1 .......... 1 1 0 2046 1 1 1 .......... 1 1 1 2047 IF PRESCALER 8/9 16/17 P7 IF SECTION 0 1 NORMAL OPERATION POWER-DOWN DB0 0 0 0 1 DB1 C2 (0) C1 (1) A6 B11 P6 CONTROL BITS 6-BIT A COUNTER N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 – P). –14– REV. C ADF4217L/ADF4218L/ADF4219L Table VI. ADF4219L IF AB Counter Latch Map IF PRESCALER IF POWER-DOWN IF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P7 P6 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 . 1 . 1 . 1 . 1 . 0 . 30 1 1 1 1 1 31 B11 .......... B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 .......... 0 0 1 NOT ALLOWED 0 0 0 .......... 0 1 0 NOT ALLOWED 0 0 0 .......... 0 1 1 3 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 8/9 16/17 P7 IF SECTION 0 1 NORMAL OPERATION POWER-DOWN N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N, NMIN IS (P2– P). REV. C C2 (0) C1 (1) A4 B12 IF PRESCALER DB0 0 0 0 1 DB1 A5 B13 P6 CONTROL BITS 5-BIT A COUNTER –15– ADF4217L/ADF4218L/ADF4219L Table VII. RF Reference Counter Latch Map ADF4129L ONLY RF PD POLARITY RF CP GAIN RF FO RF LOCK DETECT THREE-STATE CPIF RF REFERENCE COUNTER LATCH DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P12 P11 P10 P13 P9 R15 0 1 NEGATIVE POSITIVE ICP 1.0mA 4.0mA P10 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE P11 0 0 0 R13 PD POLARITY 0 1 P12 0 R14 P9 P13 CONTROL BITS 14-BIT REFERENCE COUNTER, R P4 P3 FROM RF R LATCH R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 R8 R7 R6 R5 R4 R3 R2 R1 DB1 DB0 C2 (1) C1 (0) R15 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 .......... 0 0 1 1 0 0 0 0 .......... 0 1 0 2 0 0 0 0 .......... 0 1 1 3 0 0 0 0 .......... 1 0 0 4 . . . . .......... . . . . . . . . .......... . . . . . . . . .......... . . . . 0 1 1 1 .......... 1 0 0 16380 0 1 1 1 .......... 1 0 1 16381 0 1 1 1 .......... 1 1 0 16382 0 1 1 1 .......... 1 1 1 16383 . . . . .......... . . . . 1 1 1 1 .......... 1 1 1 32767 0 0 MUXOUT LOGIC LOW STATE 0 0 1 IF ANALOG LOCK DETECT X 1 0 IF REFERENCE DIVIDER OUTPUT 0 X 1 1 IF N DIVIDER OUTPUT 0 1 0 0 RF ANALOG LOCK DETECT 0 1 0 1 RF/IF ANALOG LOCK DETECT 1 X 0 0 RF REFERENCE DIVIDER 1 X 0 1 RF N DIVIDER 1 0 1 0 FAST LOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT 1 0 1 1 IF COUNTER RESET 1 1 1 0 RF COUNTER RESET 1 1 1 1 IF AND RF COUNTER RESET –16– REV. C ADF4217L/ADF4218L/ADF4219L Table VIII. ADF4217L/ADF4218L RF AB Counter Latch Map RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH NOT USED 11-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B11 B10 B9 B8 B7 B6 B5 B4 B3 DB9 B2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 A6 A5 A4 A3 A2 A1 B1 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 1 1 3 . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 0 62 1 1 1 1 1 1 63 B9 B2 B1 B COUNTER DIVIDE RATIO 0 .......... .......... B3 0 0 0 1 NOT ALLOWED 0 0 0 .......... 0 1 0 NOT ALLOWED 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 2044 1 1 1 .......... 1 0 1 2045 1 1 1 .......... 1 1 0 2046 1 1 1 .......... 1 1 1 2047 0 1 64/65 32/33 32/33 64/65 P16 RF SECTION 0 1 NORMAL OPERATION POWER-DOWN C2 (1) C1 (1) A5 B10 RF PRESCALER ADF4218L N = BP + A, P IS PRESCALER VALUE SET BY P6, B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF NⴛFREF , N MIN IS (P2 – P). REV. C –17– DB0 0 0 RF PRESCALER ADF4217L DB1 A6 B11 P14 CONTROL BITS 6-BIT A COUNTER ADF4217L/ADF4218L/ADF4219L Table IX. ADF4219L RF AB Counter Latch Map RF PRESCALER RF POWER-DOWN RF AB COUNTER LATCH 13-BIT B COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 P16 P14 B13 B12 B11 B10 B9 B8 B7 B6 B5 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B3 B2 B1 A5 A4 A3 A2 A1 B4 A4 A3 A2 A1 A COUNTER DIVIDE RATIO 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 . . . . . . 1 1 1 1 0 30 1 1 1 1 1 31 B12 B11 .......... B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 .......... 0 0 1 NOT ALLOWED 0 0 0 .......... 0 1 0 NOT ALLOWED 0 0 0 .......... 0 1 1 3 0 0 0 .......... 1 0 0 4 . . . .......... . . . . . . . .......... . . . . . . . .......... . . . . 1 1 1 .......... 1 0 0 8188 1 1 1 .......... 1 0 1 8189 1 1 1 .......... 1 1 0 8190 1 1 1 .......... 1 1 1 8191 IF PRESCALER 16/17 32/33 P16 IF SECTION 0 1 NORMAL OPERATION POWER-DOWN DB0 0 0 0 1 DB1 C2 (1) C1 (1) A5 B13 P14 CONTROL BITS 5-BIT A COUNTER N = BP + A, P IS PRESCALER VALUE SET BY P14. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTIGUOUS VALUES OF N, NMIN IS (P2–P). A MUST BE LESS THAN P. –18– REV. C ADF4217L/ADF4218L/ADF4219L PROGRAM MODES Tables IV and VII show how to set up the program modes in the ADF4217L family. The following should be noted: The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked, and either IF or RF Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the IF/RF Analog Lock Detect is chosen, the locked condition is indicated only when both IF and RF loops are locked. The IF/RF section of the devices will return to normal powered-up operation immediately upon LE latching a “0” to the appropriate power-down bit. 2. The IF Counter Reset Mode resets the R and N counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset Mode resets the R and N counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset Mode does both of the above. If control bits C2, C1 are 0, 0, then the data is transferred from the input shift register to the 14-bit IF R counter. Table IV shows the input shift register data format for the IF R counter and the possible divide ratios. Upon removal of the reset bits, the N counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). 3. The Fastlock Mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to 1. POWER-DOWN It is possible to program the ADF4217L family for either synchronous or asynchronous power-down on either the IF or RF side. Synchronous IF Power-Down Programming a “1” to P7 of the ADF4217L family will initiate a power-down. If P2 of the ADF4217L family has been set to “0” (normal operation), then a synchronous power-down is conducted. The device will automatically put the charge pump into threestate and then complete the power-down. Asynchronous IF Power-Down IF SECTION Programmable IF Reference (R) Counter IF Phase Detector Polarity P1 sets the IF phase detector polarity. When the IF VCO characteristics are positive, this should be set to “1.” When they are negative, it should be set to “0.” See Table IV. IF Charge Pump Three-State P2 puts the IF charge pump into three-state mode when programmed to a “1.” It should be set to “0” for normal operation. See Table IV. IF Charge Pump Currents P5 sets the IF charge pump current. With P5 set to “0,” ICP is 1.0 mA. With P5 set to “1,” ICP is 4.0 mA. See Table IV. Programmable IF AB Counter If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. For the ADF4217L/ADF4218L, the AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table V shows the input register data format for programming the IF AB counter and the possible divide ratios. The ADF4219L N counter consists of an 13-bit B counter and 5-bit A counter. Table VI shows the input register data format for programming the ADF4219L. If P2 of the ADF4217L family has been set to “1” (three-state the IF charge pump) and P7 is subsequently set to “1,” an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the “1” to the IF PowerDown Bit (P7). IF Prescaler Value Synchronous RF Power-Down Tables IV, V, and VI show the power-down bits in the ADF4217L family. See the Power-Down section for a functional description. Programming a “1” to P16 of the ADF4217L family will initiate a power-down. If P10 of the ADF4217L family has been set to “0” (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and then complete the power-down. Asynchronous RF Power-Down If P10 of the ADF4217L family has been set to “1” (three-state the RF charge pump) and P16 is subsequently set to “1,” an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the “1” to the RF Power-Down Bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop’s R and N dividers to their load state conditions, and the IF/RF input section is debiased to a high impedance state. REV. C P6 in the IF AB counter latch sets the IF prescaler value. For the ADF4217L family, 8/9 or 16/17 prescalers are available. See Table V and Table VI. IF Power-Down RF SECTION Programmable RF Reference (R) Counter If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RF R counter. Table VII shows the input shift register data format for the RF R counter and the possible divide ratios. RF Phase Detector Polarity P9 sets the RF phase detector polarity. When the RF VCO characteristics are positive, this should be set to “1.” When they are negative, it should be set to “0.” See Table VII. RF Charge Pump Three-State P10 puts the RF charge pump into three-state mode when programmed to a “1.” It should be set to “0” for normal operation. See Table VII. –19– ADF4217L/ADF4218L/ADF4219L RF Program Modes program the new frequency and to initiate Fastlock. To come out of Fastlock, the RF CP Gain Bit should be returned to “0” and the extra damping resistor switched out. Tables IV and VII show how to set up the RF program modes. RF Charge Pump Currents P13 sets the RF charge pump current. With P13 set to “0,” ICP is 1.0 mA. With P13 set to “1,” ICP is 4.0 mA. See Table VII. Programmable RF AB Counter If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF AB counter. For the ADF4217L/ADF4218L, the AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table VIII shows the input register data format for programming the RF AB counter and the possible divide ratios. The ADF4219L N counter consists of a 13-bit B counter and 5-bit A counter. Table IX shows the input register data format for programming the ADF4219L. RF Prescaler Value P14 in the RF AB counter latch sets the RF prescaler value. For the ADF4217L and ADF4218L family, 32/33 or 64/65 prescalers are available. See Table VIII. For the ADF4219L, the prescaler may be 16/17 or 32/33. See Table IX. RF Power-Down Tables VII, VIII, and IX show the power-down bits (Charge Pump Bit used for asynchronous in the ADF4217L family). See the Power-Down section for a functional description. RF Fastlock The RF CP Gain Bit (P13) of the RF N Register in the ADF4217L family is the Fastlock Enable Bit. The loop filter should be designed for the lower current setting. When Fastlock is enabled, the RF CP current is set to maximum value. Also, an extra loop filter damping resistor to ground is switched in using the MUXOUT pin, thus compensating for the change of loop dynamics when in Fastlock Mode. Since the RF CP Gain Bit is contained in the RF N counter, only one write is needed to APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver The diagram in Figure 7 shows the ADF4217L/ADF4218L/ ADF4219L being used in a classic superheterodyne receiver to provide the required LOs (local oscillators). In this circuit, the reference input signal is applied to the circuit at fREFIN and is being generated by a 13 MHz temperature controlled crystal oscillator. In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference counter. The RF output frequency range is 1050 MHz to 1085 MHz. Loop filter component values are chosen so that the loop bandwidth is 20 kHz. The synthesizer is set up for a charge pump current of 4.0 mA, and the VCO sensitivity is 15.6 MHz/V. The IF output is fixed at 125 MHz. The IF loop bandwidth is chosen to be 20 kHz with a channel spacing of 200 kHz. Loop filter component values are chosen accordingly. Local Oscillator for WCDMA Receiver Figure 8 shows the ADF4217L/ADF4218L/ADF4219L being used to generate the local oscillator frequencies in a wideband CDMA (WCDMA) system. The RF output range needed is 1720 MHz to 1780 MHz. The VCO190-1750T from Varil-L will accomplish that. Channel spacing is 200 kHz, the loop bandwidth of the loop filter is 20 kHz, and the VCO sensitivity is 32 MHz/V. A charge pump current of 4.0 mA is used and the desired phase margin for the loop is 45 degrees. The IF output is fixed at 200 MHz. The VCO190-200T is used. It has a sensitivity of 11.5 MHz/V. Channel spacing and loop bandwidth are chosen the same as the RF side. RFOUT IFOUT VP VDD VP 100pF 18⍀ 100pF VDD2 VDD1 620pF 9k⍀ VP1 3.3k⍀ 400pF 620pF ADF4217L/ ADF4218L/ ADF4219L 3.9nF 5.8k⍀ MUXOUT VDD 10MHz TCXO VCO190-1068U 620pF 18⍀ 18⍀ 18⍀ LOCK DETECT 100pF RFIN IFIN REFIN 100pF 6nF 100pF 51⍀ VCC CPRF CPIF VCO190-125T 18⍀ VP2 3.3k⍀ VCC DGNDRF AGNDRF DGNDIF AGNDIF 18⍀ 100pF CLK DATA LE 51⍀ SPI COMPATIBLE SERIAL BUS DECOUPLING CAPACITORS (22F/10pF) ON VDD, VP OF THE ADF4217L/ADF4218L/ADF4219L. THE TCXO AND ON V CC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 7. Local Oscillator Design for GSM Receiver –20– REV. C ADF4217L/ADF4218L/ADF4219L RFOUT IFOUT VP VDD VP 100pF 18⍀ 100pF 18⍀ 100pF VDD2 VDD1 450pF 1.5k⍀ VP1 3.3k⍀ 2.4pF 760pF 4.7k⍀ ADF4217L/ ADF4218L/ ADF4219L 24nF MUXOUT DGNDRF AGNDRF DGNDIF AGNDIF 10MHz TCXO VCO190-1750T 690pF 18⍀ 18⍀ LOCK DETECT 100pF RFIN IFIN REFIN 18⍀ 7.5nF 100pF 51⍀ 100pF VCC CPRF CPIF VCO190-200T 18⍀ VP2 3.3k⍀ VCC CLK DATA LE 51⍀ SPI COMPATIBLE SERIAL BUS DECOUPLING CAPACITORS (22F/10pF) ON VDD , VP OF THE ADF4217L/ADF4218L/ADF4219L. THE TCXO AND ON V CC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. Figure 8. Local Oscillator Design for WCDMA System In this circuit, the reference input signal is applied to the circuit at REFIN by a 10 MHz TCXO (temperature controlled crystal oscillator). SCLK CLK MOSI DATA LE ADF4217L/ ADuC812 INTERFACING The ADF4217L/ADF4218L/ADF4219L family has a simple SPI® compatible serial interface for writing to the device. SCLK, SDATA, and LE control the data transfer. When LE (latch enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will get transferred to the appropriate latch. See Figure 1 for the timing diagram and Table I for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 µs. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds. ADuC812 Interface Figure 9 shows the interface to the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF421xL family needs a 22-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. MUXOUT (LOCK DETECT) Figure 9. ADuC812 to ADF421xL Interface ADSP2181 Interface Figure 10 shows the interface between the ADF4217L family and the ADSP-21xx digital signal processor. As previously discussed, the ADF4217L family needs a 22-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 22-bit word. To program each 22-bit latch, store the three 8-bit bytes, enable the Autobuffered Mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. SCLK DT TFS ADSP-21xx On first applying power to the ADF4217L family, it needs four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 side) for the output to become active. I/O FLAG When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz. REV. C ADF4218L/ ADF4219L I/O PORTS CLK DATA LE ADF4217L/ ADF4218L/ ADF4219L MUXOUT (LOCK DETECT) Figure 10. ADSP-21xx to ADF421xL Interface –21– ADF4217L/ADF4218L/ADF4219L OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 1 6.40 BSC 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 0.20 0.09 0.30 COPLANARITY 0.19 0.10 SEATING PLANE 0.75 0.60 0.45 8ⴗ 0ⴗ COMPLIANT TO JEDEC STANDARDS MO-153AC 24-Leadless Chip Array CASON [LGA] (CC-24) Dimensions shown in millimeters SEATING PLANE 1.20 MAX 4.50 BSC VIEW A 3.50 BSC TOP VIEW PIN 1 INDEX AREA 1.15 0.90 0.50 BSC TYP 0.05 MAX 0.10 TYP 1 0.60 0.40 24 BOTTOM VIEW 0.33 0.30 0.25 VIEW A COMPLIANT TO JEDEC STANDARDS MO-208, ECEA-1 –22– REV. C ADF4217L/ADF4218L/ADF4219L Revision History Location Page 5/03—Data Sheet changed from REV. B to REV. C. Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to TPC 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Change to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7/02—Data Sheet changed from REV. A to REV. B. Change to ADF4219L SENSITIVITY SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6/02—Data Sheet changed from REV. 0 to REV. A. Changes to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to CASON package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REV. C –23– –24– C02655–0–5/03(C)